OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [inst-set-test/] [is-lws-test.S] - Blame information for rev 112

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 107 jeremybenn
/* is-lws-test.S. l.lws instruction test of Or1ksim
2
 *
3
 * Copyright (C) 1999-2006 OpenCores
4
 * Copyright (C) 2010 Embecosm Limited
5
 *
6
 * Contributors various OpenCores participants
7
 * Contributor Jeremy Bennett 
8
 *
9
 * This file is part of OpenRISC 1000 Architectural Simulator.
10
 *
11
 * This program is free software; you can redistribute it and/or modify it
12
 * under the terms of the GNU General Public License as published by the Free
13
 * Software Foundation; either version 3 of the License, or (at your option)
14
 * any later version.
15
 *
16
 * This program is distributed in the hope that it will be useful, but WITHOUT
17
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
 * more details.
20
 *
21
 * You should have received a copy of the GNU General Public License along
22
 * with this program.  If not, see .
23
 */
24
 
25
/* ----------------------------------------------------------------------------
26
 * Coding conventions
27
 *
28
 * A simple rising stack is provided starting at _stack and pointed to by
29
 * r1. r1 points to the next free word. Only 32-bit registers may be pushed
30
 * onto the stack.
31
 *
32
 * Local labels up to 49 are reserved for macros. Each is used only once in
33
 * all macros. You can get in a serious mess if you get local label clashing
34
 * in macros.
35
 *
36
 * Arguments to functions are passed in r3 through r8.
37
 * r9 is the link (return address)
38
 * r11 is for returning results
39
 *
40
 * Only r1 and r2 are preserved across function calls. It is up to the callee
41
 * to save any other registers required.
42
 * ------------------------------------------------------------------------- */
43
 
44
/* ----------------------------------------------------------------------------
45
 * Test coverage
46
 *
47
 * The l.lws instruction was omitted from Or1ksim originally. It is specified
48
 * for ORBIS32, even though it is functionally equivalent to l.lwz.
49
 *
50
 * Having fixed the problem, this is (in good software engineering style), a
51
 * regresison test to go with the fix.
52
 *
53
 * Of course what is really needed is a comprehensive instruction test...
54
 * ------------------------------------------------------------------------- */
55
 
56
 
57
#include "inst-set-test.h"
58
 
59
/* ----------------------------------------------------------------------------
60
 * Test of load single word and extend with sign: l.lws
61
 * ------------------------------------------------------------------------- */
62
        .section .rodata
63
        .balign 4
64
50:     .word   0xdeadbeef
65
51:     .word   0x00000000
66
52:     .word   0x7fffffff
67
53:     .word   0x80000000
68
54:     .word   0xffffffff
69
 
70
        .section .text
71
        .global _start
72
_start:
73
        LOAD_STR (r3, "l.lws\n")
74
        l.jal   _puts
75
        l.nop
76
 
77
        /* Load with zero offset */
78
        LOAD_CONST (r5,50b)
79
        l.lws   r4,0(r5)
80
        CHECK_RES (" l.lws r4,0(r5): r4=0xdeadbeef:  ", r4, 0xdeadbeef)
81
 
82
        LOAD_CONST (r5,51b)
83
        l.lws   r4,0(r5)
84
        CHECK_RES (" l.lws r4,0(r5): r4=0x00000000:  ", r4, 0x00000000)
85
 
86
        LOAD_CONST (r5,52b)
87
        l.lws   r4,0(r5)
88
        CHECK_RES (" l.lws r4,0(r5): r4=0x7fffffff:  ", r4, 0x7fffffff)
89
 
90
        LOAD_CONST (r5,53b)
91
        l.lws   r4,0(r5)
92
        CHECK_RES (" l.lws r4,0(r5): r4=0x80000000:  ", r4, 0x80000000)
93
 
94
        LOAD_CONST (r5,54b)
95
        l.lws   r4,0(r5)
96
        CHECK_RES (" l.lws r4,0(r5): r4=0xffffffff:  ", r4, 0xffffffff)
97
 
98
        /* Load with positive offset */
99
        LOAD_CONST (r5,50b)
100
        l.lws   r4,4(r5)
101
        CHECK_RES (" l.lws r4,0(r5): r4=0x00000000:  ", r4, 0x00000000)
102
 
103
        LOAD_CONST (r5,50b)
104
        l.lws   r4,8(r5)
105
        CHECK_RES (" l.lws r4,0(r5): r4=0x7fffffff:  ", r4, 0x7fffffff)
106
 
107
        LOAD_CONST (r5,50b)
108
        l.lws   r4,12(r5)
109
        CHECK_RES (" l.lws r4,0(r5): r4=0x80000000:  ", r4, 0x80000000)
110
 
111
        LOAD_CONST (r5,50b)
112
        l.lws   r4,16(r5)
113
        CHECK_RES (" l.lws r4,0(r5): r4=0xffffffff:  ", r4, 0xffffffff)
114
 
115
        /* Load with negative offset */
116
        LOAD_CONST (r5,54b)
117
        l.lws   r4,-16(r5)
118
        CHECK_RES (" l.lws r4,0(r5): r4=0xdeadbeef:  ", r4, 0xdeadbeef)
119
 
120
        LOAD_CONST (r5,54b)
121
        l.lws   r4,-12(r5)
122
        CHECK_RES (" l.lws r4,0(r5): r4=0x00000000:  ", r4, 0x00000000)
123
 
124
        LOAD_CONST (r5,54b)
125
        l.lws   r4,-8(r5)
126
        CHECK_RES (" l.lws r4,0(r5): r4=0x7fffffff:  ", r4, 0x7fffffff)
127
 
128
        LOAD_CONST (r5,54b)
129
        l.lws   r4,-4(r5)
130
        CHECK_RES (" l.lws r4,0(r5): r4=0x80000000:  ", r4, 0x80000000)
131
 
132
/* ----------------------------------------------------------------------------
133
 * All done
134
 * ------------------------------------------------------------------------- */
135
_exit:
136
        LOAD_STR (r3, "Test completed\n")
137
        l.jal   _puts
138
        l.nop
139
 
140
        TEST_EXIT

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.