| 1 |
122 |
jeremybenn |
/* is-div-test.S. l.div and l.divu instruction test of Or1ksim
|
| 2 |
|
|
*
|
| 3 |
|
|
* Copyright (C) 1999-2006 OpenCores
|
| 4 |
|
|
* Copyright (C) 2010 Embecosm Limited
|
| 5 |
|
|
*
|
| 6 |
|
|
* Contributors various OpenCores participants
|
| 7 |
|
|
* Contributor Jeremy Bennett
|
| 8 |
|
|
*
|
| 9 |
|
|
* This file is part of OpenRISC 1000 Architectural Simulator.
|
| 10 |
|
|
*
|
| 11 |
|
|
* This program is free software; you can redistribute it and/or modify it
|
| 12 |
|
|
* under the terms of the GNU General Public License as published by the Free
|
| 13 |
|
|
* Software Foundation; either version 3 of the License, or (at your option)
|
| 14 |
|
|
* any later version.
|
| 15 |
|
|
*
|
| 16 |
|
|
* This program is distributed in the hope that it will be useful, but WITHOUT
|
| 17 |
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 18 |
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
| 19 |
|
|
* more details.
|
| 20 |
|
|
*
|
| 21 |
|
|
* You should have received a copy of the GNU General Public License along
|
| 22 |
|
|
* with this program. If not, see .
|
| 23 |
|
|
*/
|
| 24 |
|
|
|
| 25 |
|
|
/* ----------------------------------------------------------------------------
|
| 26 |
|
|
* Coding conventions are described in inst-set-test.S
|
| 27 |
|
|
* ------------------------------------------------------------------------- */
|
| 28 |
|
|
|
| 29 |
|
|
/* ----------------------------------------------------------------------------
|
| 30 |
|
|
* Test coverage
|
| 31 |
|
|
*
|
| 32 |
|
|
* The l.ror and l.rori instructions were missing from Or1ksim.
|
| 33 |
|
|
*
|
| 34 |
|
|
* Having fixed the problem, this is (in good software engineering style), a
|
| 35 |
|
|
* regresison test to go with the fix.
|
| 36 |
|
|
*
|
| 37 |
|
|
* This is not a comprehensive test of either instruction (yet).
|
| 38 |
|
|
*
|
| 39 |
|
|
* Of course what is really needed is a comprehensive instruction test...
|
| 40 |
|
|
* ------------------------------------------------------------------------- */
|
| 41 |
|
|
|
| 42 |
|
|
|
| 43 |
|
|
#include "inst-set-test.h"
|
| 44 |
|
|
|
| 45 |
|
|
/* ----------------------------------------------------------------------------
|
| 46 |
|
|
* A macro to carry out a test of rotate right
|
| 47 |
|
|
*
|
| 48 |
|
|
* Arguments
|
| 49 |
|
|
* op1: First operand value
|
| 50 |
|
|
* op2: Second operand value
|
| 51 |
|
|
* res: Expected result
|
| 52 |
|
|
* ------------------------------------------------------------------------- */
|
| 53 |
|
|
#define TEST_ROR(op1, op2, res) \
|
| 54 |
|
|
LOAD_CONST (r5,op1) /* Load numbers to rotate */ ;\
|
| 55 |
|
|
LOAD_CONST (r6,op2) ;\
|
| 56 |
|
|
l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\
|
| 57 |
|
|
50: l.ror r4,r5,r6 ;\
|
| 58 |
|
|
l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\
|
| 59 |
|
|
PUSH (r5) /* Save EPCR for later */ ;\
|
| 60 |
|
|
PUSH (r4) /* Save result for later */ ;\
|
| 61 |
|
|
;\
|
| 62 |
|
|
PUTS (" 0x") ;\
|
| 63 |
|
|
PUTH (op1) ;\
|
| 64 |
|
|
PUTS (" ROR 0x") ;\
|
| 65 |
|
|
PUTH (op2) ;\
|
| 66 |
|
|
PUTS (" = 0x") ;\
|
| 67 |
|
|
PUTH (res) ;\
|
| 68 |
|
|
PUTS (": ") ;\
|
| 69 |
|
|
POP (r4) ;\
|
| 70 |
|
|
CHECK_RES1 (r4, res) ;\
|
| 71 |
|
|
;\
|
| 72 |
|
|
POP (r2) /* Retrieve EPCR */ ;\
|
| 73 |
|
|
LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\
|
| 74 |
|
|
l.and r2,r2,r4 ;\
|
| 75 |
|
|
l.sfeq r2,r4 ;\
|
| 76 |
|
|
l.bnf 51f ;\
|
| 77 |
|
|
;\
|
| 78 |
|
|
PUTS (" - exception triggered: TRUE\n") ;\
|
| 79 |
|
|
l.j 52f ;\
|
| 80 |
|
|
l.nop ;\
|
| 81 |
|
|
;\
|
| 82 |
|
|
51: PUTS (" - exception triggered: FALSE\n") ;\
|
| 83 |
|
|
52:
|
| 84 |
|
|
|
| 85 |
|
|
|
| 86 |
|
|
/* ----------------------------------------------------------------------------
|
| 87 |
|
|
* A macro to carry out a test of rotate right immediate
|
| 88 |
|
|
*
|
| 89 |
|
|
* Arguments
|
| 90 |
|
|
* op1: First operand value
|
| 91 |
|
|
* op2: Second operand value
|
| 92 |
|
|
* res: Expected result
|
| 93 |
|
|
* ------------------------------------------------------------------------- */
|
| 94 |
|
|
#define TEST_RORI(op1, op2, res) \
|
| 95 |
|
|
LOAD_CONST (r5,op1) /* Load numbers to rotate */ ;\
|
| 96 |
|
|
l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\
|
| 97 |
|
|
53: l.rori r4,r5,op2 ;\
|
| 98 |
|
|
l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\
|
| 99 |
|
|
PUSH (r5) /* Save EPCR for later */ ;\
|
| 100 |
|
|
PUSH (r4) /* Save result for later */ ;\
|
| 101 |
|
|
;\
|
| 102 |
|
|
PUTS (" 0x") ;\
|
| 103 |
|
|
PUTH (op1) ;\
|
| 104 |
|
|
PUTS (" RORI 0x") ;\
|
| 105 |
|
|
PUTHQ (op2) ;\
|
| 106 |
|
|
PUTS (" = 0x") ;\
|
| 107 |
|
|
PUTH (res) ;\
|
| 108 |
|
|
PUTS (": ") ;\
|
| 109 |
|
|
POP (r4) ;\
|
| 110 |
|
|
CHECK_RES1 (r4, res) ;\
|
| 111 |
|
|
;\
|
| 112 |
|
|
POP (r2) /* Retrieve EPCR */ ;\
|
| 113 |
|
|
LOAD_CONST (r4, 53b) /* The opcode of interest */ ;\
|
| 114 |
|
|
l.and r2,r2,r4 ;\
|
| 115 |
|
|
l.sfeq r2,r4 ;\
|
| 116 |
|
|
l.bnf 54f ;\
|
| 117 |
|
|
;\
|
| 118 |
|
|
PUTS (" - exception triggered: TRUE\n") ;\
|
| 119 |
|
|
l.j 55f ;\
|
| 120 |
|
|
l.nop ;\
|
| 121 |
|
|
;\
|
| 122 |
|
|
54: PUTS (" - exception triggered: FALSE\n") ;\
|
| 123 |
|
|
55:
|
| 124 |
|
|
|
| 125 |
|
|
|
| 126 |
|
|
/* ----------------------------------------------------------------------------
|
| 127 |
|
|
* Start of code
|
| 128 |
|
|
* ------------------------------------------------------------------------- */
|
| 129 |
|
|
.section .text
|
| 130 |
|
|
.global _start
|
| 131 |
|
|
_start:
|
| 132 |
|
|
|
| 133 |
|
|
/* ----------------------------------------------------------------------------
|
| 134 |
|
|
* Test of rotate right, l.ror
|
| 135 |
|
|
* ------------------------------------------------------------------------- */
|
| 136 |
|
|
_ror:
|
| 137 |
|
|
LOAD_STR (r3, "l.ror\n")
|
| 138 |
|
|
l.jal _puts
|
| 139 |
|
|
l.nop
|
| 140 |
|
|
|
| 141 |
|
|
/* Rotate by zero */
|
| 142 |
|
|
TEST_ROR (0xb38f0f83, 0x00000000, 0xb38f0f83)
|
| 143 |
|
|
|
| 144 |
|
|
/* Rotate by amounts in the 1 - 31 range. */
|
| 145 |
|
|
TEST_ROR (0xb38f0f83, 0x00000001, 0xd9c787c1)
|
| 146 |
|
|
TEST_ROR (0xb38f0f83, 0x00000004, 0x3b38f0f8)
|
| 147 |
|
|
TEST_ROR (0xb38f0f83, 0x00000010, 0x0f83b38f)
|
| 148 |
|
|
TEST_ROR (0xb38f0f83, 0x0000001f, 0x671e1f07)
|
| 149 |
|
|
|
| 150 |
|
|
/* Rotate by larger amounts - should be masked. */
|
| 151 |
|
|
TEST_ROR (0xb38f0f83, 0x00000021, 0xd9c787c1)
|
| 152 |
|
|
TEST_ROR (0xb38f0f83, 0x00002224, 0x3b38f0f8)
|
| 153 |
|
|
TEST_ROR (0xb38f0f83, 0x00f789f0, 0x0f83b38f)
|
| 154 |
|
|
TEST_ROR (0xb38f0f83, 0xffffffff, 0x671e1f07)
|
| 155 |
|
|
|
| 156 |
|
|
|
| 157 |
|
|
/* ----------------------------------------------------------------------------
|
| 158 |
|
|
* Test of rotate right immediate, l.rori
|
| 159 |
|
|
* ------------------------------------------------------------------------- */
|
| 160 |
|
|
_rori:
|
| 161 |
|
|
LOAD_STR (r3, "l.rori\n")
|
| 162 |
|
|
l.jal _puts
|
| 163 |
|
|
l.nop
|
| 164 |
|
|
|
| 165 |
|
|
/* Rotate by zero */
|
| 166 |
|
|
TEST_RORI (0xb38f0f83, 0x00000000, 0xb38f0f83)
|
| 167 |
|
|
|
| 168 |
|
|
/* Rotate by amounts in the 1 - 31 range. */
|
| 169 |
|
|
TEST_RORI (0xb38f0f83, 0x01, 0xd9c787c1)
|
| 170 |
|
|
TEST_RORI (0xb38f0f83, 0x04, 0x3b38f0f8)
|
| 171 |
|
|
TEST_RORI (0xb38f0f83, 0x10, 0x0f83b38f)
|
| 172 |
|
|
TEST_RORI (0xb38f0f83, 0x1f, 0x671e1f07)
|
| 173 |
|
|
|
| 174 |
|
|
/* Rotate by larger amounts (32 - 63) - should be masked. */
|
| 175 |
|
|
TEST_RORI (0xb38f0f83, 0x21, 0xd9c787c1)
|
| 176 |
|
|
TEST_RORI (0xb38f0f83, 0x24, 0x3b38f0f8)
|
| 177 |
|
|
TEST_RORI (0xb38f0f83, 0x30, 0x0f83b38f)
|
| 178 |
|
|
TEST_RORI (0xb38f0f83, 0x3f, 0x671e1f07)
|
| 179 |
|
|
|
| 180 |
|
|
|
| 181 |
|
|
/* ----------------------------------------------------------------------------
|
| 182 |
|
|
* All done
|
| 183 |
|
|
* ------------------------------------------------------------------------- */
|
| 184 |
|
|
_exit:
|
| 185 |
|
|
LOAD_STR (r3, "Test completed\n")
|
| 186 |
|
|
l.jal _puts
|
| 187 |
|
|
l.nop
|
| 188 |
|
|
|
| 189 |
|
|
TEST_EXIT
|
