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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [int-test/] [int-test.S] - Blame information for rev 352

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1 93 jeremybenn
/* int-test.S. Test of Or1ksim interrupt handling
2 90 jeremybenn
 
3
   Copyright (C) 1999-2006 OpenCores
4
   Copyright (C) 2010 Embecosm Limited
5
 
6
   Contributors various OpenCores participants
7
   Contributor Jeremy Bennett 
8
 
9
   This file is part of OpenRISC 1000 Architectural Simulator.
10
 
11
   This program is free software; you can redistribute it and/or modify it
12
   under the terms of the GNU General Public License as published by the Free
13
   Software Foundation; either version 3 of the License, or (at your option)
14
   any later version.
15
 
16
   This program is distributed in the hope that it will be useful, but WITHOUT
17
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
   more details.
20
 
21
   You should have received a copy of the GNU General Public License along
22
   with this program.  If not, see .  */
23
 
24
/* ----------------------------------------------------------------------------
25
   This code is commented throughout for use with Doxygen.
26
   --------------------------------------------------------------------------*/
27
 
28 93 jeremybenn
/* NOTE. This is not a test of the Programmable Interrupt Controller.
29
 
30
   Within the test we'll use following global variables:
31 90 jeremybenn
 
32
   r16 interrupt counter
33
   r17 current tick timer comparison counter
34
   r18 sanity counter
35
   r19 loop counter
36
   r20 temp value of SR reg
37
   r21 temp value of TTMR reg.
38
   r23 RAM_START
39
 
40
   r25-r31 used by int handler
41
 
42
   The test do the following:
43 93 jeremybenn
   We set up the tick timer to trigger once and then we trigger interrupts
44
   incrementally on every cycle in the specified test program; on interrupt
45
   handler we check if data computed so far exactly matches precalculated
46
   values. If interrupt has returned incorreclty, we can detect this using
47
   assertion routine at the end.
48 90 jeremybenn
*/
49
 
50
#include "spr-defs.h"
51
#include "board.h"
52
 
53
#define  RAM_START 0x00000000
54
 
55
#define MC_CSR          (0x00)
56
#define MC_POC          (0x04)
57
#define MC_BA_MASK      (0x08)
58
#define MC_CSC(i)       (0x10 + (i) * 8)
59
#define MC_TMS(i)       (0x14 + (i) * 8)
60
 
61
.section  .reset, "ax"
62
 
63
.org 0x100
64
 
65
_reset_vector:
66
  l.addi  r2,r0,0x0
67
  l.addi  r3,r0,0x0
68
  l.addi  r4,r0,0x0
69
  l.addi  r5,r0,0x0
70
  l.addi  r6,r0,0x0
71
  l.addi  r7,r0,0x0
72
  l.addi  r8,r0,0x0
73
  l.addi  r9,r0,0x0
74
  l.addi  r10,r0,0x0
75
  l.addi  r11,r0,0x0
76
  l.addi  r12,r0,0x0
77
  l.addi  r13,r0,0x0
78
  l.addi  r14,r0,0x0
79
  l.addi  r15,r0,0x0
80
  l.addi  r16,r0,0x0
81
  l.addi  r17,r0,0x0
82
  l.addi  r18,r0,0x0
83
  l.addi  r19,r0,0x0
84
  l.addi  r20,r0,0x0
85
  l.addi  r21,r0,0x0
86
  l.addi  r22,r0,0x0
87
  l.addi  r23,r0,0x0
88
  l.addi  r24,r0,0x0
89
  l.addi  r25,r0,0x0
90
  l.addi  r26,r0,0x0
91
  l.addi  r27,r0,0x0
92
  l.addi  r28,r0,0x0
93
  l.addi  r29,r0,0x0
94
  l.addi  r30,r0,0x0
95
  l.addi  r31,r0,0x0
96
 
97
  l.movhi r3,hi(start)
98
  l.ori   r3,r3,lo(start)
99
  l.jr    r3
100
  l.nop
101
start:
102
  l.jal   _init_mc
103
  l.nop
104
 
105
  /* Setup exception wrapper */
106
  l.movhi r3,hi(_src_beg)
107
  l.ori   r3,r3,lo(_src_beg)
108
  l.movhi r4,hi(_dst_beg)
109
  l.ori   r4,r4,lo(_dst_beg)
110
  l.movhi r5,hi(_dst_end)
111
  l.ori   r5,r5,lo(_dst_end)
112
  l.sub   r5,r5,r4
113
  l.sfeqi r5,0
114
  l.bf    2f
115
  l.nop
116
1:
117
  l.lwz   r6,0(r3)
118
  l.sw    0(r4),r6
119
  l.addi  r3,r3,4
120
  l.addi  r4,r4,4
121
  l.addi  r5,r5,-4
122
  l.sfgtsi r5,0
123
  l.bf          1b
124
  l.nop
125
2:
126
  l.movhi r2,hi(_main)
127
  l.ori   r2,r2,lo(_main)
128
  l.jr    r2
129
  l.nop
130
 
131
_init_mc:
132
 
133
  l.movhi r3,hi(MC_BASE_ADDR)
134
  l.ori   r3,r3,lo(MC_BASE_ADDR)
135
 
136
  l.addi  r4,r3,MC_CSC(0)
137
  l.movhi r5,hi(FLASH_BASE_ADDR)
138
  l.srai  r5,r5,6
139
  l.ori   r5,r5,0x0025
140
  l.sw    0(r4),r5
141
 
142
  l.addi  r4,r3,MC_TMS(0)
143
  l.movhi r5,hi(FLASH_TMS_VAL)
144
  l.ori   r5,r5,lo(FLASH_TMS_VAL)
145
  l.sw    0(r4),r5
146
 
147
  l.addi  r4,r3,MC_BA_MASK
148
  l.addi  r5,r0,MC_MASK_VAL
149
  l.sw    0(r4),r5
150
 
151
  l.addi  r4,r3,MC_CSR
152
  l.movhi r5,hi(MC_CSR_VAL)
153
  l.ori   r5,r5,lo(MC_CSR_VAL)
154
  l.sw    0(r4),r5
155
 
156
  l.addi  r4,r3,MC_TMS(1)
157
  l.movhi r5,hi(SDRAM_TMS_VAL)
158
  l.ori   r5,r5,lo(SDRAM_TMS_VAL)
159
  l.sw    0(r4),r5
160
 
161
  l.addi  r4,r3,MC_CSC(1)
162
  l.movhi r5,hi(SDRAM_BASE_ADDR)
163
  l.srai  r5,r5,6
164
  l.ori   r5,r5,0x0411
165
  l.sw    0(r4),r5
166
 
167
  l.jr    r9
168
  l.nop
169
 
170
.section .text
171
 
172
#
173
# Tick timer exception handler
174
#
175
 
176
  l.addi  r31,r3,0
177
# get interrupted program pc
178
  l.mfspr r25,r0,SPR_EPCR_BASE
179
 
180
# calculate instruction address
181
  l.movhi r26,hi(_ie_start)
182
  l.ori   r26,r26,lo(_ie_start)
183
  l.addi  r3,r25,0    #print insn index
184
  l.nop   2
185
  l.sub   r25,r25,r26
186
  l.addi  r3,r25,0    #print insn index
187
  l.nop   2
188
 
189
  l.addi  r3,r31,0    # restore r3
190
  l.sfeqi r25, 0x00
191
  l.bf    _i00
192
  l.sfeqi r25, 0x04
193
  l.bf    _i04
194
  l.sfeqi r25, 0x08
195
  l.bf    _i08
196
  l.sfeqi r25, 0x0c
197
  l.bf    _i0c
198
  l.sfeqi r25, 0x10
199
  l.bf    _i10
200
  l.sfeqi r25, 0x14
201
  l.bf    _i14
202
  l.sfeqi r25, 0x18
203
  l.bf    _i18
204
  l.sfeqi r25, 0x1c
205
  l.bf    _i1c
206
  l.sfeqi r25, 0x20
207
  l.bf    _i20
208
  l.sfeqi r25, 0x24
209
  l.bf    _i24
210
  l.sfeqi r25, 0x28
211
  l.bf    _i28
212
  l.sfeqi r25, 0x2c
213
  l.bf    _i2c
214
  l.sfeqi r25, 0x30
215
  l.bf    _i30
216
  l.sfeqi r25, 0x34
217
  l.bf    _i34
218
  l.sfeqi r25, 0x38
219
  l.bf    _i38
220
  l.nop
221
 
222
# value not defined
223
_die:
224
  l.nop   2             #print r3
225
 
226
  l.addi  r3,r0,0xeeee
227
  l.nop   2
228
  l.addi  r3,r0,1
229
  l.nop   1
230
1:
231
  l.j     1b
232
  l.nop
233
 
234
 
235
_main:
236
        l.nop
237
  l.addi  r3,r0,SPR_SR_SM
238
  l.mtspr r0,r3,SPR_SR
239
        l.nop
240
 
241
#
242
# set tick counter to initial 3 cycles
243
#
244
  l.addi r16,r0,0
245
  l.addi r17,r0,1
246
  l.addi r18,r0,0
247
  l.addi r19,r0,0
248
  l.addi r22,r0,0
249
 
250
  l.movhi r23,hi(RAM_START)
251
  l.ori   r23,r23,lo(RAM_START)
252
 
253
# Set r20 to hold enable tick exception
254
        l.mfspr r20,r0,SPR_SR
255
        l.ori r20,r20,SPR_SR_SM|SPR_SR_TEE|SPR_SR_F
256
 
257
# Set r21 to hold value of TTMR
258
        l.movhi r5,hi(SPR_TTMR_SR | SPR_TTMR_IE)
259
        l.add  r21,r5,r17
260
 
261
#
262
# MAIN LOOP
263
#
264
_main_loop:
265
# reinitialize memory and registers
266
  l.addi  r3,r0,0xaaaa
267
  l.addi  r9,r0,0xbbbb
268
  l.sw    0(r23),r3
269
  l.sw    4(r23),r9
270
  l.sw    8(r23),r3
271
 
272
# Reinitializes tick timer
273
  l.addi  r17,r17,1
274
  l.mtspr r0,r0,SPR_TTCR                # set TTCR
275
  l.mtspr r0,r21,SPR_TTMR               # set TTMR
276
  l.mtspr r0,r0,SPR_TTCR                # set TTCR
277
        l.addi  r21,r21,1
278
 
279
# Enable exceptions and interrupts
280
        l.mtspr r0,r20,SPR_SR   # set SR
281
 
282
##### TEST CODE #####
283
_ie_start:
284
  l.movhi r3,0x1234         #00
285
  l.sw    0(r23),r3         #04
286
  l.movhi r3,hi(RAM_START)  #08
287
  l.lwz   r3,0(r3)          #0c
288
  l.movhi r3,hi(RAM_START)  #10
289
  l.addi  r3,r3,4           #14
290
  l.j     1f                #18
291
  l.lwz   r3,0(r3)          #1c
292
  l.addi  r3,r3,1           #20
293
1:
294
  l.sfeqi r3,0xdead         #24
295
  l.jal   2f                #28
296
  l.addi  r3,r0,0x5678      #2c
297
 
298
_return_addr:
299
2:
300
  l.bf    _die              #30
301
  l.sw    8(r23),r3         #34
302
_ie_end:
303
  l.nop                     #38
304
##### END OF TEST CODE #####
305
 
306
# do some testing
307
 
308
  l.j     _main_loop
309
  l.nop
310
 
311
_i00:
312
  l.sfeqi r3,0xaaaa
313
  l.bnf   _die
314
  l.nop
315
  l.j     _resume
316
  l.nop
317
_i04:
318
  l.movhi  r26,0x1234
319
  l.sfeq   r3,r26
320
  l.bnf   _die
321
  l.nop
322
  l.lwz   r26,0(r23)
323
  l.sfeqi r26,0xaaaa
324
  l.bnf   _die
325
  l.nop
326
  l.j     _resume
327
  l.nop
328
_i08:
329
  l.movhi r26,0x1234
330
  l.sfeq  r3,r26
331
  l.bnf   _die
332
  l.nop
333
  l.lwz   r27,0(r23)
334
  l.sfeq  r27,r26
335
  l.bnf   _die
336
  l.nop
337
  l.j     _resume
338
  l.nop
339
_i0c:
340
  l.sfeq  r3,r23
341
  l.bnf   _die
342
  l.nop
343
  l.j     _resume
344
  l.nop
345
_i10:
346
  l.movhi r26,0x1234
347
  l.sfeq  r26,r3
348
  l.bnf   _die
349
  l.nop
350
  l.j     _resume
351
  l.nop
352
_i14:
353
  l.sfeq  r3,r23
354
  l.bnf   _die
355
  l.nop
356
  l.j     _resume
357
  l.nop
358
_i18:
359
  l.addi  r26,r23,4
360
  l.sfeq  r3,r26
361
  l.bnf   _die
362
  l.nop
363
  l.j     _resume
364
  l.nop
365
_i1c:
366
  l.j     _die
367
  l.nop
368
_i20:
369
  l.j     _die
370
  l.nop
371
_i24:
372
  l.mfspr r26,r0,SPR_ESR_BASE
373
  l.addi  r30,r3,0
374
  l.addi  r3,r26,0
375
  l.nop   2
376
  l.addi  r3,r30,0
377
  l.andi  r26,r26,SPR_SR_F
378
  l.sfeq  r26,r0
379
/*  l.bnf   _die */
380
  l.nop
381
  l.sfeqi  r3,0xbbbb
382
  l.bnf   _die
383
  l.nop
384
  l.j     _resume
385
  l.nop
386
_i28:
387
  l.mfspr r26,r0,SPR_ESR_BASE
388
  l.addi  r30,r3,0
389
  l.addi  r3,r26,0
390
  l.nop   2
391
  l.addi  r3,r30,0
392
  l.andi  r26,r26,SPR_SR_F
393
  l.sfeq  r26,r0
394
  l.bnf    _die
395
  l.nop
396
  l.sfeqi  r22,1
397
  l.bf     _resume
398
  l.addi   r22,r0,1
399
  l.sfeqi  r9,0xbbbb
400
  l.bnf   _die
401
  l.nop
402
  l.j     _resume
403
  l.nop
404
_i2c:
405
  l.movhi  r26,hi(_return_addr)
406
  l.ori    r26,r26,lo(_return_addr)
407
  l.sfeq   r9,r26
408
  l.bnf   _die
409
  l.nop
410
  l.sfeqi  r3,0xbbbb
411
  l.bnf   _die
412
  l.nop
413
  l.j     _resume
414
  l.nop
415
_i30:
416
  l.sfeqi  r3,0x5678
417
  l.bnf   _die
418
  l.nop
419
  l.j     _resume
420
  l.nop
421
_i34:
422
  l.sfeqi  r3,0x5678
423
  l.bnf   _die
424
  l.nop
425
  l.lwz    r26,8(r23)
426
  l.sfeqi  r26,0xaaaa
427
  l.bnf   _die
428
  l.nop
429
  l.j     _resume
430
  l.nop
431
_i38:
432
  l.lwz    r26,8(r23)
433
  l.sfeqi  r26,0x5678
434
  l.bnf   _die
435
  l.nop
436
#
437
# mark finished ok
438
#
439
  l.movhi r3,hi(0xdeaddead)
440
  l.ori   r3,r3,lo(0xdeaddead)
441
  l.nop   2
442
  l.addi  r3,r0,0
443
  l.nop   1
444
_ok:
445
  l.j     _ok
446
  l.nop
447
 
448
_resume:
449
  l.mfspr  r27,r0,SPR_ESR_BASE
450
  l.addi   r26,r0,SPR_SR_TEE
451
  l.addi   r28,r0,-1
452
  l.xor    r26,r26,r28
453
  l.and    r26,r26,r27
454
  l.mtspr  r0,r26,SPR_ESR_BASE
455
 
456
  l.rfe
457
  l.addi    r3,r3,5         # should not be executed

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