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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [mc-async/] [mc-async.h] - Blame information for rev 214

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1 90 jeremybenn
/* mc_async.h - Memory Controller testbench ASYNCdevices defines
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   Copyright (C) 2001 Ivan Guzvinec
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   Copyright (C) 2010 Embecosm Limited
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   Contributor Ivan Guzvinec <ivang@opencores.org>
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   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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   This file is part of OpenRISC 1000 Architectural Simulator.
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   This program is free software; you can redistribute it and/or modify it
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   under the terms of the GNU General Public License as published by the Free
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   Software Foundation; either version 3 of the License, or (at your option)
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   any later version.
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   This program is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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   more details.
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   You should have received a copy of the GNU General Public License along
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   with this program.  If not, see <http:  www.gnu.org/licenses/>.  */
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/* ----------------------------------------------------------------------------
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   This code is commented throughout for use with Doxygen.
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   --------------------------------------------------------------------------*/
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#ifndef __MC_ASYNC_H
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#define __MC_ASYNC_H
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/* should configuration be readm from MC? */
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#define MC_READ_CONF
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/* TEMPLATE SELECTION       */
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/* change #undef to #define */
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#define _MC_TEST_TEMPLATE1
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#undef  _MC_TEST_TEMPLATE2
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#undef  _MC_TEST_TEMPLATE3
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/* ------------------------ */
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/* memory configuration that must reflect mcmem.cfg */
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#define MC_ASYNC_CSMASK 0xFE    /* 8 bit mask for 8 chip selects. 1 ASYNC at CS, 0 something else at CS */
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typedef struct MC_ASYNC_CS
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{
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  unsigned long BW;
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  unsigned long M;
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} MC_ASYNC_CS;
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MC_ASYNC_CS mc_async_cs[8] = {
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  { 2,    /* Bus Width : 0 - 8bit, 1 - 16bit, 2 - 32bit */
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    0x02  /* SELect mask */
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    },
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  { 2, 0x04 },
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  { 2, 0x06 },
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  { 2, 0x08 },
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  { 2, 0x0A },
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  { 2, 0x0C },
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  { 2, 0x0E },
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  { 2, 0x10 } };
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#define MC_ASYNC_TEST0  0x00000001LU /* no parity, bank after column, write enable */
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#define MC_ASYNC_TEST1  0x00000002LU /* parity */
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#define MC_ASYNC_TEST2  0x00000004LU /* bank after row */
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#define MC_ASYNC_TEST3  0x00000008LU /* RO */
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#define MC_ASYNC_TEST4  0x00000010LU /* - NOT DEFINED - */
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#ifdef _MC_TEST_TEMPLATE1 
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  #define MC_ASYNC_FLAGS        0x000002B4LU    /* MC_TEST_ flags... see mc_common.h */
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  #define MC_ASYNC_TESTS        0x0000000FLU
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#endif
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#ifdef _MC_TEST_TEMPLATE2 
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  #define MC_ASYNC_FLAGS        0x00000128LU    /* MC_TEST_ flags... see mc_common.h */
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  #define MC_ASYNC_TESTS        0x00000008LU
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#endif
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#ifdef _MC_TEST_TEMPLATE3 
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  #define MC_ASYNC_FLAGS        0x000007FFLU    /* MC_TEST_ flags... see mc_common.h */
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  #define MC_ASYNC_TESTS        0x0000000FLU
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#endif
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#endif

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