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/* except-mc.s. Exception handling support for Or1k memory controller tests
 
   Copyright (C) 1999-2006 OpenCores
   Copyright (C) 2010 Embecosm Limited
 
   Contributors various OpenCores participants
   Contributor Jeremy Bennett 
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see .  */
 
/* ----------------------------------------------------------------------------
   This code is commented throughout for use with Doxygen.
   --------------------------------------------------------------------------*/
 
/* Support file for c based tests */
#include "spr-defs.h"
 
#define reset reset
 
        .section .stack
        .space 0x1000
stack:
 
        .extern reset_support
        .extern c_reset
        .extern excpt_buserr
        .extern excpt_dpfault
        .extern excpt_ipfault
        .extern excpt_tick
        .extern excpt_align
        .extern excpt_illinsn
        .extern excpt_int
        .extern excpt_dtlbmiss
        .extern excpt_itlbmiss
        .extern excpt_range
        .extern excpt_syscall
        .extern excpt_break
        .extern excpt_trap
 
        .section .except,"ax"
        .org    0x100
reset_vector:
        l.nop
        l.nop
 
        // Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
        // and indeed it is not when simulating the or1200 Verilog core.
        l.andi  r0,r0,0x0
 
        l.addi  r4,r0,0x0
        l.addi  r5,r0,0x0
        l.addi  r6,r0,0x0
        l.addi  r7,r0,0x0
        l.addi  r8,r0,0x0
        l.addi  r9,r0,0x0
        l.addi  r10,r0,0x0
        l.addi  r11,r0,0x0
        l.addi  r12,r0,0x0
        l.addi  r13,r0,0x0
        l.addi  r14,r0,0x0
        l.addi  r15,r0,0x0
        l.addi  r16,r0,0x0
        l.addi  r17,r0,0x0
        l.addi  r18,r0,0x0
        l.addi  r19,r0,0x0
        l.addi  r20,r0,0x0
        l.addi  r21,r0,0x0
        l.addi  r22,r0,0x0
        l.addi  r23,r0,0x0
        l.addi  r24,r0,0x0
        l.addi  r25,r0,0x0
        l.addi  r26,r0,0x0
        l.addi  r27,r0,0x0
        l.addi  r28,r0,0x0
        l.addi  r29,r0,0x0
        l.addi  r30,r0,0x0
        l.addi  r31,r0,0x0
 
        l.j     init_mc
        l.nop
 
start:  l.movhi r1,hi(stack)
        l.ori   r1,r1,lo(stack)
 
        /* Check if this is RTL version */
        l.lbz   r3,0(r0)
        l.sfeqi r3,0xff
        l.bf    2f
        l.nop
        l.movhi r3,hi(_src_beg)
        l.ori   r3,r3,lo(_src_beg)
        l.movhi r4,hi(_dst_beg)
        l.ori   r4,r4,lo(_dst_beg)
        l.movhi r5,hi(_dst_end)
        l.ori   r5,r5,lo(_dst_end)
        l.sub   r5,r5,r4
        l.sfeqi r5,0
        l.bf    2f
        l.nop
1:      l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,-4
        l.sfgtsi r5,0
        l.bf    1b
        l.nop
 
2:
        l.movhi r2,hi(reset)
        l.ori   r2,r2,lo(reset)
        l.jr    r2
        l.nop
 
        .org    0x200
buserr_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_buserr)
        l.ori   r10,r10,lo(excpt_buserr)
        l.lwz   r10,0x0(r10)
        l.jr    r10
        l.nop
 
        .org    0x300
dpfault_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.addi  r3,r3,-4
        l.mtspr r0,r3,SPR_EPCR_BASE
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_dpfault)
        l.ori   r10,r10,lo(excpt_dpfault)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x400
ipfault_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_ipfault)
        l.ori   r10,r10,lo(excpt_ipfault)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x500
lpint_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_tick)
        l.ori   r10,r10,lo(excpt_tick)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x600
align_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_align)
        l.ori   r10,r10,lo(excpt_align)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x700
illinsn_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_illinsn)
        l.ori   r10,r10,lo(excpt_illinsn)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x800
hpint_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_int)
        l.ori   r10,r10,lo(excpt_int)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x900
dtlbmiss_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.addi  r3,r3,-4
        l.mtspr r0,r3,SPR_EPCR_BASE
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_dtlbmiss)
        l.ori   r10,r10,lo(excpt_dtlbmiss)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xa00
itlbmiss_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_itlbmiss)
        l.ori   r10,r10,lo(excpt_itlbmiss)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xb00
range_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_range)
        l.ori   r10,r10,lo(excpt_range)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xc00
syscall_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_syscall)
        l.ori   r10,r10,lo(excpt_syscall)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xd00
break_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_break)
        l.ori   r10,r10,lo(excpt_break)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xe00
trap_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(excpt_trap)
        l.ori   r10,r10,lo(excpt_trap)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
store_regs:
        l.sw    0x00(r1),r3
        l.sw    0x04(r1),r4
        l.sw    0x08(r1),r5
        l.sw    0x0c(r1),r6
        l.sw    0x10(r1),r7
        l.sw    0x14(r1),r8
        l.sw    0x1c(r1),r10
        l.sw    0x20(r1),r11
        l.sw    0x24(r1),r12
        l.sw    0x28(r1),r13
        l.sw    0x2c(r1),r14
        l.sw    0x30(r1),r15
        l.sw    0x34(r1),r16
        l.sw    0x38(r1),r17
        l.sw    0x3c(r1),r18
        l.sw    0x40(r1),r19
        l.sw    0x44(r1),r20
        l.sw    0x48(r1),r21
        l.sw    0x4c(r1),r22
        l.sw    0x50(r1),r23
        l.sw    0x54(r1),r24
        l.sw    0x58(r1),r25
        l.sw    0x5c(r1),r26
        l.sw    0x60(r1),r27
        l.sw    0x64(r1),r28
        l.sw    0x68(r1),r29
        l.sw    0x6c(r1),r30
        l.sw    0x70(r1),r31
        l.jr    r9
        l.nop
 
end_except:
        l.lwz   r3,0x00(r1)
        l.lwz   r4,0x04(r1)
        l.lwz   r5,0x08(r1)
        l.lwz   r6,0x0c(r1)
        l.lwz   r7,0x10(r1)
        l.lwz   r8,0x14(r1)
        l.lwz   r9,0x18(r1)
        l.lwz   r10,0x1c(r1)
        l.lwz   r11,0x20(r1)
        l.lwz   r12,0x24(r1)
        l.lwz   r13,0x28(r1)
        l.lwz   r14,0x2c(r1)
        l.lwz   r15,0x30(r1)
        l.lwz   r16,0x34(r1)
        l.lwz   r17,0x38(r1)
        l.lwz   r18,0x3c(r1)
        l.lwz   r19,0x40(r1)
        l.lwz   r20,0x44(r1)
        l.lwz   r21,0x48(r1)
        l.lwz   r22,0x4c(r1)
        l.lwz   r23,0x50(r1)
        l.lwz   r24,0x54(r1)
        l.lwz   r25,0x58(r1)
        l.lwz   r26,0x5c(r1)
        l.lwz   r27,0x60(r1)
        l.lwz   r28,0x64(r1)
        l.lwz   r29,0x68(r1)
        l.lwz   r30,0x6c(r1)
        l.lwz   r31,0x70(r1)
        l.addi  r1,r1,116
        l.rfe
        l.nop
 
init_mc:
        l.movhi r0, 0x0
        l.slli  r0,r0,16
 
/* Set speed of FLASH access */
/* TMS[0] = 0x00000210       */
/* TMS address = 0x60000014  */
        l.ori   r2,r0,0x020a
        l.movhi r3, 0x6000
        l.ori   r1,r3,0x0014
        l.sw    0(r1),r2
 
/* Set SDRAM parameters for CS1    */
/* old TMS[1] (*6000001c) = 0xfffff020 */
/* old CSC[1] (*60000018) = 0x00200611 */
/* CSR (*60000000) = 0x60300300    */
/* BA_MASK (*60000008) = 0x000000f0 */
 
/* TMS[1] (*6000001c) = 0xfffff023 */
/* CSC[1] (*60000018) = 0x00200491 */
        l.movhi r2,0x6030
        l.ori   r2,r2,0x0300
        l.ori   r1,r3,0x0000
        l.sw    0(r1),r2
        l.movhi r2,0x0000
        l.ori   r2,r2,0x00f0
        l.ori   r1,r3,0x0008
        l.sw    0(r1),r2
        l.movhi r2,0x0724
        l.ori   r2,r2,0x8230
        l.ori   r1,r3,0x001c
        l.sw    0(r1),r2
        l.movhi r2,0x0020
        l.ori   r2,r2,0x0411
        l.ori   r1,r3,0x0018
        l.sw    0(r1),r2
        l.xor   r0,r0,r0
        l.xor   r1,r1,r1
        l.xor   r2,r2,r2
        l.xor   r3,r3,r3
 
        l.j     start
        l.nop

Line No.	Rev	Author	Line
1	90	jeremybenn	`/* except-mc.s. Exception handling support for Or1k memory controller tests`
2
3			`Copyright (C) 1999-2006 OpenCores`
4			`Copyright (C) 2010 Embecosm Limited`
5
6			`Contributors various OpenCores participants`
7			`Contributor Jeremy Bennett`
8
9			`This file is part of OpenRISC 1000 Architectural Simulator.`
10
11			`This program is free software; you can redistribute it and/or modify it`
12			`under the terms of the GNU General Public License as published by the Free`
13			`Software Foundation; either version 3 of the License, or (at your option)`
14			`any later version.`
15
16			`This program is distributed in the hope that it will be useful, but WITHOUT`
17			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
18			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
19			`more details.`
20
21			`You should have received a copy of the GNU General Public License along`
22			`with this program. If not, see . */`
23
24			`/* ----------------------------------------------------------------------------`
25			`This code is commented throughout for use with Doxygen.`
26			`--------------------------------------------------------------------------*/`
27
28			`/* Support file for c based tests */`
29			`#include "spr-defs.h"`
30
31	346	jeremybenn	`#define reset reset`
32	90	jeremybenn
33			`.section .stack`
34			`.space 0x1000`
35	346	jeremybenn	`stack:`
36	90	jeremybenn
37	346	jeremybenn	`.extern reset_support`
38			`.extern c_reset`
39			`.extern excpt_buserr`
40			`.extern excpt_dpfault`
41			`.extern excpt_ipfault`
42			`.extern excpt_tick`
43			`.extern excpt_align`
44			`.extern excpt_illinsn`
45			`.extern excpt_int`
46			`.extern excpt_dtlbmiss`
47			`.extern excpt_itlbmiss`
48			`.extern excpt_range`
49			`.extern excpt_syscall`
50			`.extern excpt_break`
51			`.extern excpt_trap`
52	90	jeremybenn
53			`.section .except,"ax"`
54			`.org 0x100`
55	346	jeremybenn	`reset_vector:`
56	90	jeremybenn	`l.nop`
57			`l.nop`
58	787	jeremybenn
59			`// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,`
60			`// and indeed it is not when simulating the or1200 Verilog core.`
61			`l.andi r0,r0,0x0`
62
63	90	jeremybenn	`l.addi r4,r0,0x0`
64			`l.addi r5,r0,0x0`
65			`l.addi r6,r0,0x0`
66			`l.addi r7,r0,0x0`
67			`l.addi r8,r0,0x0`
68			`l.addi r9,r0,0x0`
69			`l.addi r10,r0,0x0`
70			`l.addi r11,r0,0x0`
71			`l.addi r12,r0,0x0`
72			`l.addi r13,r0,0x0`
73			`l.addi r14,r0,0x0`
74			`l.addi r15,r0,0x0`
75			`l.addi r16,r0,0x0`
76			`l.addi r17,r0,0x0`
77			`l.addi r18,r0,0x0`
78			`l.addi r19,r0,0x0`
79			`l.addi r20,r0,0x0`
80			`l.addi r21,r0,0x0`
81			`l.addi r22,r0,0x0`
82			`l.addi r23,r0,0x0`
83			`l.addi r24,r0,0x0`
84			`l.addi r25,r0,0x0`
85			`l.addi r26,r0,0x0`
86			`l.addi r27,r0,0x0`
87			`l.addi r28,r0,0x0`
88			`l.addi r29,r0,0x0`
89			`l.addi r30,r0,0x0`
90			`l.addi r31,r0,0x0`
91
92			`l.j init_mc`
93			`l.nop`
94
95	346	jeremybenn	`start: l.movhi r1,hi(stack)`
96			`l.ori r1,r1,lo(stack)`
97	90	jeremybenn
98			`/* Check if this is RTL version */`
99			`l.lbz r3,0(r0)`
100			`l.sfeqi r3,0xff`
101			`l.bf 2f`
102			`l.nop`
103			`l.movhi r3,hi(_src_beg)`
104			`l.ori r3,r3,lo(_src_beg)`
105			`l.movhi r4,hi(_dst_beg)`
106			`l.ori r4,r4,lo(_dst_beg)`
107			`l.movhi r5,hi(_dst_end)`
108			`l.ori r5,r5,lo(_dst_end)`
109			`l.sub r5,r5,r4`
110			`l.sfeqi r5,0`
111			`l.bf 2f`
112			`l.nop`
113			`1: l.lwz r6,0(r3)`
114			`l.sw 0(r4),r6`
115			`l.addi r3,r3,4`
116			`l.addi r4,r4,4`
117			`l.addi r5,r5,-4`
118			`l.sfgtsi r5,0`
119			`l.bf 1b`
120			`l.nop`
121
122			`2:`
123			`l.movhi r2,hi(reset)`
124			`l.ori r2,r2,lo(reset)`
125			`l.jr r2`
126			`l.nop`
127
128			`.org 0x200`
129	346	jeremybenn	`buserr_vector:`
130	90	jeremybenn	`l.addi r1,r1,-116`
131			`l.sw 0x18(r1),r9`
132			`l.jal store_regs`
133			`l.nop`
134			`l.movhi r9,hi(end_except)`
135			`l.ori r9,r9,lo(end_except)`
136	346	jeremybenn	`l.movhi r10,hi(excpt_buserr)`
137			`l.ori r10,r10,lo(excpt_buserr)`
138	90	jeremybenn	`l.lwz r10,0x0(r10)`
139			`l.jr r10`
140			`l.nop`
141
142			`.org 0x300`
143	346	jeremybenn	`dpfault_vector:`
144	90	jeremybenn	`l.addi r1,r1,-116`
145			`l.sw 0x18(r1),r9`
146			`l.jal store_regs`
147			`l.nop`
148
149			`l.mfspr r3,r0,SPR_EPCR_BASE`
150			`l.addi r3,r3,-4`
151			`l.mtspr r0,r3,SPR_EPCR_BASE`
152
153			`l.movhi r9,hi(end_except)`
154			`l.ori r9,r9,lo(end_except)`
155	346	jeremybenn	`l.movhi r10,hi(excpt_dpfault)`
156			`l.ori r10,r10,lo(excpt_dpfault)`
157	90	jeremybenn	`l.lwz r10,0(r10)`
158			`l.jr r10`
159			`l.nop`
160
161			`.org 0x400`
162	346	jeremybenn	`ipfault_vector:`
163	90	jeremybenn	`l.addi r1,r1,-116`
164			`l.sw 0x18(r1),r9`
165			`l.jal store_regs`
166			`l.nop`
167			`l.movhi r9,hi(end_except)`
168			`l.ori r9,r9,lo(end_except)`
169	346	jeremybenn	`l.movhi r10,hi(excpt_ipfault)`
170			`l.ori r10,r10,lo(excpt_ipfault)`
171	90	jeremybenn	`l.lwz r10,0(r10)`
172			`l.jr r10`
173			`l.nop`
174
175			`.org 0x500`
176	346	jeremybenn	`lpint_vector:`
177	90	jeremybenn	`l.addi r1,r1,-116`
178			`l.sw 0x18(r1),r9`
179			`l.jal store_regs`
180			`l.nop`
181			`l.movhi r9,hi(end_except)`
182			`l.ori r9,r9,lo(end_except)`
183	346	jeremybenn	`l.movhi r10,hi(excpt_tick)`
184			`l.ori r10,r10,lo(excpt_tick)`
185	90	jeremybenn	`l.lwz r10,0(r10)`
186			`l.jr r10`
187			`l.nop`
188
189			`.org 0x600`
190	346	jeremybenn	`align_vector:`
191	90	jeremybenn	`l.addi r1,r1,-116`
192			`l.sw 0x18(r1),r9`
193			`l.jal store_regs`
194			`l.nop`
195			`l.movhi r9,hi(end_except)`
196			`l.ori r9,r9,lo(end_except)`
197	346	jeremybenn	`l.movhi r10,hi(excpt_align)`
198			`l.ori r10,r10,lo(excpt_align)`
199	90	jeremybenn	`l.lwz r10,0(r10)`
200			`l.jr r10`
201			`l.nop`
202
203			`.org 0x700`
204	346	jeremybenn	`illinsn_vector:`
205	90	jeremybenn	`l.addi r1,r1,-116`
206			`l.sw 0x18(r1),r9`
207			`l.jal store_regs`
208			`l.nop`
209			`l.movhi r9,hi(end_except)`
210			`l.ori r9,r9,lo(end_except)`
211	346	jeremybenn	`l.movhi r10,hi(excpt_illinsn)`
212			`l.ori r10,r10,lo(excpt_illinsn)`
213	90	jeremybenn	`l.lwz r10,0(r10)`
214			`l.jr r10`
215			`l.nop`
216
217			`.org 0x800`
218	346	jeremybenn	`hpint_vector:`
219	90	jeremybenn	`l.addi r1,r1,-116`
220			`l.sw 0x18(r1),r9`
221			`l.jal store_regs`
222			`l.nop`
223			`l.movhi r9,hi(end_except)`
224			`l.ori r9,r9,lo(end_except)`
225	346	jeremybenn	`l.movhi r10,hi(excpt_int)`
226			`l.ori r10,r10,lo(excpt_int)`
227	90	jeremybenn	`l.lwz r10,0(r10)`
228			`l.jr r10`
229			`l.nop`
230
231			`.org 0x900`
232	346	jeremybenn	`dtlbmiss_vector:`
233	90	jeremybenn	`l.addi r1,r1,-116`
234			`l.sw 0x18(r1),r9`
235			`l.jal store_regs`
236			`l.nop`
237
238			`l.mfspr r3,r0,SPR_EPCR_BASE`
239			`l.addi r3,r3,-4`
240			`l.mtspr r0,r3,SPR_EPCR_BASE`
241
242			`l.movhi r9,hi(end_except)`
243			`l.ori r9,r9,lo(end_except)`
244	346	jeremybenn	`l.movhi r10,hi(excpt_dtlbmiss)`
245			`l.ori r10,r10,lo(excpt_dtlbmiss)`
246	90	jeremybenn	`l.lwz r10,0(r10)`
247			`l.jr r10`
248			`l.nop`
249
250			`.org 0xa00`
251	346	jeremybenn	`itlbmiss_vector:`
252	90	jeremybenn	`l.addi r1,r1,-116`
253			`l.sw 0x18(r1),r9`
254			`l.jal store_regs`
255			`l.nop`
256			`l.movhi r9,hi(end_except)`
257			`l.ori r9,r9,lo(end_except)`
258	346	jeremybenn	`l.movhi r10,hi(excpt_itlbmiss)`
259			`l.ori r10,r10,lo(excpt_itlbmiss)`
260	90	jeremybenn	`l.lwz r10,0(r10)`
261			`l.jr r10`
262			`l.nop`
263
264			`.org 0xb00`
265	346	jeremybenn	`range_vector:`
266	90	jeremybenn	`l.addi r1,r1,-116`
267			`l.sw 0x18(r1),r9`
268			`l.jal store_regs`
269			`l.nop`
270			`l.movhi r9,hi(end_except)`
271			`l.ori r9,r9,lo(end_except)`
272	346	jeremybenn	`l.movhi r10,hi(excpt_range)`
273			`l.ori r10,r10,lo(excpt_range)`
274	90	jeremybenn	`l.lwz r10,0(r10)`
275			`l.jr r10`
276			`l.nop`
277
278			`.org 0xc00`
279	346	jeremybenn	`syscall_vector:`
280	90	jeremybenn	`l.addi r1,r1,-116`
281			`l.sw 0x18(r1),r9`
282			`l.jal store_regs`
283			`l.nop`
284			`l.movhi r9,hi(end_except)`
285			`l.ori r9,r9,lo(end_except)`
286	346	jeremybenn	`l.movhi r10,hi(excpt_syscall)`
287			`l.ori r10,r10,lo(excpt_syscall)`
288	90	jeremybenn	`l.lwz r10,0(r10)`
289			`l.jr r10`
290			`l.nop`
291
292			`.org 0xd00`
293	346	jeremybenn	`break_vector:`
294	90	jeremybenn	`l.addi r1,r1,-116`
295			`l.sw 0x18(r1),r9`
296			`l.jal store_regs`
297			`l.nop`
298			`l.movhi r9,hi(end_except)`
299			`l.ori r9,r9,lo(end_except)`
300	346	jeremybenn	`l.movhi r10,hi(excpt_break)`
301			`l.ori r10,r10,lo(excpt_break)`
302	90	jeremybenn	`l.lwz r10,0(r10)`
303			`l.jr r10`
304			`l.nop`
305
306			`.org 0xe00`
307	346	jeremybenn	`trap_vector:`
308	90	jeremybenn	`l.addi r1,r1,-116`
309			`l.sw 0x18(r1),r9`
310			`l.jal store_regs`
311			`l.nop`
312			`l.movhi r9,hi(end_except)`
313			`l.ori r9,r9,lo(end_except)`
314	346	jeremybenn	`l.movhi r10,hi(excpt_trap)`
315			`l.ori r10,r10,lo(excpt_trap)`
316	90	jeremybenn	`l.lwz r10,0(r10)`
317			`l.jr r10`
318			`l.nop`
319
320			`store_regs:`
321			`l.sw 0x00(r1),r3`
322			`l.sw 0x04(r1),r4`
323			`l.sw 0x08(r1),r5`
324			`l.sw 0x0c(r1),r6`
325			`l.sw 0x10(r1),r7`
326			`l.sw 0x14(r1),r8`
327			`l.sw 0x1c(r1),r10`
328			`l.sw 0x20(r1),r11`
329			`l.sw 0x24(r1),r12`
330			`l.sw 0x28(r1),r13`
331			`l.sw 0x2c(r1),r14`
332			`l.sw 0x30(r1),r15`
333			`l.sw 0x34(r1),r16`
334			`l.sw 0x38(r1),r17`
335			`l.sw 0x3c(r1),r18`
336			`l.sw 0x40(r1),r19`
337			`l.sw 0x44(r1),r20`
338			`l.sw 0x48(r1),r21`
339			`l.sw 0x4c(r1),r22`
340			`l.sw 0x50(r1),r23`
341			`l.sw 0x54(r1),r24`
342			`l.sw 0x58(r1),r25`
343			`l.sw 0x5c(r1),r26`
344			`l.sw 0x60(r1),r27`
345			`l.sw 0x64(r1),r28`
346			`l.sw 0x68(r1),r29`
347			`l.sw 0x6c(r1),r30`
348			`l.sw 0x70(r1),r31`
349			`l.jr r9`
350			`l.nop`
351
352			`end_except:`
353			`l.lwz r3,0x00(r1)`
354			`l.lwz r4,0x04(r1)`
355			`l.lwz r5,0x08(r1)`
356			`l.lwz r6,0x0c(r1)`
357			`l.lwz r7,0x10(r1)`
358			`l.lwz r8,0x14(r1)`
359			`l.lwz r9,0x18(r1)`
360			`l.lwz r10,0x1c(r1)`
361			`l.lwz r11,0x20(r1)`
362			`l.lwz r12,0x24(r1)`
363			`l.lwz r13,0x28(r1)`
364			`l.lwz r14,0x2c(r1)`
365			`l.lwz r15,0x30(r1)`
366			`l.lwz r16,0x34(r1)`
367			`l.lwz r17,0x38(r1)`
368			`l.lwz r18,0x3c(r1)`
369			`l.lwz r19,0x40(r1)`
370			`l.lwz r20,0x44(r1)`
371			`l.lwz r21,0x48(r1)`
372			`l.lwz r22,0x4c(r1)`
373			`l.lwz r23,0x50(r1)`
374			`l.lwz r24,0x54(r1)`
375			`l.lwz r25,0x58(r1)`
376			`l.lwz r26,0x5c(r1)`
377			`l.lwz r27,0x60(r1)`
378			`l.lwz r28,0x64(r1)`
379			`l.lwz r29,0x68(r1)`
380			`l.lwz r30,0x6c(r1)`
381			`l.lwz r31,0x70(r1)`
382			`l.addi r1,r1,116`
383			`l.rfe`
384			`l.nop`
385
386			`init_mc:`
387			`l.movhi r0, 0x0`
388			`l.slli r0,r0,16`
389
390			`/* Set speed of FLASH access */`
391			`/* TMS[0] = 0x00000210 */`
392			`/* TMS address = 0x60000014 */`
393			`l.ori r2,r0,0x020a`
394			`l.movhi r3, 0x6000`
395			`l.ori r1,r3,0x0014`
396			`l.sw 0(r1),r2`
397
398			`/* Set SDRAM parameters for CS1 */`
399			`/* old TMS[1] (6000001c) = 0xfffff020 /`
400			`/* old CSC[1] (60000018) = 0x00200611 /`
401			`/* CSR (60000000) = 0x60300300 /`
402			`/* BA_MASK (60000008) = 0x000000f0 /`
403
404			`/* TMS[1] (6000001c) = 0xfffff023 /`
405			`/* CSC[1] (60000018) = 0x00200491 /`
406			`l.movhi r2,0x6030`
407			`l.ori r2,r2,0x0300`
408			`l.ori r1,r3,0x0000`
409			`l.sw 0(r1),r2`
410			`l.movhi r2,0x0000`
411			`l.ori r2,r2,0x00f0`
412			`l.ori r1,r3,0x0008`
413			`l.sw 0(r1),r2`
414			`l.movhi r2,0x0724`
415			`l.ori r2,r2,0x8230`
416			`l.ori r1,r3,0x001c`
417			`l.sw 0(r1),r2`
418			`l.movhi r2,0x0020`
419			`l.ori r2,r2,0x0411`
420			`l.ori r1,r3,0x0018`
421			`l.sw 0(r1),r2`
422			`l.xor r0,r0,r0`
423			`l.xor r1,r1,r1`
424			`l.xor r2,r2,r2`
425			`l.xor r3,r3,r3`
426
427			`l.j start`
428			`l.nop`

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