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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [mc-common/] [except-mc.S] - Blame information for rev 90

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Line No. Rev Author Line
1 90 jeremybenn
/* except-mc.s. Exception handling support for Or1k memory controller tests
2
 
3
   Copyright (C) 1999-2006 OpenCores
4
   Copyright (C) 2010 Embecosm Limited
5
 
6
   Contributors various OpenCores participants
7
   Contributor Jeremy Bennett 
8
 
9
   This file is part of OpenRISC 1000 Architectural Simulator.
10
 
11
   This program is free software; you can redistribute it and/or modify it
12
   under the terms of the GNU General Public License as published by the Free
13
   Software Foundation; either version 3 of the License, or (at your option)
14
   any later version.
15
 
16
   This program is distributed in the hope that it will be useful, but WITHOUT
17
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
   more details.
20
 
21
   You should have received a copy of the GNU General Public License along
22
   with this program.  If not, see .  */
23
 
24
/* ----------------------------------------------------------------------------
25
   This code is commented throughout for use with Doxygen.
26
   --------------------------------------------------------------------------*/
27
 
28
/* Support file for c based tests */
29
#include "spr-defs.h"
30
 
31
#define reset _reset
32
 
33
        .section .stack
34
        .space 0x1000
35
_stack:
36
 
37
        .extern _reset_support
38
        .extern _c_reset
39
        .extern _excpt_buserr
40
        .extern _excpt_dpfault
41
        .extern _excpt_ipfault
42
        .extern _excpt_tick
43
        .extern _excpt_align
44
        .extern _excpt_illinsn
45
        .extern _excpt_int
46
        .extern _excpt_dtlbmiss
47
        .extern _excpt_itlbmiss
48
        .extern _excpt_range
49
        .extern _excpt_syscall
50
        .extern _excpt_break
51
        .extern _excpt_trap
52
 
53
        .section .except,"ax"
54
        .org    0x100
55
_reset_vector:
56
        l.nop
57
        l.nop
58
        l.addi  r4,r0,0x0
59
        l.addi  r5,r0,0x0
60
        l.addi  r6,r0,0x0
61
        l.addi  r7,r0,0x0
62
        l.addi  r8,r0,0x0
63
        l.addi  r9,r0,0x0
64
        l.addi  r10,r0,0x0
65
        l.addi  r11,r0,0x0
66
        l.addi  r12,r0,0x0
67
        l.addi  r13,r0,0x0
68
        l.addi  r14,r0,0x0
69
        l.addi  r15,r0,0x0
70
        l.addi  r16,r0,0x0
71
        l.addi  r17,r0,0x0
72
        l.addi  r18,r0,0x0
73
        l.addi  r19,r0,0x0
74
        l.addi  r20,r0,0x0
75
        l.addi  r21,r0,0x0
76
        l.addi  r22,r0,0x0
77
        l.addi  r23,r0,0x0
78
        l.addi  r24,r0,0x0
79
        l.addi  r25,r0,0x0
80
        l.addi  r26,r0,0x0
81
        l.addi  r27,r0,0x0
82
        l.addi  r28,r0,0x0
83
        l.addi  r29,r0,0x0
84
        l.addi  r30,r0,0x0
85
        l.addi  r31,r0,0x0
86
 
87
        l.j     init_mc
88
        l.nop
89
 
90
start:  l.movhi r1,hi(_stack)
91
        l.ori   r1,r1,lo(_stack)
92
 
93
        /* Check if this is RTL version */
94
        l.lbz   r3,0(r0)
95
        l.sfeqi r3,0xff
96
        l.bf    2f
97
        l.nop
98
        l.movhi r3,hi(_src_beg)
99
        l.ori   r3,r3,lo(_src_beg)
100
        l.movhi r4,hi(_dst_beg)
101
        l.ori   r4,r4,lo(_dst_beg)
102
        l.movhi r5,hi(_dst_end)
103
        l.ori   r5,r5,lo(_dst_end)
104
        l.sub   r5,r5,r4
105
        l.sfeqi r5,0
106
        l.bf    2f
107
        l.nop
108
1:      l.lwz   r6,0(r3)
109
        l.sw    0(r4),r6
110
        l.addi  r3,r3,4
111
        l.addi  r4,r4,4
112
        l.addi  r5,r5,-4
113
        l.sfgtsi r5,0
114
        l.bf    1b
115
        l.nop
116
 
117
2:
118
        l.movhi r2,hi(reset)
119
        l.ori   r2,r2,lo(reset)
120
        l.jr    r2
121
        l.nop
122
 
123
        .org    0x200
124
_buserr_vector:
125
        l.addi  r1,r1,-116
126
        l.sw    0x18(r1),r9
127
        l.jal   store_regs
128
        l.nop
129
        l.movhi r9,hi(end_except)
130
        l.ori   r9,r9,lo(end_except)
131
        l.movhi r10,hi(_excpt_buserr)
132
        l.ori   r10,r10,lo(_excpt_buserr)
133
        l.lwz   r10,0x0(r10)
134
        l.jr    r10
135
        l.nop
136
 
137
        .org    0x300
138
_dpfault_vector:
139
        l.addi  r1,r1,-116
140
        l.sw    0x18(r1),r9
141
        l.jal   store_regs
142
        l.nop
143
 
144
        l.mfspr r3,r0,SPR_EPCR_BASE
145
        l.addi  r3,r3,-4
146
        l.mtspr r0,r3,SPR_EPCR_BASE
147
 
148
        l.movhi r9,hi(end_except)
149
        l.ori   r9,r9,lo(end_except)
150
        l.movhi r10,hi(_excpt_dpfault)
151
        l.ori   r10,r10,lo(_excpt_dpfault)
152
        l.lwz   r10,0(r10)
153
        l.jr    r10
154
        l.nop
155
 
156
        .org    0x400
157
_ipfault_vector:
158
        l.addi  r1,r1,-116
159
        l.sw    0x18(r1),r9
160
        l.jal   store_regs
161
        l.nop
162
        l.movhi r9,hi(end_except)
163
        l.ori   r9,r9,lo(end_except)
164
        l.movhi r10,hi(_excpt_ipfault)
165
        l.ori   r10,r10,lo(_excpt_ipfault)
166
        l.lwz   r10,0(r10)
167
        l.jr    r10
168
        l.nop
169
 
170
        .org    0x500
171
_lpint_vector:
172
        l.addi  r1,r1,-116
173
        l.sw    0x18(r1),r9
174
        l.jal   store_regs
175
        l.nop
176
        l.movhi r9,hi(end_except)
177
        l.ori   r9,r9,lo(end_except)
178
        l.movhi r10,hi(_excpt_tick)
179
        l.ori   r10,r10,lo(_excpt_tick)
180
        l.lwz   r10,0(r10)
181
        l.jr    r10
182
        l.nop
183
 
184
        .org    0x600
185
_align_vector:
186
        l.addi  r1,r1,-116
187
        l.sw    0x18(r1),r9
188
        l.jal   store_regs
189
        l.nop
190
        l.movhi r9,hi(end_except)
191
        l.ori   r9,r9,lo(end_except)
192
        l.movhi r10,hi(_excpt_align)
193
        l.ori   r10,r10,lo(_excpt_align)
194
        l.lwz   r10,0(r10)
195
        l.jr    r10
196
        l.nop
197
 
198
        .org    0x700
199
_illinsn_vector:
200
        l.addi  r1,r1,-116
201
        l.sw    0x18(r1),r9
202
        l.jal   store_regs
203
        l.nop
204
        l.movhi r9,hi(end_except)
205
        l.ori   r9,r9,lo(end_except)
206
        l.movhi r10,hi(_excpt_illinsn)
207
        l.ori   r10,r10,lo(_excpt_illinsn)
208
        l.lwz   r10,0(r10)
209
        l.jr    r10
210
        l.nop
211
 
212
        .org    0x800
213
_hpint_vector:
214
        l.addi  r1,r1,-116
215
        l.sw    0x18(r1),r9
216
        l.jal   store_regs
217
        l.nop
218
        l.movhi r9,hi(end_except)
219
        l.ori   r9,r9,lo(end_except)
220
        l.movhi r10,hi(_excpt_int)
221
        l.ori   r10,r10,lo(_excpt_int)
222
        l.lwz   r10,0(r10)
223
        l.jr    r10
224
        l.nop
225
 
226
        .org    0x900
227
_dtlbmiss_vector:
228
        l.addi  r1,r1,-116
229
        l.sw    0x18(r1),r9
230
        l.jal   store_regs
231
        l.nop
232
 
233
        l.mfspr r3,r0,SPR_EPCR_BASE
234
        l.addi  r3,r3,-4
235
        l.mtspr r0,r3,SPR_EPCR_BASE
236
 
237
        l.movhi r9,hi(end_except)
238
        l.ori   r9,r9,lo(end_except)
239
        l.movhi r10,hi(_excpt_dtlbmiss)
240
        l.ori   r10,r10,lo(_excpt_dtlbmiss)
241
        l.lwz   r10,0(r10)
242
        l.jr    r10
243
        l.nop
244
 
245
        .org    0xa00
246
_itlbmiss_vector:
247
        l.addi  r1,r1,-116
248
        l.sw    0x18(r1),r9
249
        l.jal   store_regs
250
        l.nop
251
        l.movhi r9,hi(end_except)
252
        l.ori   r9,r9,lo(end_except)
253
        l.movhi r10,hi(_excpt_itlbmiss)
254
        l.ori   r10,r10,lo(_excpt_itlbmiss)
255
        l.lwz   r10,0(r10)
256
        l.jr    r10
257
        l.nop
258
 
259
        .org    0xb00
260
_range_vector:
261
        l.addi  r1,r1,-116
262
        l.sw    0x18(r1),r9
263
        l.jal   store_regs
264
        l.nop
265
        l.movhi r9,hi(end_except)
266
        l.ori   r9,r9,lo(end_except)
267
        l.movhi r10,hi(_excpt_range)
268
        l.ori   r10,r10,lo(_excpt_range)
269
        l.lwz   r10,0(r10)
270
        l.jr    r10
271
        l.nop
272
 
273
        .org    0xc00
274
_syscall_vector:
275
        l.addi  r1,r1,-116
276
        l.sw    0x18(r1),r9
277
        l.jal   store_regs
278
        l.nop
279
        l.movhi r9,hi(end_except)
280
        l.ori   r9,r9,lo(end_except)
281
        l.movhi r10,hi(_excpt_syscall)
282
        l.ori   r10,r10,lo(_excpt_syscall)
283
        l.lwz   r10,0(r10)
284
        l.jr    r10
285
        l.nop
286
 
287
        .org    0xd00
288
_break_vector:
289
        l.addi  r1,r1,-116
290
        l.sw    0x18(r1),r9
291
        l.jal   store_regs
292
        l.nop
293
        l.movhi r9,hi(end_except)
294
        l.ori   r9,r9,lo(end_except)
295
        l.movhi r10,hi(_excpt_break)
296
        l.ori   r10,r10,lo(_excpt_break)
297
        l.lwz   r10,0(r10)
298
        l.jr    r10
299
        l.nop
300
 
301
        .org    0xe00
302
_trap_vector:
303
        l.addi  r1,r1,-116
304
        l.sw    0x18(r1),r9
305
        l.jal   store_regs
306
        l.nop
307
        l.movhi r9,hi(end_except)
308
        l.ori   r9,r9,lo(end_except)
309
        l.movhi r10,hi(_excpt_trap)
310
        l.ori   r10,r10,lo(_excpt_trap)
311
        l.lwz   r10,0(r10)
312
        l.jr    r10
313
        l.nop
314
 
315
store_regs:
316
        l.sw    0x00(r1),r3
317
        l.sw    0x04(r1),r4
318
        l.sw    0x08(r1),r5
319
        l.sw    0x0c(r1),r6
320
        l.sw    0x10(r1),r7
321
        l.sw    0x14(r1),r8
322
        l.sw    0x1c(r1),r10
323
        l.sw    0x20(r1),r11
324
        l.sw    0x24(r1),r12
325
        l.sw    0x28(r1),r13
326
        l.sw    0x2c(r1),r14
327
        l.sw    0x30(r1),r15
328
        l.sw    0x34(r1),r16
329
        l.sw    0x38(r1),r17
330
        l.sw    0x3c(r1),r18
331
        l.sw    0x40(r1),r19
332
        l.sw    0x44(r1),r20
333
        l.sw    0x48(r1),r21
334
        l.sw    0x4c(r1),r22
335
        l.sw    0x50(r1),r23
336
        l.sw    0x54(r1),r24
337
        l.sw    0x58(r1),r25
338
        l.sw    0x5c(r1),r26
339
        l.sw    0x60(r1),r27
340
        l.sw    0x64(r1),r28
341
        l.sw    0x68(r1),r29
342
        l.sw    0x6c(r1),r30
343
        l.sw    0x70(r1),r31
344
        l.jr    r9
345
        l.nop
346
 
347
end_except:
348
        l.lwz   r3,0x00(r1)
349
        l.lwz   r4,0x04(r1)
350
        l.lwz   r5,0x08(r1)
351
        l.lwz   r6,0x0c(r1)
352
        l.lwz   r7,0x10(r1)
353
        l.lwz   r8,0x14(r1)
354
        l.lwz   r9,0x18(r1)
355
        l.lwz   r10,0x1c(r1)
356
        l.lwz   r11,0x20(r1)
357
        l.lwz   r12,0x24(r1)
358
        l.lwz   r13,0x28(r1)
359
        l.lwz   r14,0x2c(r1)
360
        l.lwz   r15,0x30(r1)
361
        l.lwz   r16,0x34(r1)
362
        l.lwz   r17,0x38(r1)
363
        l.lwz   r18,0x3c(r1)
364
        l.lwz   r19,0x40(r1)
365
        l.lwz   r20,0x44(r1)
366
        l.lwz   r21,0x48(r1)
367
        l.lwz   r22,0x4c(r1)
368
        l.lwz   r23,0x50(r1)
369
        l.lwz   r24,0x54(r1)
370
        l.lwz   r25,0x58(r1)
371
        l.lwz   r26,0x5c(r1)
372
        l.lwz   r27,0x60(r1)
373
        l.lwz   r28,0x64(r1)
374
        l.lwz   r29,0x68(r1)
375
        l.lwz   r30,0x6c(r1)
376
        l.lwz   r31,0x70(r1)
377
        l.addi  r1,r1,116
378
        l.rfe
379
        l.nop
380
 
381
init_mc:
382
        l.movhi r0, 0x0
383
        l.slli  r0,r0,16
384
 
385
/* Set speed of FLASH access */
386
/* TMS[0] = 0x00000210       */
387
/* TMS address = 0x60000014  */
388
        l.ori   r2,r0,0x020a
389
        l.movhi r3, 0x6000
390
        l.ori   r1,r3,0x0014
391
        l.sw    0(r1),r2
392
 
393
/* Set SDRAM parameters for CS1    */
394
/* old TMS[1] (*6000001c) = 0xfffff020 */
395
/* old CSC[1] (*60000018) = 0x00200611 */
396
/* CSR (*60000000) = 0x60300300    */
397
/* BA_MASK (*60000008) = 0x000000f0 */
398
 
399
/* TMS[1] (*6000001c) = 0xfffff023 */
400
/* CSC[1] (*60000018) = 0x00200491 */
401
        l.movhi r2,0x6030
402
        l.ori   r2,r2,0x0300
403
        l.ori   r1,r3,0x0000
404
        l.sw    0(r1),r2
405
        l.movhi r2,0x0000
406
        l.ori   r2,r2,0x00f0
407
        l.ori   r1,r3,0x0008
408
        l.sw    0(r1),r2
409
        l.movhi r2,0x0724
410
        l.ori   r2,r2,0x8230
411
        l.ori   r1,r3,0x001c
412
        l.sw    0(r1),r2
413
        l.movhi r2,0x0020
414
        l.ori   r2,r2,0x0411
415
        l.ori   r1,r3,0x0018
416
        l.sw    0(r1),r2
417
        l.xor   r0,r0,r0
418
        l.xor   r1,r1,r1
419
        l.xor   r2,r2,r2
420
        l.xor   r3,r3,r3
421
 
422
        l.j     start
423
        l.nop

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