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90 |
jeremybenn |
/* mc_dram.c - Memory Controller testbench dram test
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Copyright (C) 2001 Ivan Guzvinec
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Copyright (C) 2010 Embecosm Limited
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Contributor Ivan Guzvinec <ivang@opencores.org>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http: www.gnu.org/licenses/>. */
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/* ----------------------------------------------------------------------------
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This code is commented throughout for use with Doxygen.
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--------------------------------------------------------------------------*/
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#include "support.h"
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#include "mc-common.h"
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#include "mc-dram.h"
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#include "config.h"
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110 |
julius |
#include "mc_defines.h"
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90 |
jeremybenn |
#include "gpio.h"
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#include "fields.h"
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#define T_ROW_SIZE 8
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#define T_ROW_OFF 5
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#define T_ROWS 25
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#define T_GROUPS 3
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typedef volatile unsigned long *REGISTER;
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/*
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unsigned long nRowSize = 0;
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unsigned long nColumns = 0;
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*/
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REGISTER mc_poc = (unsigned long*)(MC_BASE + MC_POC);
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REGISTER mc_csr = (unsigned long*)(MC_BASE + MC_CSR);
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REGISTER mc_ba_mask = (unsigned long*)(MC_BASE + MC_BA_MASK);
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REGISTER rgpio_out = (unsigned long*)(GPIO_BASE + RGPIO_OUT);
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REGISTER rgpio_in = (unsigned long*)(GPIO_BASE + RGPIO_IN);
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unsigned long lpoc;
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unsigned char mc_cs;
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unsigned long set_config()
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{
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REGISTER mc_csc;
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unsigned char ch;
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for (ch=0; ch<8; ch++) {
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if (MC_SDRAM_CSMASK & (0x01 << ch) ) {
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mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
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SET_FIELD(*mc_csc, MC_CSC, MS, mc_sdram_cs[ch].MS);
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SET_FIELD(*mc_csc, MC_CSC, BW, mc_sdram_cs[ch].BW);
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SET_FIELD(*mc_csc, MC_CSC, SEL, mc_sdram_cs[ch].M);
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SET_FLAG(*mc_csc, MC_CSC, EN);
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printf ("Channel Config %d - CSC = 0x%08lX\n", ch, *mc_csc);
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}
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}
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return 0;
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}
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unsigned long get_config()
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{
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REGISTER mc_csc;
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REGISTER mc_tms;
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unsigned char ch;
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mc_cs = 0;
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for (ch=0; ch<8; ch++) {
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mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
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mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
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if ( (GET_FIELD(*mc_csc, MC_CSC, MEMTYPE) == 0) &&
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(TEST_FLAG(*mc_csc, MC_CSC, EN) == 1 ) ) {
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mc_sdram_cs[ch].MS = GET_FIELD(*mc_csc, MC_CSC, MS);
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mc_sdram_cs[ch].BW = GET_FIELD(*mc_csc, MC_CSC, BW);
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mc_sdram_cs[ch].M = GET_FIELD(*mc_csc, MC_CSC, SEL);
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mc_cs |= (1 << ch);
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printf("get_config(%d) : MS=0x%0lx, BW=0x%0lx, M=0x%0lx\n", ch,
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mc_sdram_cs[ch].MS,
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mc_sdram_cs[ch].BW,
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mc_sdram_cs[ch].M);
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}
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}
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printf("get_config() : cs=0x%0x\n", mc_cs);
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return 0;
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}
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int main()
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{
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unsigned long ret;
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unsigned char ch;
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unsigned long j, i;
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unsigned long test;
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unsigned long gpio_pat = 0;
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unsigned long nRowSize = 0;
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unsigned long nRows = 0;
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unsigned long nRowSh = 0;
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unsigned long nRowGrp = 0;
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unsigned long nAddress;
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unsigned long mc_sel;
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REGISTER mc_tms;
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REGISTER mc_csc;
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printf ("Memory controller test with DRAM\n");
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*rgpio_out = 0xFFFFFFFF;
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/* set configuration */
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randomin(7435);
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lpoc = *mc_poc;
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#ifdef MC_READ_CONF
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if (get_config()) {
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printf("Error reading MC configuration\n");
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report(0x00000001);
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return(1);
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}
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#else
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mc_cs = MC_SDRAM_CSMASK;
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#endif
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for (ch=0; ch<8; ch++) {
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if (mc_cs & (0x01 << ch) ) {
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printf ("--- Begin Test on CS%d ---\n", ch);
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mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
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mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
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mc_sel = GET_FIELD(*mc_csc, MC_CSC, SEL);
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SET_FIELD(*mc_tms, MC_TMS_SDRAM, OM, 0); /*normal op*/
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SET_FIELD(*mc_tms, MC_TMS_SDRAM, CL, 3); /*CAS*/
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switch ( mc_sdram_cs[ch].BW + (3 * mc_sdram_cs[ch].MS) ) {
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case 0:
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case 4:
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nRowSize = MC_SDRAM_ROWSIZE_0;
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nRows = MC_SDRAM_ROWS_0;
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nRowSh = MC_SDRAM_ROWSH_0; break;
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case 1:
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case 5:
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nRowSize = MC_SDRAM_ROWSIZE_1;
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nRows = MC_SDRAM_ROWS_1;
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nRowSh = MC_SDRAM_ROWSH_1; break;
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case 2:
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nRowSize = MC_SDRAM_ROWSIZE_2;
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nRows = MC_SDRAM_ROWS_2;
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nRowSh = MC_SDRAM_ROWSH_2; break;
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case 3:
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nRowSize = MC_SDRAM_ROWSIZE_3;
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nRows = MC_SDRAM_ROWS_3;
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nRowSh = MC_SDRAM_ROWSH_3; break;
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case 6:
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nRowSize = MC_SDRAM_ROWSIZE_6;
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nRows = MC_SDRAM_ROWS_6;
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nRowSh = MC_SDRAM_ROWSH_6; break;
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case 7:
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nRowSize = MC_SDRAM_ROWSIZE_7;
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nRows = MC_SDRAM_ROWS_7;
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nRowSh = MC_SDRAM_ROWSH_7; break;
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case 8:
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nRowSize = MC_SDRAM_ROWSIZE_8;
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nRows = MC_SDRAM_ROWS_8;
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nRowSh = MC_SDRAM_ROWSH_8; break;
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}
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printf ("CS configuration : CSC - 0x%08lX, TMS - 0x%08lX, rs = %lu, nr = %lu, sh = %lu, sel = %lu\n",
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*mc_csc, *mc_tms, nRowSize, nRows, nRowSh, mc_sel);
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/*nRows -= MC_SDRAM_ROW_OFF;*/
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for (test=0; test<16; test++) {
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/* configure MC*/
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CLEAR_FLAG(*mc_csc, MC_CSC, PEN); /* no parity */
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CLEAR_FLAG(*mc_csc, MC_CSC, KRO); /* close row */
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CLEAR_FLAG(*mc_csc, MC_CSC, BAS); /* bank after column */
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CLEAR_FLAG(*mc_csc, MC_CSC, WP); /* write enable */
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SET_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* single loc access */
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CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* sequential burst */
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SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 0); /* 1 */
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switch (test) {
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case 0:
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if ((MC_SDRAM_TESTS & MC_SDRAM_TEST0) != MC_SDRAM_TEST0)
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continue;
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break;
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case 1:
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if ((MC_SDRAM_TESTS & MC_SDRAM_TEST1) != MC_SDRAM_TEST1)
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continue;
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SET_FLAG(*mc_csc, MC_CSC, PEN); /* parity */
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break;
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case 2:
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if ((MC_SDRAM_TESTS & MC_SDRAM_TEST2) != MC_SDRAM_TEST2)
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continue;
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SET_FLAG(*mc_csc, MC_CSC, KRO); /* keep row */
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break;
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case 3:
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| 215 |
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if ((MC_SDRAM_TESTS & MC_SDRAM_TEST3) != MC_SDRAM_TEST3)
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| 216 |
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continue;
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| 217 |
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SET_FLAG(*mc_csc, MC_CSC, BAS); /* bank after row*/
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| 218 |
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break;
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| 219 |
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case 4:
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| 220 |
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if ((MC_SDRAM_TESTS & MC_SDRAM_TEST4) != MC_SDRAM_TEST4)
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| 221 |
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continue;
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| 222 |
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SET_FLAG(*mc_csc, MC_CSC, WP); /* RO */
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| 223 |
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break;
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| 224 |
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case 5:
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| 225 |
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if ((MC_SDRAM_TESTS & MC_SDRAM_TEST5) != MC_SDRAM_TEST5)
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| 226 |
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continue;
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| 227 |
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CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
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| 228 |
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break;
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| 229 |
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case 6:
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| 230 |
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if ((MC_SDRAM_TESTS & MC_SDRAM_TEST6) != MC_SDRAM_TEST6)
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| 231 |
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continue;
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| 232 |
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CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
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| 233 |
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SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 1); /* 2 */
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| 234 |
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break;
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| 235 |
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case 7:
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| 236 |
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if ((MC_SDRAM_TESTS & MC_SDRAM_TEST7) != MC_SDRAM_TEST7)
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| 237 |
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continue;
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| 238 |
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CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
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| 239 |
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SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 2); /* 4 */
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| 240 |
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break;
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| 241 |
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case 8:
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| 242 |
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if ((MC_SDRAM_TESTS & MC_SDRAM_TEST8) != MC_SDRAM_TEST8)
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| 243 |
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continue;
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| 244 |
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CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
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| 245 |
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SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 3); /* 8 */
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| 246 |
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break;
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| 247 |
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case 9:
|
| 248 |
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if ((MC_SDRAM_TESTS & MC_SDRAM_TEST9) != MC_SDRAM_TEST9)
|
| 249 |
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continue;
|
| 250 |
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CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
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| 251 |
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SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 7); /* full page */
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| 252 |
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break;
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| 253 |
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case 10:
|
| 254 |
|
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if ((MC_SDRAM_TESTS & MC_SDRAM_TEST10) != MC_SDRAM_TEST10)
|
| 255 |
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continue;
|
| 256 |
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CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
|
| 257 |
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SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
|
| 258 |
|
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break;
|
| 259 |
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case 11:
|
| 260 |
|
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if ((MC_SDRAM_TESTS & MC_SDRAM_TEST11) != MC_SDRAM_TEST11)
|
| 261 |
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continue;
|
| 262 |
|
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CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
|
| 263 |
|
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SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
|
| 264 |
|
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SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 1); /* 2 */
|
| 265 |
|
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break;
|
| 266 |
|
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case 12:
|
| 267 |
|
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if ((MC_SDRAM_TESTS & MC_SDRAM_TEST12) != MC_SDRAM_TEST12)
|
| 268 |
|
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continue;
|
| 269 |
|
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CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
|
| 270 |
|
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SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
|
| 271 |
|
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SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 2); /* 4 */
|
| 272 |
|
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break;
|
| 273 |
|
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case 13:
|
| 274 |
|
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if ((MC_SDRAM_TESTS & MC_SDRAM_TEST13) != MC_SDRAM_TEST13)
|
| 275 |
|
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continue;
|
| 276 |
|
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CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
|
| 277 |
|
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SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
|
| 278 |
|
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SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 3); /* 8 */
|
| 279 |
|
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break;
|
| 280 |
|
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case 14:
|
| 281 |
|
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if ((MC_SDRAM_TESTS & MC_SDRAM_TEST14) != MC_SDRAM_TEST14)
|
| 282 |
|
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continue;
|
| 283 |
|
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CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
|
| 284 |
|
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SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
|
| 285 |
|
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SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 7); /* fullrow */
|
| 286 |
|
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break;
|
| 287 |
|
|
case 15:
|
| 288 |
|
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if ((MC_SDRAM_TESTS & MC_SDRAM_TEST15) != MC_SDRAM_TEST15)
|
| 289 |
|
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continue;
|
| 290 |
|
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SET_FLAG(*mc_csc, MC_CSC, KRO); /* keep row */
|
| 291 |
|
|
CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
|
| 292 |
|
|
SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
|
| 293 |
|
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SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 1); /* 2 */
|
| 294 |
|
|
break;
|
| 295 |
|
|
} /*switch test*/
|
| 296 |
|
|
|
| 297 |
|
|
printf ("Begin TEST %lu : CSC - 0x%08lX, TMS - 0x%08lX\n", test, *mc_csc, *mc_tms);
|
| 298 |
|
|
|
| 299 |
|
|
if (MC_SDRAM_ACC & MC_SDRAM_SROW) {
|
| 300 |
|
|
/* perform sequential row access */
|
| 301 |
|
|
printf("Seuential Row\n");
|
| 302 |
|
|
for (j=0; j<T_ROWS; j++) {
|
| 303 |
|
|
nAddress = mc_sel << 21;
|
| 304 |
|
|
nAddress |= MC_MEM_BASE;
|
| 305 |
|
|
nAddress += ( (j + T_ROW_OFF) << nRowSh);
|
| 306 |
|
|
|
| 307 |
|
|
gpio_pat ^= 0x00000008;
|
| 308 |
|
|
*rgpio_out = gpio_pat;
|
| 309 |
|
|
ret = mc_test_row(nAddress, nAddress + T_ROW_SIZE, MC_SDRAM_FLAGS);
|
| 310 |
|
|
|
| 311 |
|
|
printf("\trow - %lu: nAddress = 0x%08lX, ret = 0x%08lX\n", j, nAddress, ret);
|
| 312 |
|
|
|
| 313 |
|
|
if (ret) {
|
| 314 |
|
|
gpio_pat ^= 0x00000080;
|
| 315 |
|
|
*rgpio_out = gpio_pat;
|
| 316 |
|
|
report(ret);
|
| 317 |
|
|
return ret;
|
| 318 |
|
|
}
|
| 319 |
|
|
}
|
| 320 |
|
|
}
|
| 321 |
|
|
|
| 322 |
|
|
if (MC_SDRAM_ACC & MC_SDRAM_RROW) {
|
| 323 |
|
|
/* perform random row access */
|
| 324 |
|
|
printf("Random Row\n");
|
| 325 |
|
|
for (j=0; j<T_ROWS; j++) {
|
| 326 |
|
|
nAddress = mc_sel << 21;
|
| 327 |
|
|
nAddress |= MC_MEM_BASE;
|
| 328 |
|
|
nAddress += ( (T_ROW_OFF + random(nRows)) << nRowSh);
|
| 329 |
|
|
|
| 330 |
|
|
gpio_pat ^= 0x00000008;
|
| 331 |
|
|
*rgpio_out = gpio_pat;
|
| 332 |
|
|
ret = mc_test_row(nAddress, nAddress + T_ROW_SIZE, MC_SDRAM_FLAGS);
|
| 333 |
|
|
|
| 334 |
|
|
printf("\trow - %lu: nAddress = 0x%08lX, ret = 0x%08lX\n", j, nAddress, ret);
|
| 335 |
|
|
|
| 336 |
|
|
if (ret) {
|
| 337 |
|
|
gpio_pat ^= 0x00000080;
|
| 338 |
|
|
*rgpio_out = gpio_pat;
|
| 339 |
|
|
report(ret);
|
| 340 |
|
|
return ret;
|
| 341 |
|
|
}
|
| 342 |
|
|
}
|
| 343 |
|
|
}
|
| 344 |
|
|
|
| 345 |
|
|
if (MC_SDRAM_ACC & MC_SDRAM_SGRP) {
|
| 346 |
|
|
/* perform sequential row in group access */
|
| 347 |
|
|
printf("Sequential Group ");
|
| 348 |
|
|
|
| 349 |
|
|
printf("Group Size = %d\n", MC_SDRAM_GROUPSIZE);
|
| 350 |
|
|
for (i=0; i<T_GROUPS; i++) {
|
| 351 |
|
|
nRowGrp = random(nRows - MC_SDRAM_GROUPSIZE) + T_ROW_OFF;
|
| 352 |
|
|
for (j=0; j<MC_SDRAM_GROUPSIZE; j++) {
|
| 353 |
|
|
nAddress = mc_sel << 21;
|
| 354 |
|
|
nAddress |= MC_MEM_BASE;
|
| 355 |
|
|
nAddress += ((nRowGrp+j) << nRowSh);
|
| 356 |
|
|
|
| 357 |
|
|
gpio_pat ^= 0x00000008;
|
| 358 |
|
|
*rgpio_out = gpio_pat;
|
| 359 |
|
|
ret = mc_test_row(nAddress, nAddress + T_ROW_SIZE, MC_SDRAM_FLAGS);
|
| 360 |
|
|
|
| 361 |
|
|
printf("\trow - %lu: nAddress = 0x%08lX, ret = 0x%08lX\n", j, nAddress, ret);
|
| 362 |
|
|
|
| 363 |
|
|
if (ret) {
|
| 364 |
|
|
gpio_pat ^= 0x00000080;
|
| 365 |
|
|
*rgpio_out = gpio_pat;
|
| 366 |
|
|
report(ret);
|
| 367 |
|
|
return ret;
|
| 368 |
|
|
}
|
| 369 |
|
|
}
|
| 370 |
|
|
}
|
| 371 |
|
|
}
|
| 372 |
|
|
|
| 373 |
|
|
if (MC_SDRAM_ACC & MC_SDRAM_RGRP) {
|
| 374 |
|
|
/* perform random row in group access */
|
| 375 |
|
|
printf("Random Group ");
|
| 376 |
|
|
|
| 377 |
|
|
printf("Group Size = %d\n", MC_SDRAM_GROUPSIZE);
|
| 378 |
|
|
for (i=0; i<T_GROUPS; i++) {
|
| 379 |
|
|
nRowGrp = random(nRows - T_GROUPS) + T_ROW_OFF;
|
| 380 |
|
|
for (j=0; j<MC_SDRAM_GROUPSIZE; j++) {
|
| 381 |
|
|
nAddress = mc_sel << 21;
|
| 382 |
|
|
nAddress |= MC_MEM_BASE;
|
| 383 |
|
|
nAddress += ((nRowGrp + random(MC_SDRAM_GROUPSIZE)) << nRowSh);
|
| 384 |
|
|
|
| 385 |
|
|
gpio_pat ^= 0x00000008;
|
| 386 |
|
|
*rgpio_out = gpio_pat;
|
| 387 |
|
|
ret = mc_test_row(nAddress, nAddress + T_ROW_SIZE, MC_SDRAM_FLAGS);
|
| 388 |
|
|
|
| 389 |
|
|
printf("\trow - %lu: nAddress = 0x%08lX, ret = 0x%08lX\n", j, nAddress, ret);
|
| 390 |
|
|
|
| 391 |
|
|
if (ret) {
|
| 392 |
|
|
gpio_pat ^= 0x00000080;
|
| 393 |
|
|
*rgpio_out = gpio_pat;
|
| 394 |
|
|
report(ret);
|
| 395 |
|
|
return ret;
|
| 396 |
|
|
}
|
| 397 |
|
|
}
|
| 398 |
|
|
}
|
| 399 |
|
|
} /*for groups*/
|
| 400 |
|
|
|
| 401 |
|
|
} /*for test*/
|
| 402 |
|
|
} /*if*/
|
| 403 |
|
|
} /*for CS*/
|
| 404 |
|
|
printf("--- End SDRAM tests ---\n");
|
| 405 |
|
|
report(0xDEADDEAD);
|
| 406 |
|
|
|
| 407 |
|
|
gpio_pat ^= 0x00000020;
|
| 408 |
|
|
*rgpio_out = gpio_pat;
|
| 409 |
|
|
|
| 410 |
|
|
return 0;
|
| 411 |
|
|
} /* main */
|
