OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [mc-ssram/] [mc-ssram.c] - Blame information for rev 112

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 90 jeremybenn
/* mc_ssram.c - Memory Controller testbench SSRAM test
2
 
3
   Copyright (C) 2001 Ivan Guzvinec
4
   Copyright (C) 2010 Embecosm Limited
5
 
6
   Contributor Ivan Guzvinec <ivang@opencores.org>
7
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
8
 
9
   This file is part of OpenRISC 1000 Architectural Simulator.
10
 
11
   This program is free software; you can redistribute it and/or modify it
12
   under the terms of the GNU General Public License as published by the Free
13
   Software Foundation; either version 3 of the License, or (at your option)
14
   any later version.
15
 
16
   This program is distributed in the hope that it will be useful, but WITHOUT
17
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
   more details.
20
 
21
   You should have received a copy of the GNU General Public License along
22
   with this program.  If not, see <http:  www.gnu.org/licenses/>.  */
23
 
24
/* ----------------------------------------------------------------------------
25
   This code is commented throughout for use with Doxygen.
26
   --------------------------------------------------------------------------*/
27
 
28
#include "support.h"
29
 
30
#include "mc-common.h"
31
#include "mc-ssram.h"
32
 
33
#include "config.h"
34 112 jeremybenn
#include "mc-defines.h"
35 90 jeremybenn
#include "gpio.h"
36
#include "fields.h"
37
 
38
typedef volatile unsigned long *REGISTER;
39
 
40
REGISTER mc_poc        = (unsigned long*)(MC_BASE + MC_POC);
41
REGISTER mc_csr        = (unsigned long*)(MC_BASE + MC_CSR);
42
REGISTER mc_ba_mask    = (unsigned long*)(MC_BASE + MC_BA_MASK);
43
 
44
REGISTER rgpio_out     = (unsigned long*)(GPIO_BASE + RGPIO_OUT);
45
REGISTER rgpio_in      = (unsigned long*)(GPIO_BASE + RGPIO_IN);
46
 
47
unsigned long lpoc;
48
unsigned char mc_cs;
49
 
50
unsigned long set_config()
51
{
52
    REGISTER mc_csc;
53
    unsigned char ch;
54
 
55
    lpoc = *mc_poc;
56
 
57
    for (ch=0; ch<8; ch++) {
58
        if (MC_SSRAM_CSMASK && (0x01 << ch) ) {
59
            mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
60
            SET_FIELD(*mc_csc, MC_CSC, SEL, mc_ssram_cs[ch].M);
61
            SET_FLAG(*mc_csc, MC_CSC, EN);
62
            printf ("Channel Config %d - CSC = 0x%08lX\n", ch, *mc_csc);
63
        }
64
    }
65
 
66
    return 0;
67
}
68
 
69
unsigned long get_config()
70
{
71
  REGISTER mc_csc;
72
  REGISTER mc_tms;
73
  unsigned char ch;
74
 
75
  mc_cs = 0;
76
  for (ch=0; ch<8; ch++) {
77
    mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
78
    mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
79
    if ( (GET_FIELD(*mc_csc, MC_CSC, MEMTYPE) == 1) &&
80
         (TEST_FLAG(*mc_csc, MC_CSC, EN) == 1     ) ) {
81
      mc_ssram_cs[ch].M  = GET_FIELD(*mc_csc, MC_CSC, SEL);
82
      mc_cs |= (1 << ch);
83
 
84
      printf("get_config(%d) : M=0x%0lx\n", ch,
85
             mc_ssram_cs[ch].M);
86
    }
87
  }
88
  printf("get_config() : cs=0x%0x\n", mc_cs);
89
  return 0;
90
}
91
 
92
int main()
93
{
94
    unsigned long ret;
95
    unsigned char ch;
96
 
97
    unsigned long test;
98
    unsigned long gpio_pat;
99
 
100
    unsigned long nAddress;
101
    unsigned long nMemSize;
102
    unsigned long mc_sel;
103
 
104
    REGISTER mc_tms;
105
    REGISTER mc_csc;
106
 
107
    *rgpio_out = 0xFFFFFFFF;
108
 
109
#ifdef MC_READ_CONF
110
    if (get_config()) {
111
      printf("Error reading MC configuration\n");
112
      report(0x000000001);
113
      return(1);
114
    }
115
#else
116
    mc_cs = MC_SSRAM_CSMASK;
117
#endif
118
 
119
    *rgpio_out = 0;
120
    for (ch=0; ch<8; ch++) {
121
        if (mc_cs & (0x01 << ch) ) {
122
            printf ("--- Begin Test on CS%d ---\n", ch);
123
 
124
            mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
125
            mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
126
            mc_sel = GET_FIELD(*mc_csc, MC_CSC, SEL);
127
 
128
            printf ("CS configuration : CSC - 0x%08lX, TMS - 0x%08lXu\n",
129
                    *mc_csc, *mc_tms);
130
 
131
            for (test=0; test<4; test++) {
132
                /* configure MC*/
133
                CLEAR_FLAG(*mc_csc, MC_CSC, PEN); /* no parity */
134
                CLEAR_FLAG(*mc_csc, MC_CSC, BAS); /* bank after column */
135
                CLEAR_FLAG(*mc_csc, MC_CSC, WP);  /* write enable */
136
 
137
                switch (test) {
138
                case 0:
139
                    if ((MC_SSRAM_TESTS & MC_SSRAM_TEST0) != MC_SSRAM_TEST0)
140
                        continue;
141
                    break;
142
                case 1:
143
                    if ((MC_SSRAM_TESTS & MC_SSRAM_TEST1) != MC_SSRAM_TEST1)
144
                        continue;
145
                    SET_FLAG(*mc_csc, MC_CSC, PEN); /* parity */
146
                    break;
147
                case 2:
148
                    if ((MC_SSRAM_TESTS & MC_SSRAM_TEST2) != MC_SSRAM_TEST2)
149
                        continue;
150
                    SET_FLAG(*mc_csc, MC_CSC, BAS); /* bank after row */
151
                    break;
152
                case 3:
153
                    if ((MC_SSRAM_TESTS & MC_SSRAM_TEST3) != MC_SSRAM_TEST3)
154
                        continue;
155
                    SET_FLAG(*mc_csc, MC_CSC, WP);  /* RO */
156
                    break;
157
                } /*switch test*/
158
 
159
                printf ("Begin TEST %lu : CSC - 0x%08lX, TMS - 0x%08lX\n", test, *mc_csc, *mc_tms);
160
 
161
                nAddress = mc_sel << 21;
162
                nAddress |= MC_MEM_BASE;
163
                nMemSize = ( ((*mc_ba_mask && 0x000000FF) + 1) << 21);
164
 
165
                gpio_pat ^= 0x00000008;
166
                *rgpio_out = gpio_pat;
167
                ret = mc_test_row(nAddress, nAddress + nMemSize, MC_SSRAM_FLAGS);
168
 
169
                printf("\trow tested: nAddress = 0x%08lX, ret = 0x%08lX\n", nAddress, ret);
170
 
171
                if (ret) {
172
                    gpio_pat ^= 0x00000080;
173
                    *rgpio_out = gpio_pat;
174
                    report(ret);
175
                    return ret;
176
                }
177
 
178
            } /*for test*/
179
        } /*if*/
180
    } /*for CS*/
181
    printf("--- End SSRAM tests ---\n");
182
    report(0xDEADDEAD);
183
 
184
    gpio_pat ^= 0x00000020;
185
    *rgpio_out = gpio_pat;
186
 
187
    return 0;
188
} /* main */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.