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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [mc-ssram/] [mc-ssram.c] - Blame information for rev 146

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1 90 jeremybenn
/* mc_ssram.c - Memory Controller testbench SSRAM test
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   Copyright (C) 2001 Ivan Guzvinec
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   Copyright (C) 2010 Embecosm Limited
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   Contributor Ivan Guzvinec <ivang@opencores.org>
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   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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   This file is part of OpenRISC 1000 Architectural Simulator.
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   This program is free software; you can redistribute it and/or modify it
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   under the terms of the GNU General Public License as published by the Free
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   Software Foundation; either version 3 of the License, or (at your option)
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   any later version.
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   This program is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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   more details.
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   You should have received a copy of the GNU General Public License along
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   with this program.  If not, see <http:  www.gnu.org/licenses/>.  */
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/* ----------------------------------------------------------------------------
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   This code is commented throughout for use with Doxygen.
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   --------------------------------------------------------------------------*/
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#include "support.h"
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#include "mc-common.h"
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#include "mc-ssram.h"
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#include "config.h"
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#include "mc-defines.h"
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#include "gpio.h"
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#include "fields.h"
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typedef volatile unsigned long *REGISTER;
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REGISTER mc_poc        = (unsigned long*)(MC_BASE + MC_POC);
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REGISTER mc_csr        = (unsigned long*)(MC_BASE + MC_CSR);
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REGISTER mc_ba_mask    = (unsigned long*)(MC_BASE + MC_BA_MASK);
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REGISTER rgpio_out     = (unsigned long*)(GPIO_BASE + RGPIO_OUT);
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REGISTER rgpio_in      = (unsigned long*)(GPIO_BASE + RGPIO_IN);
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unsigned long lpoc;
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unsigned char mc_cs;
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unsigned long set_config()
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{
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    REGISTER mc_csc;
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    unsigned char ch;
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    lpoc = *mc_poc;
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    for (ch=0; ch<8; ch++) {
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        if (MC_SSRAM_CSMASK && (0x01 << ch) ) {
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            mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
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            SET_FIELD(*mc_csc, MC_CSC, SEL, mc_ssram_cs[ch].M);
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            SET_FLAG(*mc_csc, MC_CSC, EN);
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            printf ("Channel Config %d - CSC = 0x%08lX\n", ch, *mc_csc);
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        }
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    }
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    return 0;
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}
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unsigned long get_config()
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{
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  REGISTER mc_csc;
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  REGISTER mc_tms;
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  unsigned char ch;
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  mc_cs = 0;
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  for (ch=0; ch<8; ch++) {
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    mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
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    mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
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    if ( (GET_FIELD(*mc_csc, MC_CSC, MEMTYPE) == 1) &&
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         (TEST_FLAG(*mc_csc, MC_CSC, EN) == 1     ) ) {
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      mc_ssram_cs[ch].M  = GET_FIELD(*mc_csc, MC_CSC, SEL);
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      mc_cs |= (1 << ch);
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      printf("get_config(%d) : M=0x%0lx\n", ch,
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             mc_ssram_cs[ch].M);
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    }
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  }
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  printf("get_config() : cs=0x%0x\n", mc_cs);
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  return 0;
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}
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int main()
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{
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    unsigned long ret;
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    unsigned char ch;
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    unsigned long test;
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    unsigned long gpio_pat;
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    unsigned long nAddress;
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    unsigned long nMemSize;
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    unsigned long mc_sel;
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    REGISTER mc_tms;
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    REGISTER mc_csc;
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    *rgpio_out = 0xFFFFFFFF;
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#ifdef MC_READ_CONF
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    if (get_config()) {
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      printf("Error reading MC configuration\n");
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      report(0x000000001);
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      return(1);
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    }
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#else
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    mc_cs = MC_SSRAM_CSMASK;
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#endif
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    *rgpio_out = 0;
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    for (ch=0; ch<8; ch++) {
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        if (mc_cs & (0x01 << ch) ) {
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            printf ("--- Begin Test on CS%d ---\n", ch);
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            mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
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            mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
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            mc_sel = GET_FIELD(*mc_csc, MC_CSC, SEL);
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            printf ("CS configuration : CSC - 0x%08lX, TMS - 0x%08lXu\n",
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                    *mc_csc, *mc_tms);
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            for (test=0; test<4; test++) {
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                /* configure MC*/
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                CLEAR_FLAG(*mc_csc, MC_CSC, PEN); /* no parity */
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                CLEAR_FLAG(*mc_csc, MC_CSC, BAS); /* bank after column */
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                CLEAR_FLAG(*mc_csc, MC_CSC, WP);  /* write enable */
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                switch (test) {
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                case 0:
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                    if ((MC_SSRAM_TESTS & MC_SSRAM_TEST0) != MC_SSRAM_TEST0)
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                        continue;
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                    break;
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                case 1:
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                    if ((MC_SSRAM_TESTS & MC_SSRAM_TEST1) != MC_SSRAM_TEST1)
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                        continue;
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                    SET_FLAG(*mc_csc, MC_CSC, PEN); /* parity */
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                    break;
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                case 2:
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                    if ((MC_SSRAM_TESTS & MC_SSRAM_TEST2) != MC_SSRAM_TEST2)
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                        continue;
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                    SET_FLAG(*mc_csc, MC_CSC, BAS); /* bank after row */
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                    break;
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                case 3:
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                    if ((MC_SSRAM_TESTS & MC_SSRAM_TEST3) != MC_SSRAM_TEST3)
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                        continue;
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                    SET_FLAG(*mc_csc, MC_CSC, WP);  /* RO */
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                    break;
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                } /*switch test*/
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                printf ("Begin TEST %lu : CSC - 0x%08lX, TMS - 0x%08lX\n", test, *mc_csc, *mc_tms);
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                nAddress = mc_sel << 21;
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                nAddress |= MC_MEM_BASE;
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                nMemSize = ( ((*mc_ba_mask && 0x000000FF) + 1) << 21);
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                gpio_pat ^= 0x00000008;
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                *rgpio_out = gpio_pat;
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                ret = mc_test_row(nAddress, nAddress + nMemSize, MC_SSRAM_FLAGS);
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                printf("\trow tested: nAddress = 0x%08lX, ret = 0x%08lX\n", nAddress, ret);
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                if (ret) {
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                    gpio_pat ^= 0x00000080;
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                    *rgpio_out = gpio_pat;
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                    report(ret);
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                    return ret;
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                }
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            } /*for test*/
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        } /*if*/
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    } /*for CS*/
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    printf("--- End SSRAM tests ---\n");
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    report(0xDEADDEAD);
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    gpio_pat ^= 0x00000020;
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    *rgpio_out = gpio_pat;
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    return 0;
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} /* main */

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