URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [mmu/] [mmu-asm.S] - Blame information for rev 346

Go to most recent revision | Details | Compare with Previous | View Log


/* mmu-asm.S. Machine code to support Or1ksim MMU test
 
   Copyright (C) 1999-2006 OpenCores
   Copyright (C) 2010 Embecosm Limited
 
   Contributors various OpenCores participants
   Contributor Jeremy Bennett 
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see .  */
 
/* ----------------------------------------------------------------------------
   This code is commented throughout for use with Doxygen.
   --------------------------------------------------------------------------*/
#include "spr-defs.h"
 
#define PAGE_SIZE 8192
#define DTLB_PR_NOLIMIT  (SPR_DTLBTR_URE  | \
                          SPR_DTLBTR_UWE  | \
                          SPR_DTLBTR_SRE  | \
                          SPR_DTLBTR_SWE  )
#define ITLB_PR_NOLIMIT  (SPR_ITLBTR_SXE  | \
                          SPR_ITLBTR_UXE  )
        .global lo_dmmu_en
        .global lo_immu_en
        .global lo_dtlb_ci_test
        .global lo_itlb_ci_test
        .global testjump
        .global ic_enable
        .global ic_disable
        .global dc_enable
        .global dc_disable
 
lo_dmmu_en:
        l.mfspr r11,r0,SPR_SR
        l.ori   r11,r11,SPR_SR_DME
        l.mtspr r0,r11,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
lo_dmmu_dis:
        l.addi  r13,r0,-1
        l.xori  r13,r13,SPR_SR_DME
        l.mfspr r11,r0,SPR_SR
        l.and   r11,r11,r13
        l.mtspr r0,r11,SPR_SR
        l.jr    r9
        l.nop
 
lo_immu_en:
        l.mfspr r11,r0,SPR_SR
        l.ori   r11,r11,SPR_SR_IME
        l.mtspr r0,r11,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
lo_immu_dis:
        l.addi  r13,r0,-1
        l.xori  r13,r13,SPR_SR_IME
        l.mfspr r11,r0,SPR_SR
        l.and   r11,r11,r13
        l.mtspr r0,r11,SPR_SR
        l.jr    r9
        l.nop
 
testjump:
        l.movhi r5,0x4800
        l.ori   r5,r5,0x4800
        l.sw    0x0(r3),r5
        l.movhi r5,0x1500
        l.ori   r5,r5,0x0000
        l.sw    0x4(r3),r5
        l.or    r5,r0,r9
        l.jalr  r4
        l.nop
        l.or    r9,r0,r5
        l.jr    r9
        l.nop
 
ic_enable:
        /* Disable IC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_ICE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        /* Invalidate IC */
        l.addi  r13,r0,0
        l.addi  r11,r0,8192
1:
        l.mtspr r0,r13,SPR_ICBIR
        l.sfne  r13,r11
        l.bf    1b
        l.addi  r13,r13,16
 
        /* Enable IC */
        l.mfspr r13,r0,SPR_SR
        l.ori   r13,r13,SPR_SR_ICE
        l.mtspr r0,r13,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        l.jr    r9
        l.nop
 
ic_disable:
        /* Disable IC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_ICE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        l.jr    r9
        l.nop
 
dc_enable:
        /* Disable DC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_DCE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        /* Flush DC */
        l.addi  r13,r0,0
        l.addi  r11,r0,8192
1:
        l.mtspr r0,r13,SPR_DCBIR
        l.sfne  r13,r11
        l.bf    1b
        l.addi  r13,r13,16
 
        /* Enable DC */
        l.mfspr r13,r0,SPR_SR
        l.ori   r13,r13,SPR_SR_DCE
        l.mtspr r0,r13,SPR_SR
 
        l.jr    r9
        l.nop
 
dc_disable:
        /* Disable DC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_DCE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        l.jr    r9
        l.nop
 
        /* dtlb_ic_test(unsigned long add, unsigned long set) */
lo_dtlb_ci_test:
        l.addi  r1,r1,-4
        l.sw    0(r1),r9
 
        l.addi  r8,r0,0
 
        l.movhi r5,hi(0x01234567)
        l.ori   r5,r5,lo(0x01234567)
        l.sw    0(r3),r5
        l.movhi r5,hi(0x89abcdef)
        l.ori   r5,r5,lo(0x89abcdef)
        l.sw    (PAGE_SIZE - 4)(r3),r5
 
        l.ori   r5,r3,SPR_DTLBMR_V
        l.mtspr r4,r5,SPR_DTLBMR_BASE(0)
 
        l.ori   r5,r3,(DTLB_PR_NOLIMIT  | SPR_DTLBTR_CI)
        l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
 
        l.addi  r5,r3,PAGE_SIZE
        l.ori   r5,r5,SPR_DTLBMR_V
        l.addi  r6,r4,1
        l.mtspr r6,r5,SPR_DTLBMR_BASE(0)
 
        l.addi  r5,r3,PAGE_SIZE
        l.ori   r5,r5,(DTLB_PR_NOLIMIT  | SPR_DTLBTR_CI)
        l.addi  r6,r4,1
        l.mtspr r6,r5,SPR_DTLBTR_BASE(0)
 
        l.jal   lo_dmmu_en
        l.nop
        l.jal   dc_enable
        l.nop
 
        l.movhi r6,hi(0x01234567)
        l.ori   r6,r6,lo(0x01234567)
        l.lwz   r5,0(r3)
        l.sfeq  r6,r5
        l.bnf   11f
        l.nop
        l.movhi r6,hi(0x89abcdef)
        l.ori   r6,r6,lo(0x89abcdef)
        l.lwz   r5,(PAGE_SIZE - 4)(r3)
        l.sfeq  r6,r5
        l.bnf   12f
        l.nop
 
        l.movhi r5,hi(0x76543210)
        l.ori   r5,r5,lo(0x76543210)
        l.sw    0(r3),r5
        l.movhi r5,hi(0xfedcba9)
        l.ori   r5,r5,lo(0xfedcba9)
        l.sw    (PAGE_SIZE - 4)(r3),r5
 
        l.jal   lo_dmmu_dis
        l.nop
        l.ori   r5,r3,(DTLB_PR_NOLIMIT)
        l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
        l.jal   lo_dmmu_en
        l.nop
 
        l.movhi r6,hi(0x76543210)
        l.ori   r6,r6,lo(0x76543210)
        l.lwz   r5,0(r3)
        l.sfeq  r6,r5
        l.bnf   13f
        l.nop
        l.movhi r6,hi(0xfedcba9)
        l.ori   r6,r6,lo(0xfedcba9)
        l.lwz   r5,(PAGE_SIZE - 4)(r3)
        l.sfeq  r6,r5
        l.bnf   14f
        l.nop
 
        l.jal   lo_dmmu_dis
        l.nop
        l.ori   r5,r3,(DTLB_PR_NOLIMIT | SPR_DTLBTR_CI)
        l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
        l.jal   lo_dmmu_en
        l.nop
 
        l.movhi r5,hi(0x00112233)
        l.ori   r5,r5,lo(0x00112233)
        l.sw    0(r3),r5
#if 1
        l.movhi r5,hi(0x44556677)
        l.ori   r5,r5,lo(0x44556677)
        l.sw    4(r3),r5
        l.movhi r5,hi(0x8899aabb)
        l.ori   r5,r5,lo(0x8899aabb)
        l.sw    8(r3),r5
        l.movhi r5,hi(0xccddeeff)
        l.ori   r5,r5,lo(0xccddeeff)
        l.sw    12(r3),r5
#endif
        l.movhi r5,hi(0x44556677)
        l.ori   r5,r5,lo(0x44556677)
        l.sw    (PAGE_SIZE - 4)(r3),r5
 
        l.movhi r6,hi(0x00112233)
        l.ori   r6,r6,lo(0x00112233)
        l.lwz   r5,0(r3)
        l.sfeq  r6,r5
        l.bnf   15f
        l.nop
        l.movhi r6,hi(0x44556677)
        l.ori   r6,r6,lo(0x44556677)
        l.lwz   r5,(PAGE_SIZE - 4)(r3)
        l.sfeq  r6,r5
        l.bnf   16f
        l.nop
 
        l.jal   lo_dmmu_dis
        l.nop
        l.ori   r5,r3,(DTLB_PR_NOLIMIT)
        l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
        l.jal   lo_dmmu_en
        l.nop
 
        l.movhi r6,hi(0x76543210)
        l.ori   r6,r6,lo(0x76543210)
        l.lwz   r5,0(r3)
        l.sfeq  r6,r5
        l.bnf   17f
        l.nop
 
        l.movhi r6,hi(0xfedcba9)
        l.ori   r6,r6,lo(0xfedcba9)
        l.lwz   r5,(PAGE_SIZE - 4)(r3)
        l.sfeq  r6,r5
        l.bnf   18f
        l.nop
 
        /* Invalidate cache */
        l.jal   dc_disable
        l.nop
 
        l.movhi r5,hi(0x00112233)
        l.ori   r5,r5,lo(0x00112233)
        l.sw    12(r3),r5
        l.movhi r5,hi(0x44556677)
        l.ori   r5,r5,lo(0x44556677)
        l.sw    8(r3),r5
        l.movhi r5,hi(0x8899aabb)
        l.ori   r5,r5,lo(0x8899aabb)
        l.sw    4(r3),r5
        l.movhi r5,hi(0xccddeeff)
        l.ori   r5,r5,lo(0xccddeeff)
        l.sw    0(r3),r5
        l.movhi r5,hi(0x44556677)
        l.ori   r5,r5,lo(0x44556677)
        l.sw    (PAGE_SIZE - 4)(r3),r5
 
        l.jal   dc_enable
        l.nop
 
        /* I want this part to execute as fast as possible */
        l.jal   ic_enable
        l.nop
 
        l.addi  r5,r3,PAGE_SIZE
 
        /* This jump is just to be shure that the following
           instructions will get into IC */
        l.j     1f
        l.nop
        /* This shuld trigger cahe line refill */
2:      l.lwz   r6,0(r3)
        l.j     2f
        /* This load is from non cached area and may cause some problems
           in previuos refill, which is probably still in progress */
        l.lwz   r6,0(r5)
1:      l.j     2b
        l.nop
2:
        /* Check the line that was previosly refilled */
        l.movhi r6,hi(0x00112233)
        l.ori   r6,r6,lo(0x00112233)
        l.lwz   r5,12(r3)
        l.sfeq  r6,r5
        l.bnf   19f
        l.nop
        l.movhi r6,hi(0x44556677)
        l.ori   r6,r6,lo(0x44556677)
        l.lwz   r5,8(r3)
        l.sfeq  r6,r5
        l.bnf   19f
        l.nop
        l.movhi r6,hi(0x8899aabb)
        l.ori   r6,r6,lo(0x8899aabb)
        l.lwz   r5,4(r3)
        l.sfeq  r6,r5
        l.bnf   19f
        l.nop
        l.movhi r6,hi(0xccddeeff)
        l.ori   r6,r6,lo(0xccddeeff)
        l.lwz   r5,0(r3)
        l.sfeq  r6,r5
        l.bnf   19f
        l.nop
 
        l.jal   dc_disable
        l.nop
 
        l.jal   lo_dmmu_dis
        l.nop
 
        l.j     10f
        l.nop
 
19:     l.addi  r8,r8,1
18:     l.addi  r8,r8,1
17:     l.addi  r8,r8,1
16:     l.addi  r8,r8,1
15:     l.addi  r8,r8,1
14:     l.addi  r8,r8,1
13:     l.addi  r8,r8,1
12:     l.addi  r8,r8,1
11:     l.addi  r8,r8,1
 
10:     l.jal   dc_disable
        l.nop
 
        l.jal   ic_disable
        l.nop
 
        l.jal   lo_dmmu_dis
        l.nop
 
        l.addi  r11,r8,0
        l.sw    0(r0),r8
        l.sw    4(r0),r5
 
        l.lwz   r9,0(r1)
        l.jr    r9
        l.addi  r1,r1,4
 
        /* itlb_ic_test(unsigned long add, unsigned long set) */
lo_itlb_ci_test:
        l.addi  r1,r1,-4
        l.sw    0(r1),r9
 
        l.addi  r8,r0,0
 
        /* Copy the code to the prepeared location */
        l.addi  r7,r0,88
        l.movhi r5,hi(ci_test)
        l.ori   r5,r5,lo(ci_test)
        l.addi  r6,r3,0
1:      l.lwz   r11,0(r5)
        l.sw    0(r6),r11
        l.addi  r5,r5,4
        l.addi  r6,r6,4
        l.addi  r7,r7,-4
        l.sfeqi r7,0
        l.bnf   1b
        l.nop
 
        l.ori   r5,r3,SPR_ITLBMR_V
        l.mtspr r4,r5,SPR_ITLBMR_BASE(0)
 
        l.ori   r5,r3,ITLB_PR_NOLIMIT
        l.mtspr r4,r5,SPR_ITLBTR_BASE(0)
 
        l.jal   lo_immu_en
        l.nop
        l.jal   ic_enable
        l.nop
 
        l.addi  r5,r0,0
        l.addi  r6,r0,0
        l.jalr  r3
        l.nop
 
        l.sfeqi r5,5
        l.bnf   11f
        l.nop
 
        /* Copy the code to the prepeared location */
        l.addi  r7,r0,20
        l.movhi r5,hi(ic_refill_test)
        l.ori   r5,r5,lo(ic_refill_test)
        l.addi  r6,r3,12
1:      l.lwz   r11,0(r5)
        l.sw    0(r6),r11
        l.addi  r5,r5,4
        l.addi  r6,r6,4
        l.addi  r7,r7,-4
        l.sfeqi r7,0
        l.bnf   1b
        l.nop
 
        l.jal   ic_disable
        l.nop
        l.jal   ic_enable
        l.nop
 
        l.addi  r5,r0,0
        l.addi  r6,r3,12
        l.jalr  r6
        l.nop
        l.addi  r6,r3,16
        l.jalr  r6
        l.nop
 
        l.sfeqi r5,4
        l.bnf   12f
        l.nop
 
        l.j     10f
        l.nop
 
12:     l.addi  r8,r8,1
11:     l.addi  r8,r8,1
 
10:     l.jal   ic_disable
        l.nop
 
        l.jal   lo_dmmu_dis
        l.nop
 
        l.addi  r11,r8,0
        l.sw    0(r0),r11
        l.sw    4(r0),r5
 
        l.lwz   r9,0(r1)
        l.jr    r9
        l.addi  r1,r1,4
 
ci_test:
3:      l.addi  r5,r5,1
 
        l.sfeqi r6,0x01
        l.bnf   1f
        l.nop
 
        l.addi  r13,r0,-1
        l.xori  r13,r13,SPR_SR_IME
        l.mfspr r11,r0,SPR_SR
        l.and   r13,r11,r13
        l.mtspr r0,r13,SPR_SR
 
        l.ori   r7,r3,(ITLB_PR_NOLIMIT  | SPR_ITLBTR_CI)
        l.mtspr r4,r7,SPR_ITLBTR_BASE(0)
 
        l.mtspr r0,r11,SPR_SR
 
1:      l.lwz   r7,0(r3)
        l.addi  r7,r7,1
        l.sw    0(r3),r7
 
2:      l.addi  r6,r6,1
        l.sfeqi r6,3
        l.bnf   3b
        l.nop
 
        l.jr    r9
        l.nop
 
 
ic_refill_test:
        l.jr    r9
        l.addi  r5,r5,1
        l.addi  r5,r5,1
        l.jr    r9
        l.addi  r5,r5,1

Line No.	Rev	Author	Line
1	90	jeremybenn	`/* mmu-asm.S. Machine code to support Or1ksim MMU test`
2
3			`Copyright (C) 1999-2006 OpenCores`
4			`Copyright (C) 2010 Embecosm Limited`
5
6			`Contributors various OpenCores participants`
7			`Contributor Jeremy Bennett`
8
9			`This file is part of OpenRISC 1000 Architectural Simulator.`
10
11			`This program is free software; you can redistribute it and/or modify it`
12			`under the terms of the GNU General Public License as published by the Free`
13			`Software Foundation; either version 3 of the License, or (at your option)`
14			`any later version.`
15
16			`This program is distributed in the hope that it will be useful, but WITHOUT`
17			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
18			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
19			`more details.`
20
21			`You should have received a copy of the GNU General Public License along`
22			`with this program. If not, see . */`
23
24			`/* ----------------------------------------------------------------------------`
25			`This code is commented throughout for use with Doxygen.`
26			`--------------------------------------------------------------------------*/`
27			`#include "spr-defs.h"`
28
29			`#define PAGE_SIZE 8192`
30			`#define DTLB_PR_NOLIMIT (SPR_DTLBTR_URE \| \`
31			`SPR_DTLBTR_UWE \| \`
32			`SPR_DTLBTR_SRE \| \`
33			`SPR_DTLBTR_SWE )`
34			`#define ITLB_PR_NOLIMIT (SPR_ITLBTR_SXE \| \`
35			`SPR_ITLBTR_UXE )`
36	346	jeremybenn	`.global lo_dmmu_en`
37			`.global lo_immu_en`
38			`.global lo_dtlb_ci_test`
39			`.global lo_itlb_ci_test`
40			`.global testjump`
41			`.global ic_enable`
42			`.global ic_disable`
43			`.global dc_enable`
44			`.global dc_disable`
45	90	jeremybenn
46	346	jeremybenn	`lo_dmmu_en:`
47			`l.mfspr r11,r0,SPR_SR`
48	90	jeremybenn	`l.ori r11,r11,SPR_SR_DME`
49			`l.mtspr r0,r11,SPR_ESR_BASE`
50			`l.mtspr r0,r9,SPR_EPCR_BASE`
51			`l.rfe`
52			`l.nop`
53
54	346	jeremybenn	`lo_dmmu_dis:`
55	90	jeremybenn	`l.addi r13,r0,-1`
56			`l.xori r13,r13,SPR_SR_DME`
57			`l.mfspr r11,r0,SPR_SR`
58			`l.and r11,r11,r13`
59			`l.mtspr r0,r11,SPR_SR`
60			`l.jr r9`
61			`l.nop`
62
63	346	jeremybenn	`lo_immu_en:`
64			`l.mfspr r11,r0,SPR_SR`
65	90	jeremybenn	`l.ori r11,r11,SPR_SR_IME`
66			`l.mtspr r0,r11,SPR_ESR_BASE`
67			`l.mtspr r0,r9,SPR_EPCR_BASE`
68			`l.rfe`
69			`l.nop`
70
71	346	jeremybenn	`lo_immu_dis:`
72	90	jeremybenn	`l.addi r13,r0,-1`
73			`l.xori r13,r13,SPR_SR_IME`
74			`l.mfspr r11,r0,SPR_SR`
75			`l.and r11,r11,r13`
76			`l.mtspr r0,r11,SPR_SR`
77			`l.jr r9`
78			`l.nop`
79
80	346	jeremybenn	`testjump:`
81	90	jeremybenn	`l.movhi r5,0x4800`
82			`l.ori r5,r5,0x4800`
83			`l.sw 0x0(r3),r5`
84			`l.movhi r5,0x1500`
85			`l.ori r5,r5,0x0000`
86			`l.sw 0x4(r3),r5`
87			`l.or r5,r0,r9`
88			`l.jalr r4`
89			`l.nop`
90			`l.or r9,r0,r5`
91			`l.jr r9`
92			`l.nop`
93
94	346	jeremybenn	`ic_enable:`
95	90	jeremybenn	`/* Disable IC */`
96			`l.mfspr r13,r0,SPR_SR`
97			`l.addi r11,r0,-1`
98			`l.xori r11,r11,SPR_SR_ICE`
99			`l.and r11,r13,r11`
100			`l.mtspr r0,r11,SPR_SR`
101
102			`/* Invalidate IC */`
103			`l.addi r13,r0,0`
104			`l.addi r11,r0,8192`
105			`1:`
106			`l.mtspr r0,r13,SPR_ICBIR`
107			`l.sfne r13,r11`
108			`l.bf 1b`
109			`l.addi r13,r13,16`
110
111			`/* Enable IC */`
112			`l.mfspr r13,r0,SPR_SR`
113			`l.ori r13,r13,SPR_SR_ICE`
114			`l.mtspr r0,r13,SPR_SR`
115			`l.nop`
116			`l.nop`
117			`l.nop`
118			`l.nop`
119			`l.nop`
120
121			`l.jr r9`
122			`l.nop`
123
124	346	jeremybenn	`ic_disable:`
125	90	jeremybenn	`/* Disable IC */`
126			`l.mfspr r13,r0,SPR_SR`
127			`l.addi r11,r0,-1`
128			`l.xori r11,r11,SPR_SR_ICE`
129			`l.and r11,r13,r11`
130			`l.mtspr r0,r11,SPR_SR`
131
132			`l.jr r9`
133			`l.nop`
134
135	346	jeremybenn	`dc_enable:`
136	90	jeremybenn	`/* Disable DC */`
137			`l.mfspr r13,r0,SPR_SR`
138			`l.addi r11,r0,-1`
139			`l.xori r11,r11,SPR_SR_DCE`
140			`l.and r11,r13,r11`
141			`l.mtspr r0,r11,SPR_SR`
142
143			`/* Flush DC */`
144			`l.addi r13,r0,0`
145			`l.addi r11,r0,8192`
146			`1:`
147			`l.mtspr r0,r13,SPR_DCBIR`
148			`l.sfne r13,r11`
149			`l.bf 1b`
150			`l.addi r13,r13,16`
151
152			`/* Enable DC */`
153			`l.mfspr r13,r0,SPR_SR`
154			`l.ori r13,r13,SPR_SR_DCE`
155			`l.mtspr r0,r13,SPR_SR`
156
157			`l.jr r9`
158			`l.nop`
159
160	346	jeremybenn	`dc_disable:`
161	90	jeremybenn	`/* Disable DC */`
162			`l.mfspr r13,r0,SPR_SR`
163			`l.addi r11,r0,-1`
164			`l.xori r11,r11,SPR_SR_DCE`
165			`l.and r11,r13,r11`
166			`l.mtspr r0,r11,SPR_SR`
167
168			`l.jr r9`
169			`l.nop`
170
171			`/* dtlb_ic_test(unsigned long add, unsigned long set) */`
172	346	jeremybenn	`lo_dtlb_ci_test:`
173	90	jeremybenn	`l.addi r1,r1,-4`
174			`l.sw 0(r1),r9`
175
176			`l.addi r8,r0,0`
177
178			`l.movhi r5,hi(0x01234567)`
179			`l.ori r5,r5,lo(0x01234567)`
180			`l.sw 0(r3),r5`
181			`l.movhi r5,hi(0x89abcdef)`
182			`l.ori r5,r5,lo(0x89abcdef)`
183			`l.sw (PAGE_SIZE - 4)(r3),r5`
184
185			`l.ori r5,r3,SPR_DTLBMR_V`
186			`l.mtspr r4,r5,SPR_DTLBMR_BASE(0)`
187
188			`l.ori r5,r3,(DTLB_PR_NOLIMIT \| SPR_DTLBTR_CI)`
189			`l.mtspr r4,r5,SPR_DTLBTR_BASE(0)`
190
191			`l.addi r5,r3,PAGE_SIZE`
192			`l.ori r5,r5,SPR_DTLBMR_V`
193			`l.addi r6,r4,1`
194			`l.mtspr r6,r5,SPR_DTLBMR_BASE(0)`
195
196			`l.addi r5,r3,PAGE_SIZE`
197			`l.ori r5,r5,(DTLB_PR_NOLIMIT \| SPR_DTLBTR_CI)`
198			`l.addi r6,r4,1`
199			`l.mtspr r6,r5,SPR_DTLBTR_BASE(0)`
200
201	346	jeremybenn	`l.jal lo_dmmu_en`
202	90	jeremybenn	`l.nop`
203	346	jeremybenn	`l.jal dc_enable`
204	90	jeremybenn	`l.nop`
205
206			`l.movhi r6,hi(0x01234567)`
207			`l.ori r6,r6,lo(0x01234567)`
208			`l.lwz r5,0(r3)`
209			`l.sfeq r6,r5`
210			`l.bnf 11f`
211			`l.nop`
212			`l.movhi r6,hi(0x89abcdef)`
213			`l.ori r6,r6,lo(0x89abcdef)`
214			`l.lwz r5,(PAGE_SIZE - 4)(r3)`
215			`l.sfeq r6,r5`
216			`l.bnf 12f`
217			`l.nop`
218
219			`l.movhi r5,hi(0x76543210)`
220			`l.ori r5,r5,lo(0x76543210)`
221			`l.sw 0(r3),r5`
222			`l.movhi r5,hi(0xfedcba9)`
223			`l.ori r5,r5,lo(0xfedcba9)`
224			`l.sw (PAGE_SIZE - 4)(r3),r5`
225
226	346	jeremybenn	`l.jal lo_dmmu_dis`
227	90	jeremybenn	`l.nop`
228			`l.ori r5,r3,(DTLB_PR_NOLIMIT)`
229			`l.mtspr r4,r5,SPR_DTLBTR_BASE(0)`
230	346	jeremybenn	`l.jal lo_dmmu_en`
231	90	jeremybenn	`l.nop`
232
233			`l.movhi r6,hi(0x76543210)`
234			`l.ori r6,r6,lo(0x76543210)`
235			`l.lwz r5,0(r3)`
236			`l.sfeq r6,r5`
237			`l.bnf 13f`
238			`l.nop`
239			`l.movhi r6,hi(0xfedcba9)`
240			`l.ori r6,r6,lo(0xfedcba9)`
241			`l.lwz r5,(PAGE_SIZE - 4)(r3)`
242			`l.sfeq r6,r5`
243			`l.bnf 14f`
244			`l.nop`
245
246	346	jeremybenn	`l.jal lo_dmmu_dis`
247	90	jeremybenn	`l.nop`
248			`l.ori r5,r3,(DTLB_PR_NOLIMIT \| SPR_DTLBTR_CI)`
249			`l.mtspr r4,r5,SPR_DTLBTR_BASE(0)`
250	346	jeremybenn	`l.jal lo_dmmu_en`
251	90	jeremybenn	`l.nop`
252
253			`l.movhi r5,hi(0x00112233)`
254			`l.ori r5,r5,lo(0x00112233)`
255			`l.sw 0(r3),r5`
256			`#if 1`
257			`l.movhi r5,hi(0x44556677)`
258			`l.ori r5,r5,lo(0x44556677)`
259			`l.sw 4(r3),r5`
260			`l.movhi r5,hi(0x8899aabb)`
261			`l.ori r5,r5,lo(0x8899aabb)`
262			`l.sw 8(r3),r5`
263			`l.movhi r5,hi(0xccddeeff)`
264			`l.ori r5,r5,lo(0xccddeeff)`
265			`l.sw 12(r3),r5`
266			`#endif`
267			`l.movhi r5,hi(0x44556677)`
268			`l.ori r5,r5,lo(0x44556677)`
269			`l.sw (PAGE_SIZE - 4)(r3),r5`
270
271			`l.movhi r6,hi(0x00112233)`
272			`l.ori r6,r6,lo(0x00112233)`
273			`l.lwz r5,0(r3)`
274			`l.sfeq r6,r5`
275			`l.bnf 15f`
276			`l.nop`
277			`l.movhi r6,hi(0x44556677)`
278			`l.ori r6,r6,lo(0x44556677)`
279			`l.lwz r5,(PAGE_SIZE - 4)(r3)`
280			`l.sfeq r6,r5`
281			`l.bnf 16f`
282			`l.nop`
283
284	346	jeremybenn	`l.jal lo_dmmu_dis`
285	90	jeremybenn	`l.nop`
286			`l.ori r5,r3,(DTLB_PR_NOLIMIT)`
287			`l.mtspr r4,r5,SPR_DTLBTR_BASE(0)`
288	346	jeremybenn	`l.jal lo_dmmu_en`
289	90	jeremybenn	`l.nop`
290
291			`l.movhi r6,hi(0x76543210)`
292			`l.ori r6,r6,lo(0x76543210)`
293			`l.lwz r5,0(r3)`
294			`l.sfeq r6,r5`
295			`l.bnf 17f`
296			`l.nop`
297
298			`l.movhi r6,hi(0xfedcba9)`
299			`l.ori r6,r6,lo(0xfedcba9)`
300			`l.lwz r5,(PAGE_SIZE - 4)(r3)`
301			`l.sfeq r6,r5`
302			`l.bnf 18f`
303			`l.nop`
304
305			`/* Invalidate cache */`
306	346	jeremybenn	`l.jal dc_disable`
307	90	jeremybenn	`l.nop`
308
309			`l.movhi r5,hi(0x00112233)`
310			`l.ori r5,r5,lo(0x00112233)`
311			`l.sw 12(r3),r5`
312			`l.movhi r5,hi(0x44556677)`
313			`l.ori r5,r5,lo(0x44556677)`
314			`l.sw 8(r3),r5`
315			`l.movhi r5,hi(0x8899aabb)`
316			`l.ori r5,r5,lo(0x8899aabb)`
317			`l.sw 4(r3),r5`
318			`l.movhi r5,hi(0xccddeeff)`
319			`l.ori r5,r5,lo(0xccddeeff)`
320			`l.sw 0(r3),r5`
321			`l.movhi r5,hi(0x44556677)`
322			`l.ori r5,r5,lo(0x44556677)`
323			`l.sw (PAGE_SIZE - 4)(r3),r5`
324
325	346	jeremybenn	`l.jal dc_enable`
326	90	jeremybenn	`l.nop`
327
328			`/* I want this part to execute as fast as possible */`
329	346	jeremybenn	`l.jal ic_enable`
330	90	jeremybenn	`l.nop`
331
332			`l.addi r5,r3,PAGE_SIZE`
333
334			`/* This jump is just to be shure that the following`
335			`instructions will get into IC */`
336			`l.j 1f`
337			`l.nop`
338			`/* This shuld trigger cahe line refill */`
339			`2: l.lwz r6,0(r3)`
340			`l.j 2f`
341			`/* This load is from non cached area and may cause some problems`
342			`in previuos refill, which is probably still in progress */`
343			`l.lwz r6,0(r5)`
344			`1: l.j 2b`
345			`l.nop`
346			`2:`
347			`/* Check the line that was previosly refilled */`
348			`l.movhi r6,hi(0x00112233)`
349			`l.ori r6,r6,lo(0x00112233)`
350			`l.lwz r5,12(r3)`
351			`l.sfeq r6,r5`
352			`l.bnf 19f`
353			`l.nop`
354			`l.movhi r6,hi(0x44556677)`
355			`l.ori r6,r6,lo(0x44556677)`
356			`l.lwz r5,8(r3)`
357			`l.sfeq r6,r5`
358			`l.bnf 19f`
359			`l.nop`
360			`l.movhi r6,hi(0x8899aabb)`
361			`l.ori r6,r6,lo(0x8899aabb)`
362			`l.lwz r5,4(r3)`
363			`l.sfeq r6,r5`
364			`l.bnf 19f`
365			`l.nop`
366			`l.movhi r6,hi(0xccddeeff)`
367			`l.ori r6,r6,lo(0xccddeeff)`
368			`l.lwz r5,0(r3)`
369			`l.sfeq r6,r5`
370			`l.bnf 19f`
371			`l.nop`
372
373	346	jeremybenn	`l.jal dc_disable`
374	90	jeremybenn	`l.nop`
375
376	346	jeremybenn	`l.jal lo_dmmu_dis`
377	90	jeremybenn	`l.nop`
378
379			`l.j 10f`
380			`l.nop`
381
382			`19: l.addi r8,r8,1`
383			`18: l.addi r8,r8,1`
384			`17: l.addi r8,r8,1`
385			`16: l.addi r8,r8,1`
386			`15: l.addi r8,r8,1`
387			`14: l.addi r8,r8,1`
388			`13: l.addi r8,r8,1`
389			`12: l.addi r8,r8,1`
390			`11: l.addi r8,r8,1`
391
392	346	jeremybenn	`10: l.jal dc_disable`
393	90	jeremybenn	`l.nop`
394
395	346	jeremybenn	`l.jal ic_disable`
396	90	jeremybenn	`l.nop`
397
398	346	jeremybenn	`l.jal lo_dmmu_dis`
399	90	jeremybenn	`l.nop`
400
401			`l.addi r11,r8,0`
402			`l.sw 0(r0),r8`
403			`l.sw 4(r0),r5`
404
405			`l.lwz r9,0(r1)`
406			`l.jr r9`
407			`l.addi r1,r1,4`
408
409			`/* itlb_ic_test(unsigned long add, unsigned long set) */`
410	346	jeremybenn	`lo_itlb_ci_test:`
411	90	jeremybenn	`l.addi r1,r1,-4`
412			`l.sw 0(r1),r9`
413
414			`l.addi r8,r0,0`
415
416			`/* Copy the code to the prepeared location */`
417			`l.addi r7,r0,88`
418	346	jeremybenn	`l.movhi r5,hi(ci_test)`
419			`l.ori r5,r5,lo(ci_test)`
420	90	jeremybenn	`l.addi r6,r3,0`
421			`1: l.lwz r11,0(r5)`
422			`l.sw 0(r6),r11`
423			`l.addi r5,r5,4`
424			`l.addi r6,r6,4`
425			`l.addi r7,r7,-4`
426			`l.sfeqi r7,0`
427			`l.bnf 1b`
428			`l.nop`
429
430			`l.ori r5,r3,SPR_ITLBMR_V`
431			`l.mtspr r4,r5,SPR_ITLBMR_BASE(0)`
432
433			`l.ori r5,r3,ITLB_PR_NOLIMIT`
434			`l.mtspr r4,r5,SPR_ITLBTR_BASE(0)`
435
436	346	jeremybenn	`l.jal lo_immu_en`
437	90	jeremybenn	`l.nop`
438	346	jeremybenn	`l.jal ic_enable`
439	90	jeremybenn	`l.nop`
440
441			`l.addi r5,r0,0`
442			`l.addi r6,r0,0`
443			`l.jalr r3`
444			`l.nop`
445
446			`l.sfeqi r5,5`
447			`l.bnf 11f`
448			`l.nop`
449
450			`/* Copy the code to the prepeared location */`
451			`l.addi r7,r0,20`
452	346	jeremybenn	`l.movhi r5,hi(ic_refill_test)`
453			`l.ori r5,r5,lo(ic_refill_test)`
454	90	jeremybenn	`l.addi r6,r3,12`
455			`1: l.lwz r11,0(r5)`
456			`l.sw 0(r6),r11`
457			`l.addi r5,r5,4`
458			`l.addi r6,r6,4`
459			`l.addi r7,r7,-4`
460			`l.sfeqi r7,0`
461			`l.bnf 1b`
462			`l.nop`
463
464	346	jeremybenn	`l.jal ic_disable`
465	90	jeremybenn	`l.nop`
466	346	jeremybenn	`l.jal ic_enable`
467	90	jeremybenn	`l.nop`
468
469			`l.addi r5,r0,0`
470			`l.addi r6,r3,12`
471			`l.jalr r6`
472			`l.nop`
473			`l.addi r6,r3,16`
474			`l.jalr r6`
475			`l.nop`
476
477			`l.sfeqi r5,4`
478			`l.bnf 12f`
479			`l.nop`
480
481			`l.j 10f`
482			`l.nop`
483
484			`12: l.addi r8,r8,1`
485			`11: l.addi r8,r8,1`
486
487	346	jeremybenn	`10: l.jal ic_disable`
488	90	jeremybenn	`l.nop`
489
490	346	jeremybenn	`l.jal lo_dmmu_dis`
491	90	jeremybenn	`l.nop`
492
493			`l.addi r11,r8,0`
494			`l.sw 0(r0),r11`
495			`l.sw 4(r0),r5`
496
497			`l.lwz r9,0(r1)`
498			`l.jr r9`
499			`l.addi r1,r1,4`
500

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [mmu/] [mmu-asm.S] - Blame information for rev 346