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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [mmu/] [mmu-asm.S] - Blame information for rev 178

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Line No. Rev Author Line
1 90 jeremybenn
/* mmu-asm.S. Machine code to support Or1ksim MMU test
2
 
3
   Copyright (C) 1999-2006 OpenCores
4
   Copyright (C) 2010 Embecosm Limited
5
 
6
   Contributors various OpenCores participants
7
   Contributor Jeremy Bennett 
8
 
9
   This file is part of OpenRISC 1000 Architectural Simulator.
10
 
11
   This program is free software; you can redistribute it and/or modify it
12
   under the terms of the GNU General Public License as published by the Free
13
   Software Foundation; either version 3 of the License, or (at your option)
14
   any later version.
15
 
16
   This program is distributed in the hope that it will be useful, but WITHOUT
17
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
   more details.
20
 
21
   You should have received a copy of the GNU General Public License along
22
   with this program.  If not, see .  */
23
 
24
/* ----------------------------------------------------------------------------
25
   This code is commented throughout for use with Doxygen.
26
   --------------------------------------------------------------------------*/
27
#include "spr-defs.h"
28
 
29
#define PAGE_SIZE 8192
30
#define DTLB_PR_NOLIMIT  (SPR_DTLBTR_URE  | \
31
                          SPR_DTLBTR_UWE  | \
32
                          SPR_DTLBTR_SRE  | \
33
                          SPR_DTLBTR_SWE  )
34
#define ITLB_PR_NOLIMIT  (SPR_ITLBTR_SXE  | \
35
                          SPR_ITLBTR_UXE  )
36
        .global _lo_dmmu_en
37
        .global _lo_immu_en
38
        .global _lo_dtlb_ci_test
39
        .global _lo_itlb_ci_test
40
        .global _testjump
41
        .global _ic_enable
42
        .global _ic_disable
43
        .global _dc_enable
44
        .global _dc_disable
45
 
46
_lo_dmmu_en:
47
                                l.mfspr r11,r0,SPR_SR
48
        l.ori   r11,r11,SPR_SR_DME
49
        l.mtspr r0,r11,SPR_ESR_BASE
50
        l.mtspr r0,r9,SPR_EPCR_BASE
51
        l.rfe
52
        l.nop
53
 
54
_lo_dmmu_dis:
55
        l.addi  r13,r0,-1
56
        l.xori  r13,r13,SPR_SR_DME
57
        l.mfspr r11,r0,SPR_SR
58
        l.and   r11,r11,r13
59
        l.mtspr r0,r11,SPR_SR
60
        l.jr    r9
61
        l.nop
62
 
63
_lo_immu_en:
64
                                l.mfspr r11,r0,SPR_SR
65
        l.ori   r11,r11,SPR_SR_IME
66
        l.mtspr r0,r11,SPR_ESR_BASE
67
        l.mtspr r0,r9,SPR_EPCR_BASE
68
        l.rfe
69
        l.nop
70
 
71
_lo_immu_dis:
72
        l.addi  r13,r0,-1
73
        l.xori  r13,r13,SPR_SR_IME
74
        l.mfspr r11,r0,SPR_SR
75
        l.and   r11,r11,r13
76
        l.mtspr r0,r11,SPR_SR
77
        l.jr    r9
78
        l.nop
79
 
80
_testjump:
81
        l.movhi r5,0x4800
82
        l.ori   r5,r5,0x4800
83
        l.sw    0x0(r3),r5
84
        l.movhi r5,0x1500
85
        l.ori   r5,r5,0x0000
86
        l.sw    0x4(r3),r5
87
        l.or    r5,r0,r9
88
        l.jalr  r4
89
        l.nop
90
        l.or    r9,r0,r5
91
        l.jr    r9
92
        l.nop
93
 
94
_ic_enable:
95
        /* Disable IC */
96
        l.mfspr r13,r0,SPR_SR
97
        l.addi  r11,r0,-1
98
        l.xori  r11,r11,SPR_SR_ICE
99
        l.and   r11,r13,r11
100
        l.mtspr r0,r11,SPR_SR
101
 
102
        /* Invalidate IC */
103
        l.addi  r13,r0,0
104
        l.addi  r11,r0,8192
105
1:
106
        l.mtspr r0,r13,SPR_ICBIR
107
        l.sfne  r13,r11
108
        l.bf    1b
109
        l.addi  r13,r13,16
110
 
111
        /* Enable IC */
112
        l.mfspr r13,r0,SPR_SR
113
        l.ori   r13,r13,SPR_SR_ICE
114
        l.mtspr r0,r13,SPR_SR
115
        l.nop
116
        l.nop
117
        l.nop
118
        l.nop
119
        l.nop
120
 
121
        l.jr    r9
122
        l.nop
123
 
124
_ic_disable:
125
        /* Disable IC */
126
        l.mfspr r13,r0,SPR_SR
127
        l.addi  r11,r0,-1
128
        l.xori  r11,r11,SPR_SR_ICE
129
        l.and   r11,r13,r11
130
        l.mtspr r0,r11,SPR_SR
131
 
132
        l.jr    r9
133
        l.nop
134
 
135
_dc_enable:
136
        /* Disable DC */
137
        l.mfspr r13,r0,SPR_SR
138
        l.addi  r11,r0,-1
139
        l.xori  r11,r11,SPR_SR_DCE
140
        l.and   r11,r13,r11
141
        l.mtspr r0,r11,SPR_SR
142
 
143
        /* Flush DC */
144
        l.addi  r13,r0,0
145
        l.addi  r11,r0,8192
146
1:
147
        l.mtspr r0,r13,SPR_DCBIR
148
        l.sfne  r13,r11
149
        l.bf    1b
150
        l.addi  r13,r13,16
151
 
152
        /* Enable DC */
153
        l.mfspr r13,r0,SPR_SR
154
        l.ori   r13,r13,SPR_SR_DCE
155
        l.mtspr r0,r13,SPR_SR
156
 
157
        l.jr    r9
158
        l.nop
159
 
160
_dc_disable:
161
        /* Disable DC */
162
        l.mfspr r13,r0,SPR_SR
163
        l.addi  r11,r0,-1
164
        l.xori  r11,r11,SPR_SR_DCE
165
        l.and   r11,r13,r11
166
        l.mtspr r0,r11,SPR_SR
167
 
168
        l.jr    r9
169
        l.nop
170
 
171
        /* dtlb_ic_test(unsigned long add, unsigned long set) */
172
_lo_dtlb_ci_test:
173
        l.addi  r1,r1,-4
174
        l.sw    0(r1),r9
175
 
176
        l.addi  r8,r0,0
177
 
178
        l.movhi r5,hi(0x01234567)
179
        l.ori   r5,r5,lo(0x01234567)
180
        l.sw    0(r3),r5
181
        l.movhi r5,hi(0x89abcdef)
182
        l.ori   r5,r5,lo(0x89abcdef)
183
        l.sw    (PAGE_SIZE - 4)(r3),r5
184
 
185
        l.ori   r5,r3,SPR_DTLBMR_V
186
        l.mtspr r4,r5,SPR_DTLBMR_BASE(0)
187
 
188
        l.ori   r5,r3,(DTLB_PR_NOLIMIT  | SPR_DTLBTR_CI)
189
        l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
190
 
191
        l.addi  r5,r3,PAGE_SIZE
192
        l.ori   r5,r5,SPR_DTLBMR_V
193
        l.addi  r6,r4,1
194
        l.mtspr r6,r5,SPR_DTLBMR_BASE(0)
195
 
196
        l.addi  r5,r3,PAGE_SIZE
197
        l.ori   r5,r5,(DTLB_PR_NOLIMIT  | SPR_DTLBTR_CI)
198
        l.addi  r6,r4,1
199
        l.mtspr r6,r5,SPR_DTLBTR_BASE(0)
200
 
201
        l.jal   _lo_dmmu_en
202
        l.nop
203
        l.jal   _dc_enable
204
        l.nop
205
 
206
        l.movhi r6,hi(0x01234567)
207
        l.ori   r6,r6,lo(0x01234567)
208
        l.lwz   r5,0(r3)
209
        l.sfeq  r6,r5
210
        l.bnf   11f
211
        l.nop
212
        l.movhi r6,hi(0x89abcdef)
213
        l.ori   r6,r6,lo(0x89abcdef)
214
        l.lwz   r5,(PAGE_SIZE - 4)(r3)
215
        l.sfeq  r6,r5
216
        l.bnf   12f
217
        l.nop
218
 
219
        l.movhi r5,hi(0x76543210)
220
        l.ori   r5,r5,lo(0x76543210)
221
        l.sw    0(r3),r5
222
        l.movhi r5,hi(0xfedcba9)
223
        l.ori   r5,r5,lo(0xfedcba9)
224
        l.sw    (PAGE_SIZE - 4)(r3),r5
225
 
226
        l.jal   _lo_dmmu_dis
227
        l.nop
228
        l.ori   r5,r3,(DTLB_PR_NOLIMIT)
229
        l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
230
        l.jal   _lo_dmmu_en
231
        l.nop
232
 
233
        l.movhi r6,hi(0x76543210)
234
        l.ori   r6,r6,lo(0x76543210)
235
        l.lwz   r5,0(r3)
236
        l.sfeq  r6,r5
237
        l.bnf   13f
238
        l.nop
239
        l.movhi r6,hi(0xfedcba9)
240
        l.ori   r6,r6,lo(0xfedcba9)
241
        l.lwz   r5,(PAGE_SIZE - 4)(r3)
242
        l.sfeq  r6,r5
243
        l.bnf   14f
244
        l.nop
245
 
246
        l.jal   _lo_dmmu_dis
247
        l.nop
248
        l.ori   r5,r3,(DTLB_PR_NOLIMIT | SPR_DTLBTR_CI)
249
        l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
250
        l.jal   _lo_dmmu_en
251
        l.nop
252
 
253
        l.movhi r5,hi(0x00112233)
254
        l.ori   r5,r5,lo(0x00112233)
255
        l.sw    0(r3),r5
256
#if 1
257
        l.movhi r5,hi(0x44556677)
258
        l.ori   r5,r5,lo(0x44556677)
259
        l.sw    4(r3),r5
260
        l.movhi r5,hi(0x8899aabb)
261
        l.ori   r5,r5,lo(0x8899aabb)
262
        l.sw    8(r3),r5
263
        l.movhi r5,hi(0xccddeeff)
264
        l.ori   r5,r5,lo(0xccddeeff)
265
        l.sw    12(r3),r5
266
#endif
267
        l.movhi r5,hi(0x44556677)
268
        l.ori   r5,r5,lo(0x44556677)
269
        l.sw    (PAGE_SIZE - 4)(r3),r5
270
 
271
        l.movhi r6,hi(0x00112233)
272
        l.ori   r6,r6,lo(0x00112233)
273
        l.lwz   r5,0(r3)
274
        l.sfeq  r6,r5
275
        l.bnf   15f
276
        l.nop
277
        l.movhi r6,hi(0x44556677)
278
        l.ori   r6,r6,lo(0x44556677)
279
        l.lwz   r5,(PAGE_SIZE - 4)(r3)
280
        l.sfeq  r6,r5
281
        l.bnf   16f
282
        l.nop
283
 
284
        l.jal   _lo_dmmu_dis
285
        l.nop
286
        l.ori   r5,r3,(DTLB_PR_NOLIMIT)
287
        l.mtspr r4,r5,SPR_DTLBTR_BASE(0)
288
        l.jal   _lo_dmmu_en
289
        l.nop
290
 
291
        l.movhi r6,hi(0x76543210)
292
        l.ori   r6,r6,lo(0x76543210)
293
        l.lwz   r5,0(r3)
294
        l.sfeq  r6,r5
295
        l.bnf   17f
296
        l.nop
297
 
298
        l.movhi r6,hi(0xfedcba9)
299
        l.ori   r6,r6,lo(0xfedcba9)
300
        l.lwz   r5,(PAGE_SIZE - 4)(r3)
301
        l.sfeq  r6,r5
302
        l.bnf   18f
303
        l.nop
304
 
305
        /* Invalidate cache */
306
        l.jal   _dc_disable
307
        l.nop
308
 
309
        l.movhi r5,hi(0x00112233)
310
        l.ori   r5,r5,lo(0x00112233)
311
        l.sw    12(r3),r5
312
        l.movhi r5,hi(0x44556677)
313
        l.ori   r5,r5,lo(0x44556677)
314
        l.sw    8(r3),r5
315
        l.movhi r5,hi(0x8899aabb)
316
        l.ori   r5,r5,lo(0x8899aabb)
317
        l.sw    4(r3),r5
318
        l.movhi r5,hi(0xccddeeff)
319
        l.ori   r5,r5,lo(0xccddeeff)
320
        l.sw    0(r3),r5
321
        l.movhi r5,hi(0x44556677)
322
        l.ori   r5,r5,lo(0x44556677)
323
        l.sw    (PAGE_SIZE - 4)(r3),r5
324
 
325
        l.jal   _dc_enable
326
        l.nop
327
 
328
        /* I want this part to execute as fast as possible */
329
        l.jal   _ic_enable
330
        l.nop
331
 
332
        l.addi  r5,r3,PAGE_SIZE
333
 
334
        /* This jump is just to be shure that the following
335
           instructions will get into IC */
336
        l.j     1f
337
        l.nop
338
        /* This shuld trigger cahe line refill */
339
2:      l.lwz   r6,0(r3)
340
        l.j     2f
341
        /* This load is from non cached area and may cause some problems
342
           in previuos refill, which is probably still in progress */
343
        l.lwz   r6,0(r5)
344
1:      l.j     2b
345
        l.nop
346
2:
347
        /* Check the line that was previosly refilled */
348
        l.movhi r6,hi(0x00112233)
349
        l.ori   r6,r6,lo(0x00112233)
350
        l.lwz   r5,12(r3)
351
        l.sfeq  r6,r5
352
        l.bnf   19f
353
        l.nop
354
        l.movhi r6,hi(0x44556677)
355
        l.ori   r6,r6,lo(0x44556677)
356
        l.lwz   r5,8(r3)
357
        l.sfeq  r6,r5
358
        l.bnf   19f
359
        l.nop
360
        l.movhi r6,hi(0x8899aabb)
361
        l.ori   r6,r6,lo(0x8899aabb)
362
        l.lwz   r5,4(r3)
363
        l.sfeq  r6,r5
364
        l.bnf   19f
365
        l.nop
366
        l.movhi r6,hi(0xccddeeff)
367
        l.ori   r6,r6,lo(0xccddeeff)
368
        l.lwz   r5,0(r3)
369
        l.sfeq  r6,r5
370
        l.bnf   19f
371
        l.nop
372
 
373
        l.jal   _dc_disable
374
        l.nop
375
 
376
        l.jal   _lo_dmmu_dis
377
        l.nop
378
 
379
        l.j     10f
380
        l.nop
381
 
382
19:     l.addi  r8,r8,1
383
18:     l.addi  r8,r8,1
384
17:     l.addi  r8,r8,1
385
16:     l.addi  r8,r8,1
386
15:     l.addi  r8,r8,1
387
14:     l.addi  r8,r8,1
388
13:     l.addi  r8,r8,1
389
12:     l.addi  r8,r8,1
390
11:     l.addi  r8,r8,1
391
 
392
10:     l.jal   _dc_disable
393
        l.nop
394
 
395
        l.jal   _ic_disable
396
        l.nop
397
 
398
        l.jal   _lo_dmmu_dis
399
        l.nop
400
 
401
        l.addi  r11,r8,0
402
        l.sw    0(r0),r8
403
        l.sw    4(r0),r5
404
 
405
        l.lwz   r9,0(r1)
406
        l.jr    r9
407
        l.addi  r1,r1,4
408
 
409
        /* itlb_ic_test(unsigned long add, unsigned long set) */
410
_lo_itlb_ci_test:
411
        l.addi  r1,r1,-4
412
        l.sw    0(r1),r9
413
 
414
        l.addi  r8,r0,0
415
 
416
        /* Copy the code to the prepeared location */
417
        l.addi  r7,r0,88
418
        l.movhi r5,hi(_ci_test)
419
        l.ori   r5,r5,lo(_ci_test)
420
        l.addi  r6,r3,0
421
1:      l.lwz   r11,0(r5)
422
        l.sw    0(r6),r11
423
        l.addi  r5,r5,4
424
        l.addi  r6,r6,4
425
        l.addi  r7,r7,-4
426
        l.sfeqi r7,0
427
        l.bnf   1b
428
        l.nop
429
 
430
        l.ori   r5,r3,SPR_ITLBMR_V
431
        l.mtspr r4,r5,SPR_ITLBMR_BASE(0)
432
 
433
        l.ori   r5,r3,ITLB_PR_NOLIMIT
434
        l.mtspr r4,r5,SPR_ITLBTR_BASE(0)
435
 
436
        l.jal   _lo_immu_en
437
        l.nop
438
        l.jal   _ic_enable
439
        l.nop
440
 
441
        l.addi  r5,r0,0
442
        l.addi  r6,r0,0
443
        l.jalr  r3
444
        l.nop
445
 
446
        l.sfeqi r5,5
447
        l.bnf   11f
448
        l.nop
449
 
450
        /* Copy the code to the prepeared location */
451
        l.addi  r7,r0,20
452
        l.movhi r5,hi(_ic_refill_test)
453
        l.ori   r5,r5,lo(_ic_refill_test)
454
        l.addi  r6,r3,12
455
1:      l.lwz   r11,0(r5)
456
        l.sw    0(r6),r11
457
        l.addi  r5,r5,4
458
        l.addi  r6,r6,4
459
        l.addi  r7,r7,-4
460
        l.sfeqi r7,0
461
        l.bnf   1b
462
        l.nop
463
 
464
        l.jal   _ic_disable
465
        l.nop
466
        l.jal   _ic_enable
467
        l.nop
468
 
469
        l.addi  r5,r0,0
470
        l.addi  r6,r3,12
471
        l.jalr  r6
472
        l.nop
473
        l.addi  r6,r3,16
474
        l.jalr  r6
475
        l.nop
476
 
477
        l.sfeqi r5,4
478
        l.bnf   12f
479
        l.nop
480
 
481
        l.j     10f
482
        l.nop
483
 
484
12:     l.addi  r8,r8,1
485
11:     l.addi  r8,r8,1
486
 
487
10:     l.jal   _ic_disable
488
        l.nop
489
 
490
        l.jal   _lo_dmmu_dis
491
        l.nop
492
 
493
        l.addi  r11,r8,0
494
        l.sw    0(r0),r11
495
        l.sw    4(r0),r5
496
 
497
        l.lwz   r9,0(r1)
498
        l.jr    r9
499
        l.addi  r1,r1,4
500
 
501
_ci_test:
502
3:      l.addi  r5,r5,1
503
 
504
        l.sfeqi r6,0x01
505
        l.bnf   1f
506
        l.nop
507
 
508
        l.addi  r13,r0,-1
509
        l.xori  r13,r13,SPR_SR_IME
510
        l.mfspr r11,r0,SPR_SR
511
        l.and   r13,r11,r13
512
        l.mtspr r0,r13,SPR_SR
513
 
514
        l.ori   r7,r3,(ITLB_PR_NOLIMIT  | SPR_ITLBTR_CI)
515
        l.mtspr r4,r7,SPR_ITLBTR_BASE(0)
516
 
517
        l.mtspr r0,r11,SPR_SR
518
 
519
1:      l.lwz   r7,0(r3)
520
        l.addi  r7,r7,1
521
        l.sw    0(r3),r7
522
 
523
2:      l.addi  r6,r6,1
524
        l.sfeqi r6,3
525
        l.bnf   3b
526
        l.nop
527
 
528
        l.jr    r9
529
        l.nop
530
 
531
 
532
_ic_refill_test:
533
        l.jr    r9
534
        l.addi  r5,r5,1
535
        l.addi  r5,r5,1
536
        l.jr    r9
537
        l.addi  r5,r5,1

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