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/* mmu.c. Test of the Or1ksim MMU

   Copyright (C) 1999-2006 OpenCores

   Copyright (C) 2010 Embecosm Limited

   Contributors various OpenCores participants

   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>

   This file is part of OpenRISC 1000 Architectural Simulator.

   This program is free software; you can redistribute it and/or modify it

   under the terms of the GNU General Public License as published by the Free

   Software Foundation; either version 3 of the License, or (at your option)

   any later version.

   This program is distributed in the hope that it will be useful, but WITHOUT

   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

   more details.

   You should have received a copy of the GNU General Public License along

   with this program.  If not, see <http:  www.gnu.org/licenses/>.  */

/* ----------------------------------------------------------------------------

   This code is commented throughout for use with Doxygen.

   --------------------------------------------------------------------------*/

/* This is MMU test for OpenRISC 1200 */

#include "spr-defs.h"

#include "support.h"

/* For shorter simulation run */

#define RTL_SIM 1

/* Define RAM physical location and size

   Bottom half will be used for this program, the rest

   will be used for testing */

#define FLASH_START 0xf0000000

#define FLASH_SIZE  0x00200000

#define RAM_START   0x00000000

#define RAM_SIZE    0x00200000

/* What is the last address in ram that is used by this program */

#define TEXT_END_ADD (FLASH_START + (FLASH_SIZE / 2))

#define DATA_END_ADD (RAM_START + (RAM_SIZE / 2))

#define TLB_TEXT_SET_NB 8

#define TLB_DATA_SET_NB 4

/* MMU page size */

#define PAGE_SIZE 8192

/* Number of DTLB sets used (power of 2, max is 256) */

#define DTLB_SETS 64

/* Number of DTLB ways (1, 2, 3 etc., max is 4). */

#define DTLB_WAYS 1

/* Number of ITLB sets used (power of 2, max is 256) */

#define ITLB_SETS 64

/* Number of ITLB ways (1, 2, 3 etc., max is 4). */

#define ITLB_WAYS 1

/* TLB mode codes */

#define TLB_CODE_ONE_TO_ONE     0x00000000

#define TLB_CODE_PLUS_ONE_PAGE  0x10000000

#define TLB_CODE_MINUS_ONE_PAGE 0x20000000

#define TLB_CODE_MASK   0xfffff000

#define TLB_PR_MASK     0x00000fff

#define DTLB_PR_NOLIMIT  (SPR_DTLBTR_URE  | \

                          SPR_DTLBTR_UWE  | \

                          SPR_DTLBTR_SRE  | \

                          SPR_DTLBTR_SWE  )

#define ITLB_PR_NOLIMIT  (SPR_ITLBTR_SXE  | \

                          SPR_ITLBTR_UXE  )

#if 1

#define debug printf

#else

#define debug

#endif

/* fails if x is false */

#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))

//#define TEST_JUMP(x) testjump( ((x) & (RAM_SIZE/2 - 1)) + DATA_END_ADD, (x))

#define TEST_JUMP(x) copy_jump (((x) & (RAM_SIZE/2 - 1)) + DATA_END_ADD); call (x)

/* Extern functions */

extern void lo_dmmu_en (void);

extern void lo_immu_en (void);

extern int  lo_dtlb_ci_test (unsigned long, unsigned long);

extern int  lo_itlb_ci_test(unsigned long, unsigned long);

extern void testjump(unsigned long phy_addr, unsigned long virt_addr);

extern void (*jr)(void);

/* Local functions prototypes */

void dmmu_disable (void);

void immu_disable (void);

/* Global variables */

extern unsigned long ram_end;

/* DTLB mode status */

volatile unsigned long dtlb_val;

/* ITLB mode status */

volatile unsigned long itlb_val;

/* DTLB miss counter */

volatile int dtlb_miss_count;

/* Data page fault counter */

volatile int dpage_fault_count;

/* ITLB miss counter */

volatile int itlb_miss_count;

/* Instruction page fault counter */

volatile int ipage_fault_count;

/* EA of last DTLB miss exception */

unsigned long dtlb_miss_ea;

/* EA of last data page fault exception */

unsigned long dpage_fault_ea;

/* EA of last ITLB miss exception */

unsigned long itlb_miss_ea;

/* EA of last insn page fault exception */

unsigned long ipage_fault_ea;

void sys_call (void)

{

  asm("l.sys\t0");

}

void fail (char *func, int line)

{

#ifndef __FUNCTION__

#define __FUNCTION__ "?"

#endif

  /* Trigger sys call exception to enable supervisor mode again */

  sys_call ();

  immu_disable ();

  dmmu_disable ();

  debug("Test failed in %s:%i\n", func, line);

  report (0xeeeeeeee);

  exit (1);

}

void call(unsigned long add)

{

        asm("l.jalr\t\t%0" : : "r" (add) : "r9", "r11");

        asm("l.nop" : :);

}

void jump(void)

{

        asm("jr:");

        asm("l.jr\t\tr9") ;

        asm("l.nop" : :);

}

void copy_jump(unsigned long phy_add)

{

        memcpy((void *)phy_add, (void *)&jr, 8);

}

/* Bus error exception handler */

void bus_err_handler (void)

{

  /* This shouldn't happend */

  debug("Test failed: Bus error\n");

  report (0xeeeeeeee);

  exit (1);

}

/* Illegal insn exception handler */

void ill_insn_handler (void)

{

  /* This shouldn't happend */

  debug("Test failed: Illegal insn\n");

  report (0xeeeeeeee);

  exit (1);

}

/* Sys call exception handler */

void sys_call_handler (void)

{

  /* Set supervisor mode */

  mtspr (SPR_ESR_BASE, mfspr (SPR_ESR_BASE) | SPR_SR_SM);

}

/* DTLB miss exception handler */

void dtlb_miss_handler (void)

{

  unsigned long ea, ta, tlbtr;

  int set, way = 0;

  int i;

  /* Get EA that cause the exception */

  ea = mfspr (SPR_EEAR_BASE);

  /* Find TLB set and LRU way */

  set = (ea / PAGE_SIZE) % DTLB_SETS;

  for (i = 0; i < DTLB_WAYS; i++) {

    if ((mfspr (SPR_DTLBMR_BASE(i) + set) & SPR_DTLBMR_LRU) == 0) {

      way = i;

      break;

    }

  }

  debug("ea = %08lx set = %d way = %d\n", ea, set, way);

  if (((RAM_START <= ea) && (ea < DATA_END_ADD) ) || ((FLASH_START <= ea) && (ea < TEXT_END_ADD))) {

    /* If this is acces to data of this program set one to one translation */

    mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);

    mtspr (SPR_DTLBTR_BASE(way) + set, (ea & SPR_DTLBTR_PPN) | DTLB_PR_NOLIMIT);

    return;

  }

  /* Update DTLB miss counter and EA */

  dtlb_miss_count++;

  dtlb_miss_ea = ea;

  /* Whatever access is in progress, translated address have to point to physical RAM */

  ta = (ea & ((RAM_SIZE/2) - 1)) + RAM_START + (RAM_SIZE/2);

  tlbtr = (ta & SPR_DTLBTR_PPN) | (dtlb_val & TLB_PR_MASK);

  debug("tlbtr = %08lx dtlb_val = %08lx\n", tlbtr, dtlb_val);

  /* Set DTLB entry */

  mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);

  mtspr (SPR_DTLBTR_BASE(way) + set, tlbtr);

}

/* Data page fault exception handler */

void dpage_fault_handler (void)

{

  unsigned long ea;

  int set, way = 0;

  int i;

  /* Get EA that cause the exception */

  ea = mfspr (SPR_EEAR_BASE);

  /* Find TLB set and way */

  set = (ea / PAGE_SIZE) % DTLB_SETS;

  for (i = 0; i < DTLB_WAYS; i++) {

    if ((mfspr (SPR_DTLBMR_BASE(i) + set) & SPR_DTLBMR_VPN) == (ea & SPR_DTLBMR_VPN)) {

      way = i;

      break;

    }

  }

  debug("ea = %08lx set = %d way = %d\n", ea, set, way);

  if (((RAM_START <= ea) && (ea < DATA_END_ADD) ) || ((FLASH_START <= ea) && (ea < TEXT_END_ADD))) {

    /* If this is acces to data of this program set one to one translation */

    mtspr (SPR_DTLBTR_BASE(way) + set, (ea & SPR_DTLBTR_PPN) | DTLB_PR_NOLIMIT);

    return;

  }

  /* Update data page fault counter and EA */

  dpage_fault_count++;

  dpage_fault_ea = ea;

  /* Give permission */

  mtspr (SPR_DTLBTR_BASE(way) + set, (mfspr (SPR_DTLBTR_BASE(way) + set) & ~DTLB_PR_NOLIMIT) | dtlb_val);

}

/* ITLB miss exception handler */

void itlb_miss_handler (void)

{

  unsigned long ea, ta, tlbtr;

  int set, way = 0;

  int i;

  /* Get EA that cause the exception */

  ea = mfspr (SPR_EEAR_BASE);

  /* Find TLB set and LRU way */

  set = (ea / PAGE_SIZE) % ITLB_SETS;

  for (i = 0; i < ITLB_WAYS; i++) {

    if ((mfspr (SPR_ITLBMR_BASE(i) + set) & SPR_ITLBMR_LRU) == 0) {

      way = i;

      break;

    }

  }

  debug("ea = %08lx set = %d way = %d\n", ea, set, way);

  if ((FLASH_START <= ea) && (ea < TEXT_END_ADD)) {

    /* If this is acces to data of this program set one to one translation */

    mtspr (SPR_ITLBMR_BASE(way) + set, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V);

    mtspr (SPR_ITLBTR_BASE(way) + set, (ea & SPR_ITLBTR_PPN) | ITLB_PR_NOLIMIT);

    return;

  }

  /* Update ITLB miss counter and EA */

  itlb_miss_count++;

  itlb_miss_ea = ea;

  /* Whatever access is in progress, translated address have to point to physical RAM */

  ta = (ea & ((RAM_SIZE/2) - 1)) + DATA_END_ADD;

  tlbtr = (ta & SPR_ITLBTR_PPN) | (itlb_val & TLB_PR_MASK);

  debug("ta = %08lx\n", ta);

  /* Set ITLB entry */

  mtspr (SPR_ITLBMR_BASE(way) + set, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V);

  mtspr (SPR_ITLBTR_BASE(way) + set, tlbtr);

}

/* Intstruction page fault exception handler */

void ipage_fault_handler (void)

{

  unsigned long ea;

  int set, way = 0;

  int i;

  /* Get EA that cause the exception */

  ea = mfspr (SPR_EEAR_BASE);

  /* Find TLB set and way */

  set = (ea / PAGE_SIZE) % ITLB_SETS;

  for (i = 0; i < ITLB_WAYS; i++) {

    if ((mfspr (SPR_ITLBMR_BASE(i) + set) & SPR_ITLBMR_VPN) == (ea & SPR_ITLBMR_VPN)) {

      way = i;

      break;

    }

  }

  debug("ea = %08lx set = %d way = %d\n", ea, set, way);

  if ((FLASH_START <= ea) && (ea < TEXT_END_ADD)) {

    /* If this is acces to data of this program set one to one translation */

    mtspr (SPR_DTLBTR_BASE(way) + set, (ea & SPR_DTLBTR_PPN) | ITLB_PR_NOLIMIT);

    return;

  }

  /* Update instruction page fault counter and EA */

  ipage_fault_count++;

  ipage_fault_ea = ea;

  /* Give permission */

  mtspr (SPR_ITLBTR_BASE(way) + set, (mfspr (SPR_ITLBTR_BASE(way) + set) & ~ITLB_PR_NOLIMIT) | itlb_val);

}

/* Invalidate all entries in DTLB and enable DMMU */

void dmmu_enable (void)

{

  /* Register DTLB miss handler */

  excpt_dtlbmiss = (unsigned long)dtlb_miss_handler;

  /* Register data page fault handler */

  excpt_dpfault = (unsigned long)dpage_fault_handler;

  /* Enable DMMU */

  lo_dmmu_en ();

}

/* Disable DMMU */

void dmmu_disable (void)

{

  mtspr (SPR_SR, mfspr (SPR_SR) & ~SPR_SR_DME);

}

/* Invalidate all entries in ITLB and enable IMMU */

void immu_enable (void)

{

  /* Register ITLB miss handler */

  excpt_itlbmiss = (unsigned long)itlb_miss_handler;

  /* Register instruction page fault handler */

  excpt_ipfault = (unsigned long)ipage_fault_handler;

  /* Enable IMMU */

  lo_immu_en ();

}

/* Disable IMMU */

void immu_disable (void)

{

  mtspr (SPR_SR, mfspr (SPR_SR) & ~SPR_SR_IME);

}

void write_pattern(unsigned long start, unsigned long end)

{

  unsigned long add;

  add = start;

  while (add < end) {

    REG32(add) = add;

    add += PAGE_SIZE;

  }

}

/* Translation address register test

   Set various translation and check the pattern */

int dtlb_translation_test (void)

{

  int i, j;

  unsigned long ea, ta;

  /* Disable DMMU */

  dmmu_disable();

  /* Invalidate all entries in DTLB */

  for (i = 0; i < DTLB_WAYS; i++) {

    for (j = 0; j < DTLB_SETS; j++) {

      mtspr (SPR_DTLBMR_BASE(i) + j, 0);

      mtspr (SPR_DTLBTR_BASE(i) + j, 0);

    }

  }

  /* Set one to one translation for the use of this program */

  for (i = 0; i < TLB_DATA_SET_NB; i++) {

    ea = RAM_START + (i*PAGE_SIZE);

    ta = RAM_START + (i*PAGE_SIZE);

    mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_DTLBMR_V);

    mtspr (SPR_DTLBTR_BASE(0) + i, ta | DTLB_PR_NOLIMIT);

  }

  /* Set dtlb permisions */

  dtlb_val = DTLB_PR_NOLIMIT;

  /* Write test pattern */

  for (i = 0; i < DTLB_SETS; i++) {

    REG32(RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE)) = i;

    REG32(RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4) = 0xffffffff - i;

  }

  /* Set one to one translation of the last way of DTLB */

  for (i = TLB_DATA_SET_NB; i < DTLB_SETS; i++) {

    ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);

    ta = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);

    mtspr (SPR_DTLBMR_BASE(DTLB_WAYS - 1) + i, ea | SPR_DTLBMR_V);

    mtspr (SPR_DTLBTR_BASE(DTLB_WAYS - 1) + i, ta | DTLB_PR_NOLIMIT);

  }

  /* Enable DMMU */

  dmmu_enable();

  /* Check the pattern */

  for (i = TLB_DATA_SET_NB; i < DTLB_SETS; i++) {

    ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);

    ASSERT(REG32(ea) == i);

    ea = RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4;

    ASSERT(REG32(ea) == (0xffffffff - i));

  }

  /* Write new pattern */

  for (i = TLB_DATA_SET_NB; i < DTLB_SETS; i++) {

    REG32(RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE)) = 0xffffffff - i;

    REG32(RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4) = i;

  }

  /* Set 0 -> RAM_START + (RAM_SIZE/2) translation */

  for (i = TLB_DATA_SET_NB; i < DTLB_SETS; i++) {

    ea = i*PAGE_SIZE;

    ta = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);

    mtspr (SPR_DTLBMR_BASE(DTLB_WAYS - 1) + i, ea | SPR_DTLBMR_V);

    mtspr (SPR_DTLBTR_BASE(DTLB_WAYS - 1) + i, ta | DTLB_PR_NOLIMIT);

  }

  /* Check the pattern */

  for (i = TLB_DATA_SET_NB; i < DTLB_SETS; i++) {

    ea = i*PAGE_SIZE;

    ASSERT(REG32(ea) == (0xffffffff - i));

    ea = ((i + 1)*PAGE_SIZE) - 4;

    ASSERT(REG32(ea) == i);

  }

  /* Write new pattern */

  for (i = TLB_DATA_SET_NB; i < DTLB_SETS; i++) {

    REG32(i*PAGE_SIZE) = i;

    REG32(((i + 1)*PAGE_SIZE) - 4) = 0xffffffff - i;

  }

  /* Set hi -> lo, lo -> hi translation */

  for (i = TLB_DATA_SET_NB; i < DTLB_SETS; i++) {

    ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);

    ta = RAM_START + (RAM_SIZE/2) + ((DTLB_SETS - i - 1 + TLB_DATA_SET_NB)*PAGE_SIZE);

    mtspr (SPR_DTLBMR_BASE(DTLB_WAYS - 1) + i, ea | SPR_DTLBMR_V);

    mtspr (SPR_DTLBTR_BASE(DTLB_WAYS - 1) + i, ta | DTLB_PR_NOLIMIT);

  }

  /* Check the pattern */

  for (i = TLB_DATA_SET_NB; i < DTLB_SETS; i++) {

    ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);

    ASSERT(REG32(ea) == (DTLB_SETS - i - 1 + TLB_DATA_SET_NB));

    ea = RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4;

    ASSERT(REG32(ea) == (0xffffffff - DTLB_SETS + i + 1 - TLB_DATA_SET_NB));

  }

  /* Write new pattern */

  for (i = TLB_DATA_SET_NB; i < DTLB_SETS; i++) {

    REG32(RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE)) = 0xffffffff - i;

    REG32(RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4) = i;

  }

  /* Disable DMMU */

  dmmu_disable();

  /* Check the pattern */

  for (i = TLB_DATA_SET_NB; i < DTLB_SETS; i++) {

    ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);

    ASSERT(REG32(ea) == (0xffffffff - DTLB_SETS + i + 1 - TLB_DATA_SET_NB));

    ea = RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4;

    ASSERT(REG32(ea) == (DTLB_SETS - i - 1 + TLB_DATA_SET_NB));

  }

  return 0;

}

/* EA match register test

   Shifting one in DTLBMR and performing accesses to boundaries

   of the page, checking the triggering of exceptions */

int dtlb_match_test (int way, int set)

{

  int i, j, tmp;

  unsigned long add, t_add;

  unsigned long ea, ta;

  /* Disable DMMU */

  dmmu_disable();

  /* Invalidate all entries in DTLB */

  for (i = 0; i < DTLB_WAYS; i++) {

    for (j = 0; j < DTLB_SETS; j++) {

      mtspr (SPR_DTLBMR_BASE(i) + j, 0);

      mtspr (SPR_DTLBTR_BASE(i) + j, 0);

    }

  }

  /* Set one to one translation for the use of this program */

  for (i = 0; i < TLB_DATA_SET_NB; i++) {

    ea = RAM_START + (i*PAGE_SIZE);

    ta = RAM_START + (i*PAGE_SIZE);

    mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_DTLBMR_V);

    mtspr (SPR_DTLBTR_BASE(0) + i, ta | DTLB_PR_NOLIMIT);

  }

  /* Set dtlb permisions */

  dtlb_val = DTLB_PR_NOLIMIT;

  /* Set pattern */

  REG32(RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE) - 4) = 0x00112233;

  REG32(RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE)) = 0x44556677;

  REG32(RAM_START + (RAM_SIZE/2) + (set + 1)*PAGE_SIZE - 4) = 0x8899aabb;

  REG32(RAM_START + (RAM_SIZE/2) + (set + 1)*PAGE_SIZE) = 0xccddeeff;

  /* Enable DMMU */

  dmmu_enable();

  /* Shifting one in DTLBMR */

  i = 0;

  add = (PAGE_SIZE*DTLB_SETS);

  t_add = add + (set*PAGE_SIZE);

  while (add != 0x00000000) {

    mtspr (SPR_DTLBMR_BASE(way) + set, t_add | SPR_DTLBMR_V);

    mtspr (SPR_DTLBTR_BASE(way) + set, (RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE)) | DTLB_PR_NOLIMIT);

    /* Reset DTLB miss counter and EA */

    dtlb_miss_count = 0;

    dtlb_miss_ea = 0;

    if (((t_add < RAM_START) || (t_add >= DATA_END_ADD)) && ((t_add < FLASH_START) || (t_add >= TEXT_END_ADD))) {

      /* Read last address of previous page */

      tmp = REG32(t_add - 4);

      ASSERT(tmp == 0x00112233);

      ASSERT(dtlb_miss_count == 1);

      /* Read first address of the page */

      tmp = REG32(t_add);

      ASSERT(tmp == 0x44556677);

      ASSERT(dtlb_miss_count == 1);

      /* Read last address of the page */

      tmp = REG32(t_add + PAGE_SIZE - 4);

      ASSERT(tmp == 0x8899aabb);

      ASSERT(dtlb_miss_count == 1);

      /* Read first address of next page */

      tmp = REG32(t_add + PAGE_SIZE);

      ASSERT(tmp == 0xccddeeff);

      ASSERT(dtlb_miss_count == 2);

    }

    i++;

    add = (PAGE_SIZE*DTLB_SETS) << i;

    t_add = add + (set*PAGE_SIZE);

    for (j = 0; j < DTLB_WAYS; j++) {

      mtspr (SPR_DTLBMR_BASE(j) + ((set - 1) & (DTLB_SETS - 1)), 0);

      mtspr (SPR_DTLBMR_BASE(j) + ((set + 1) & (DTLB_SETS - 1)), 0);

    }

  }

  /* Disable DMMU */

  dmmu_disable();

  return 0;

}

/* Valid bit test

   Set all ways of one set to be invalid, perform

   access so miss handler will set them to valid,

   try access again - there should be no miss exceptions */

int dtlb_valid_bit_test (int set)

{

  int i, j;

  unsigned long ea, ta;

  /* Disable DMMU */

  dmmu_disable();

  /* Invalidate all entries in DTLB */

  for (i = 0; i < DTLB_WAYS; i++) {

    for (j = 0; j < DTLB_SETS; j++) {

      mtspr (SPR_DTLBMR_BASE(i) + j, 0);

      mtspr (SPR_DTLBTR_BASE(i) + j, 0);