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/* pcu.S -- Tests the performance counters unit
 
   Contributor Julius Baxter 
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see .  */
 
/* Currently only checks instruction fetch, TLB miss and cache miss counters. */
 
#include "spr-defs.h"
 
        .section .except,"ax"
 
        .org 0x100
        l.j     start_test
        l.nop
        .org 0x200
        l.jal   unhandled_except
        l.nop
        .org 0x300
        l.jal   unhandled_except
        l.nop
        .org 0x400
        l.jal   unhandled_except
        l.nop
        .org 0x500
        l.jal   unhandled_except
        l.nop
        .org 0x600
        l.jal   unhandled_except
        l.nop
        .org 0x700
        l.jal   unhandled_except
        l.nop
        .org 0x800
        l.jal   unhandled_except
        l.nop
 
        /* DTLB miss - just disable DMMU and return */
        /* clobber r13 */
        .org 0x900
        l.mfspr r13,r0,SPR_ESR_BASE
        l.xori  r13,r13,SPR_SR_DME
        l.mtspr r0,r13,SPR_ESR_BASE
        l.rfe
 
        /* ITLB miss - just disable IMMU and return */
        /* clobber r13 */
        .org 0xa00
        l.mfspr r13,r0,SPR_ESR_BASE
        l.xori  r13,r13,SPR_SR_IME
        l.mtspr r0,r13,SPR_ESR_BASE
        l.rfe
 
        .org 0xb00
        l.jal   unhandled_except
        l.nop
 
        /* System call - switches user/supervisor mode */
        /* Clobbers r13 */
        .org 0xc00
        l.mfspr r13,r0,SPR_ESR_BASE
        l.xori  r13,r13,SPR_SR_SM       /* Toggle SM bit */
        l.mtspr r0,r13,SPR_ESR_BASE
        l.rfe
 
        .org 0xd00
        l.jal   unhandled_except
        l.nop
        .org 0xe00
        l.jal   unhandled_except
        l.nop
        .org 0xf00
        l.jal   unhandled_except
        l.nop
 
 
        .section .text
start_test:
        /* Check PCU is present */
        l.movhi r0,0
        l.mfspr r2,r0,SPR_UPR
        l.andi  r2,r2,SPR_UPR_PCUP
        l.sfnei r2,SPR_UPR_PCUP
        /* Fail if not present */
        l.bf    fail
        l.nop
 
        /* Assumption that we are already in SM */
 
        /* Set SUMRA bit in SR */
        l.movhi r2,hi(SPR_SR_SUMRA)
        l.mfspr r3,r0,SPR_SR
        l.or    r3,r3,r2
        l.mtspr r0,r3,SPR_SR
 
        /* Check instruction fetch counter - supervisor mode */
        /* r1 - counter of which counter (0-7) we're using */
        l.movhi r1,0
        /* use r5 to hold pcmr value */
        l.ori   r5,r0,(SPR_PCMR_CISM | SPR_PCMR_IF | SPR_PCMR_UMRA)
        /* report pcmr value */
        l.or    r3,r5,r5
        l.nop   NOP_REPORT
pcr_if_sm:
        /* report which counter we're using */
        l.or    r3,r1,r1
        l.nop   NOP_REPORT
        /* clear (0) pccr */
        l.mtspr r1,r0,SPR_PCCR(0)
        /* Load pcmr with appropriate mode */
        l.mtspr r1,r5,SPR_PCMR(0)
        /* This next instruction should be counted */
        l.nop
        /* Pull PCCR out and check it's != 0 */
        l.mfspr r3,r1,SPR_PCCR(0)
        //l.nop NOP_REPORT
        l.sfnei r3,0
        l.bnf   fail
 
        /* Now change to usermode, ensure the counter doesn't increment */
        l.sys   0
        /* SM = 0 */
        l.mfspr r6,r1,SPR_PCCR(0)
        l.nop
        l.nop
        l.nop
        l.mfspr r7,r1,SPR_PCCR(0)
        /* r6 and r7 should be equal */
        l.sfne  r6,r7
        l.bf    fail
        l.sys   0
        /* SM = 1 */
 
        /* End of loop */
        l.sfeqi r1,7            /* Finished checking all 8 regs? */
        l.bnf   pcr_if_sm       /* check next set */
        l.addi  r1,r1,1         /* increment set counter */
 
 
        /* Check instruction fetch counter - user mode */
        /* r1 - counter of which counter (0-7) we're using */
        l.movhi r1,0
        /* use r5 to hold pcmr value */
        l.ori   r5,r0,(SPR_PCMR_CIUM | SPR_PCMR_IF | SPR_PCMR_UMRA)
        /* report pcmr value */
        l.or    r3,r5,r5
        l.nop   NOP_REPORT
pcr_if_um:
        /* report which counter we're using */
        l.or    r3,r1,r1
        l.nop   NOP_REPORT
        /* clear (0) pccr */
        l.mtspr r1,r0,SPR_PCCR(0)
        /* Load pcmr with appropriate mode */
        l.mtspr r1,r5,SPR_PCMR(0)
        /* Switch to user mode */
        l.sys 0
        /* SM = 0 */
        /* This next instruction should be counted */
        l.nop
        l.mfspr r6,r1,SPR_PCCR(0)
        l.nop
        l.nop
        l.mfspr r7,r1,SPR_PCCR(0)
        /* r6 should be smaller than r7 */
        l.sfgeu r6,r7
        l.bf    fail
 
        /* Now change to supervisor, ensure the counter doesn't increment */
        l.sys   0
        /* SM = 1 */
        l.mfspr r6,r1,SPR_PCCR(0)
        l.nop
        l.nop
        l.nop
        l.mfspr r7,r1,SPR_PCCR(0)
        /* r6 and r7 should be equal */
        l.sfeq  r6,r7
        l.bnf   fail
 
        /* End of loop */
        l.sfeqi r1,7            /* Finished checking all 8 regs? */
        l.bnf   pcr_if_um       /* check next set */
        l.addi  r1,r1,1         /* increment set counter */
 
 
        /* Check for MMU miss */
        /* immu */
 
        /* Clear MMU match registers, will cause a miss as soon as we turn on
        the MMU */
        l.movhi r1,0    /* Set counter */
        l.movhi r2,0    /* Way counter */
immu_clear_ways:
        l.slli  r3,r2,8 /* way * 0x100 */
immu_clear_sets:
        l.add   r4,r1,r3        /* set + way */
        /* clear immu entry */
        l.mtspr r4,r0,SPR_ITLBMR_BASE(0)
        l.mtspr r4,r0,SPR_ITLBTR_BASE(0)
        /* End of immu sets? */
        l.sfnei r1,127
        l.bf    immu_clear_sets
        l.addi  r1,r1,1
 
        /* Reset set counter */
        l.movhi r1,0
 
        /* end of immu ways? */
        l.sfnei r2,3
        l.bf    immu_clear_ways
        l.addi  r2,r2,1
 
        /* Check itlb miss counter */
        /* r1 - counter of which counter (0-7) we're using */
        l.movhi r1,0
        /* use r5 to hold pcmr value */
        l.ori   r5,r0,(SPR_PCMR_CISM | SPR_PCMR_ITLBM | SPR_PCMR_UMRA)
        /* report pcmr value */
        l.or    r3,r5,r5
        l.nop   NOP_REPORT
pcr_itlbm:
        /* report which counter we're using */
        l.or    r3,r1,r1
        l.nop   NOP_REPORT
        /* clear (0) pccr */
        l.mtspr r1,r0,SPR_PCCR(0)
        /* Load pcmr with appropriate mode */
        l.mtspr r1,r5,SPR_PCMR(0)
 
        /* Switch on IMMU - cause tlb miss*/
        l.mfspr r4,r0,SPR_SR
        l.ori   r4,r4,SPR_SR_IME
        l.mtspr r0,r4,SPR_SR
        /* Miss should occur here */
 
        /* Check PCCR incremented */
        l.mfspr r6,r1,SPR_PCCR(0)
        l.sfeq  r6,r0
        l.bf    fail
 
        /* End of loop */
        l.sfeqi r1,7            /* Finished checking all 8 regs? */
        l.bnf   pcr_itlbm       /* check next set */
        l.addi  r1,r1,1         /* increment set counter */
 
        /* Check for MMU miss */
        /* dmmu */
 
        /* Clear MMU match registers, will cause a miss as soon as we turn on
        the MMU */
        l.movhi r1,0    /* Set counter */
        l.movhi r2,0    /* Way counter */
dmmu_clear_ways:
        l.slli  r3,r2,8 /* way * 0x100 */
dmmu_clear_sets:
        l.add   r4,r1,r3        /* set + way */
        /* clear dmmu entry */
        l.mtspr r4,r0,SPR_DTLBMR_BASE(0)
        l.mtspr r4,r0,SPR_DTLBTR_BASE(0)
        /* End of dmmu sets? */
        l.sfnei r1,127
        l.bf    dmmu_clear_sets
        l.addi  r1,r1,1
 
        /* Reset set counter */
        l.movhi r1,0
 
        /* end of dmmu ways? */
        l.sfnei r2,3
        l.bf    dmmu_clear_ways
        l.addi  r2,r2,1
 
        /* Check dtlb miss counter */
        /* r1 - counter of which counter (0-7) we're using */
        l.movhi r1,0
        /* use r5 to hold pcmr value */
        l.ori   r5,r0,(SPR_PCMR_CISM | SPR_PCMR_DTLBM | SPR_PCMR_UMRA)
        /* report pcmr value */
        l.or    r3,r5,r5
        l.nop   NOP_REPORT
pcr_dtlbm:
        /* report which counter we're using */
        l.or    r3,r1,r1
        l.nop   NOP_REPORT
        /* clear (0) pccr */
        l.mtspr r1,r0,SPR_PCCR(0)
        /* Load pcmr with appropriate mode */
        l.mtspr r1,r5,SPR_PCMR(0)
 
        /* Switch on DMMU - cause tlb miss*/
        l.mfspr r4,r0,SPR_SR
        l.ori   r4,r4,SPR_SR_DME
        l.mtspr r0,r4,SPR_SR
 
        l.sw    0(r0),r6
        /* Miss should occur here */
 
        /* Check PCCR incremented */
        l.mfspr r6,r1,SPR_PCCR(0)
        l.sfeq  r6,r0
        l.bf    fail
 
        /* End of loop */
        l.sfeqi r1,7            /* Finished checking all 8 regs? */
        l.bnf   pcr_dtlbm       /* check next set */
        l.addi  r1,r1,1         /* increment set counter */
 
 
        /* Check instruction cache miss counter */
icache_miss_test:
        /* Check if IC present and skip enabling otherwise */
        l.mfspr r3,r0,SPR_UPR
        l.andi  r4,r3,SPR_UPR_ICP
        l.sfeq  r4,r0
        l.bf    dcache_miss_test
        l.nop
 
        /* r1 - counter of which counter (0-7) we're using */
        l.movhi r1,0
 
 
        /* use r5 to hold pcmr value */
        l.ori   r5,r0,(SPR_PCMR_CISM | SPR_PCMR_ICM | SPR_PCMR_UMRA)
        /* report pcmr value */
        l.or    r3,r5,r5
        l.nop   NOP_REPORT
 
pcr_icmiss:
        /* report which counter we're using */
        l.or    r3,r1,r1
        l.nop   NOP_REPORT
        /* clear (0) pccr */
        l.mtspr r1,r0,SPR_PCCR(0)
        /* Load pcmr with appropriate mode */
        /* use r5 to hold pcmr value */
        l.ori   r5,r0,(SPR_PCMR_CISM | SPR_PCMR_ICM | SPR_PCMR_UMRA)
        l.mtspr r1,r5,SPR_PCMR(0)
 
        /* Disable IC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_ICE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
 
        /* Establish cache block size
        If BS=0, 16;
        If BS=1, 32;
        r14 contain block size
        */
        l.mfspr r3,r0,SPR_ICCFGR
        l.andi  r4,r3,SPR_ICCFGR_CBS
        l.srli  r5,r4,7
        l.ori   r6,r0,16
        l.sll   r14,r6,r5
 
        /* Establish number of cache sets
        r7 contains number of cache sets
        r5 contains log(# of cache sets)
        */
        l.andi  r4,r3,SPR_ICCFGR_NCS
        l.srli  r5,r4,3
        l.ori   r6,r0,1
        l.sll   r7,r6,r5
 
        /* Invalidate IC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r5
 
.L7:
        l.mtspr r0,r6,SPR_ICBIR
        l.sfne  r6,r5
        l.bf    .L7
        l.add   r6,r6,r14
 
        /* Enable IC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_ICE
        l.mtspr r0,r6,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
 
        /* Should have had at least 1 miss, check this */
        l.mfspr r6,r1,SPR_PCCR(0)
        l.sfeq  r6,r0
        l.bf    fail
        l.nop
 
        /* End of loop */
        l.sfeqi r1,7            /* Finished checking all 8 regs? */
        l.bnf   pcr_icmiss      /* check next set */
        l.addi  r1,r1,1         /* increment set counter */
 
 
 
dcache_miss_test:
 
        /* Check if DC present and skip enabling otherwise */
        l.mfspr r3,r0,SPR_UPR
        l.andi  r4,r3,SPR_UPR_DCP
        l.sfeq  r4,r0
        l.bf    dcache_miss_test_done
        l.nop
 
        /* r1 - counter of which counter (0-7) we're using */
        l.movhi r1,0
 
        /* use r5 to hold pcmr value */
        l.ori   r5,r0,(SPR_PCMR_CISM | SPR_PCMR_DCM | SPR_PCMR_UMRA)
        /* report pcmr value */
        l.or    r3,r5,r5
        l.nop   NOP_REPORT
 
pcr_dcmiss:
        /* report which counter we're using */
        l.or    r3,r1,r1
        l.nop   NOP_REPORT
        /* clear (0) pccr */
        l.mtspr r1,r0,SPR_PCCR(0)
        /* Load pcmr with appropriate mode */
        /* use r5 to hold pcmr value */
        l.ori   r5,r0,(SPR_PCMR_CISM | SPR_PCMR_DCM | SPR_PCMR_UMRA)
        l.mtspr r1,r5,SPR_PCMR(0)
 
                /* Disable DC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
        /* Establish cache block size
           If BS=0, 16;
           If BS=1, 32;
           r14 contain block size
        */
        l.mfspr r3,r0,SPR_DCCFGR
        l.andi  r4,r3,SPR_DCCFGR_CBS
        l.srli  r5,r4,7
        l.ori   r6,r0,16
        l.sll   r14,r6,r5
        /* Establish number of cache sets
           r7 contains number of cache sets
           r5 contains log(# of cache sets)
        */
        l.andi  r4,r3,SPR_DCCFGR_NCS
        l.srli  r5,r4,3
        l.ori   r6,r0,1
        l.sll   r7,r6,r5
        /* Invalidate DC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r5
.L9:
        l.mtspr r0,r6,SPR_DCBIR
        l.sfne  r6,r5
        l.bf    .L9
        l.add   r6,r6,r14
        /* Enable DC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_DCE
        l.mtspr r0,r6,SPR_SR
 
        /* Should trigger a dcache miss */
        l.sw    0(r0),r6
        /* Should trigger another dcache miss */
        l.lwz   r6,0x1000(r0)
 
        /* Should have had 2 misses */
        l.mfspr r6,r1,SPR_PCCR(0)
        l.sfnei r6,2
        l.bf    fail
        l.nop
 
        /* End of loop */
        l.sfeqi r1,7            /* Finished checking all 8 regs? */
        l.bnf   pcr_dcmiss      /* check next set */
        l.addi  r1,r1,1         /* increment set counter */
 
dcache_miss_test_done:
 
finish_ok:
        l.movhi r3,0xdead
        l.ori   r3,r3,0xdead
        l.nop   NOP_REPORT
        l.ori   r3,r0,0
        l.nop   NOP_EXIT
 
fail:
        l.ori   r3,r0,0x1234
        l.nop   NOP_EXIT
 
unhandled_except:
        l.addi  r3,r9,-8
        l.nop   NOP_REPORT
        l.nop   NOP_EXIT
 

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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [pcu/] [pcu.S] - Blame information for rev 731

Line No.	Rev	Author	Line
1	556	julius	`/* pcu.S -- Tests the performance counters unit`
2
3			`Contributor Julius Baxter`
4
5			`This file is part of OpenRISC 1000 Architectural Simulator.`
6
7			`This program is free software; you can redistribute it and/or modify it`
8			`under the terms of the GNU General Public License as published by the Free`
9			`Software Foundation; either version 3 of the License, or (at your option)`
10			`any later version.`
11
12			`This program is distributed in the hope that it will be useful, but WITHOUT`
13			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
14			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
15			`more details.`
16
17			`You should have received a copy of the GNU General Public License along`
18			`with this program. If not, see . */`
19
20			`/* Currently only checks instruction fetch, TLB miss and cache miss counters. */`
21
22			`#include "spr-defs.h"`
23
24			`.section .except,"ax"`
25
26			`.org 0x100`
27			`l.j start_test`
28			`l.nop`
29			`.org 0x200`
30			`l.jal unhandled_except`
31			`l.nop`
32			`.org 0x300`
33			`l.jal unhandled_except`
34			`l.nop`
35			`.org 0x400`
36			`l.jal unhandled_except`
37			`l.nop`
38			`.org 0x500`
39			`l.jal unhandled_except`
40			`l.nop`
41			`.org 0x600`
42			`l.jal unhandled_except`
43			`l.nop`
44			`.org 0x700`
45			`l.jal unhandled_except`
46			`l.nop`
47			`.org 0x800`
48			`l.jal unhandled_except`
49			`l.nop`
50
51			`/* DTLB miss - just disable DMMU and return */`
52			`/* clobber r13 */`
53			`.org 0x900`
54			`l.mfspr r13,r0,SPR_ESR_BASE`
55			`l.xori r13,r13,SPR_SR_DME`
56			`l.mtspr r0,r13,SPR_ESR_BASE`
57			`l.rfe`
58
59			`/* ITLB miss - just disable IMMU and return */`
60			`/* clobber r13 */`
61			`.org 0xa00`
62			`l.mfspr r13,r0,SPR_ESR_BASE`
63			`l.xori r13,r13,SPR_SR_IME`
64			`l.mtspr r0,r13,SPR_ESR_BASE`
65			`l.rfe`
66
67			`.org 0xb00`
68			`l.jal unhandled_except`
69			`l.nop`
70
71			`/* System call - switches user/supervisor mode */`
72			`/* Clobbers r13 */`
73			`.org 0xc00`
74			`l.mfspr r13,r0,SPR_ESR_BASE`
75			`l.xori r13,r13,SPR_SR_SM /* Toggle SM bit */`
76			`l.mtspr r0,r13,SPR_ESR_BASE`
77			`l.rfe`
78
79			`.org 0xd00`
80			`l.jal unhandled_except`
81			`l.nop`
82			`.org 0xe00`
83			`l.jal unhandled_except`
84			`l.nop`
85			`.org 0xf00`
86			`l.jal unhandled_except`
87			`l.nop`
88
89
90			`.section .text`
91			`start_test:`
92			`/* Check PCU is present */`
93			`l.movhi r0,0`
94			`l.mfspr r2,r0,SPR_UPR`
95			`l.andi r2,r2,SPR_UPR_PCUP`
96			`l.sfnei r2,SPR_UPR_PCUP`
97			`/* Fail if not present */`
98			`l.bf fail`
99			`l.nop`
100
101			`/* Assumption that we are already in SM */`
102
103			`/* Set SUMRA bit in SR */`
104			`l.movhi r2,hi(SPR_SR_SUMRA)`
105			`l.mfspr r3,r0,SPR_SR`
106			`l.or r3,r3,r2`
107			`l.mtspr r0,r3,SPR_SR`
108
109			`/* Check instruction fetch counter - supervisor mode */`
110			`/* r1 - counter of which counter (0-7) we're using */`
111			`l.movhi r1,0`
112			`/* use r5 to hold pcmr value */`
113			`l.ori r5,r0,(SPR_PCMR_CISM \| SPR_PCMR_IF \| SPR_PCMR_UMRA)`
114			`/* report pcmr value */`
115			`l.or r3,r5,r5`
116			`l.nop NOP_REPORT`
117			`pcr_if_sm:`
118			`/* report which counter we're using */`
119			`l.or r3,r1,r1`
120			`l.nop NOP_REPORT`
121			`/* clear (0) pccr */`
122			`l.mtspr r1,r0,SPR_PCCR(0)`
123			`/* Load pcmr with appropriate mode */`
124			`l.mtspr r1,r5,SPR_PCMR(0)`
125			`/* This next instruction should be counted */`
126			`l.nop`
127			`/* Pull PCCR out and check it's != 0 */`
128			`l.mfspr r3,r1,SPR_PCCR(0)`
129			`//l.nop NOP_REPORT`
130			`l.sfnei r3,0`
131			`l.bnf fail`
132
133			`/* Now change to usermode, ensure the counter doesn't increment */`
134			`l.sys 0`
135			`/* SM = 0 */`
136			`l.mfspr r6,r1,SPR_PCCR(0)`
137			`l.nop`
138			`l.nop`
139			`l.nop`
140			`l.mfspr r7,r1,SPR_PCCR(0)`
141			`/* r6 and r7 should be equal */`
142			`l.sfne r6,r7`
143			`l.bf fail`
144			`l.sys 0`
145			`/* SM = 1 */`
146
147			`/* End of loop */`
148			`l.sfeqi r1,7 /* Finished checking all 8 regs? */`
149			`l.bnf pcr_if_sm /* check next set */`
150			`l.addi r1,r1,1 /* increment set counter */`
151
152
153			`/* Check instruction fetch counter - user mode */`
154			`/* r1 - counter of which counter (0-7) we're using */`
155			`l.movhi r1,0`
156			`/* use r5 to hold pcmr value */`
157			`l.ori r5,r0,(SPR_PCMR_CIUM \| SPR_PCMR_IF \| SPR_PCMR_UMRA)`
158			`/* report pcmr value */`
159			`l.or r3,r5,r5`
160			`l.nop NOP_REPORT`
161			`pcr_if_um:`
162			`/* report which counter we're using */`
163			`l.or r3,r1,r1`
164			`l.nop NOP_REPORT`
165			`/* clear (0) pccr */`
166			`l.mtspr r1,r0,SPR_PCCR(0)`
167			`/* Load pcmr with appropriate mode */`
168			`l.mtspr r1,r5,SPR_PCMR(0)`
169			`/* Switch to user mode */`
170			`l.sys 0`
171			`/* SM = 0 */`
172			`/* This next instruction should be counted */`
173			`l.nop`
174			`l.mfspr r6,r1,SPR_PCCR(0)`
175			`l.nop`
176			`l.nop`
177			`l.mfspr r7,r1,SPR_PCCR(0)`
178			`/* r6 should be smaller than r7 */`
179			`l.sfgeu r6,r7`
180			`l.bf fail`
181
182			`/* Now change to supervisor, ensure the counter doesn't increment */`
183			`l.sys 0`
184			`/* SM = 1 */`
185			`l.mfspr r6,r1,SPR_PCCR(0)`
186			`l.nop`
187			`l.nop`
188			`l.nop`
189			`l.mfspr r7,r1,SPR_PCCR(0)`
190			`/* r6 and r7 should be equal */`
191			`l.sfeq r6,r7`
192			`l.bnf fail`
193
194			`/* End of loop */`
195			`l.sfeqi r1,7 /* Finished checking all 8 regs? */`
196			`l.bnf pcr_if_um /* check next set */`
197			`l.addi r1,r1,1 /* increment set counter */`
198
199
200			`/* Check for MMU miss */`
201			`/* immu */`
202
203			`/* Clear MMU match registers, will cause a miss as soon as we turn on`
204			`the MMU */`
205			`l.movhi r1,0 /* Set counter */`
206			`l.movhi r2,0 /* Way counter */`
207			`immu_clear_ways:`
208			`l.slli r3,r2,8 /* way * 0x100 */`
209			`immu_clear_sets:`
210			`l.add r4,r1,r3 /* set + way */`
211			`/* clear immu entry */`
212			`l.mtspr r4,r0,SPR_ITLBMR_BASE(0)`
213			`l.mtspr r4,r0,SPR_ITLBTR_BASE(0)`
214			`/* End of immu sets? */`
215			`l.sfnei r1,127`
216			`l.bf immu_clear_sets`
217			`l.addi r1,r1,1`
218
219			`/* Reset set counter */`
220			`l.movhi r1,0`
221
222			`/* end of immu ways? */`
223			`l.sfnei r2,3`
224			`l.bf immu_clear_ways`
225			`l.addi r2,r2,1`
226
227			`/* Check itlb miss counter */`
228			`/* r1 - counter of which counter (0-7) we're using */`
229			`l.movhi r1,0`
230			`/* use r5 to hold pcmr value */`
231			`l.ori r5,r0,(SPR_PCMR_CISM \| SPR_PCMR_ITLBM \| SPR_PCMR_UMRA)`
232			`/* report pcmr value */`
233			`l.or r3,r5,r5`
234			`l.nop NOP_REPORT`
235			`pcr_itlbm:`
236			`/* report which counter we're using */`
237			`l.or r3,r1,r1`
238			`l.nop NOP_REPORT`
239			`/* clear (0) pccr */`
240			`l.mtspr r1,r0,SPR_PCCR(0)`
241			`/* Load pcmr with appropriate mode */`
242			`l.mtspr r1,r5,SPR_PCMR(0)`
243
244			`/* Switch on IMMU - cause tlb miss*/`
245			`l.mfspr r4,r0,SPR_SR`
246			`l.ori r4,r4,SPR_SR_IME`
247			`l.mtspr r0,r4,SPR_SR`
248			`/* Miss should occur here */`
249
250			`/* Check PCCR incremented */`
251			`l.mfspr r6,r1,SPR_PCCR(0)`
252			`l.sfeq r6,r0`
253			`l.bf fail`
254
255			`/* End of loop */`
256			`l.sfeqi r1,7 /* Finished checking all 8 regs? */`
257			`l.bnf pcr_itlbm /* check next set */`
258			`l.addi r1,r1,1 /* increment set counter */`
259
260			`/* Check for MMU miss */`
261			`/* dmmu */`
262
263			`/* Clear MMU match registers, will cause a miss as soon as we turn on`
264			`the MMU */`
265			`l.movhi r1,0 /* Set counter */`
266			`l.movhi r2,0 /* Way counter */`
267			`dmmu_clear_ways:`
268			`l.slli r3,r2,8 /* way * 0x100 */`
269			`dmmu_clear_sets:`
270			`l.add r4,r1,r3 /* set + way */`
271			`/* clear dmmu entry */`
272			`l.mtspr r4,r0,SPR_DTLBMR_BASE(0)`
273			`l.mtspr r4,r0,SPR_DTLBTR_BASE(0)`
274			`/* End of dmmu sets? */`
275			`l.sfnei r1,127`
276			`l.bf dmmu_clear_sets`
277			`l.addi r1,r1,1`
278
279			`/* Reset set counter */`
280			`l.movhi r1,0`
281
282			`/* end of dmmu ways? */`
283			`l.sfnei r2,3`
284			`l.bf dmmu_clear_ways`
285			`l.addi r2,r2,1`
286
287			`/* Check dtlb miss counter */`
288			`/* r1 - counter of which counter (0-7) we're using */`
289			`l.movhi r1,0`
290			`/* use r5 to hold pcmr value */`
291			`l.ori r5,r0,(SPR_PCMR_CISM \| SPR_PCMR_DTLBM \| SPR_PCMR_UMRA)`
292			`/* report pcmr value */`
293			`l.or r3,r5,r5`
294			`l.nop NOP_REPORT`
295			`pcr_dtlbm:`
296			`/* report which counter we're using */`
297			`l.or r3,r1,r1`
298			`l.nop NOP_REPORT`
299			`/* clear (0) pccr */`
300			`l.mtspr r1,r0,SPR_PCCR(0)`
301			`/* Load pcmr with appropriate mode */`
302			`l.mtspr r1,r5,SPR_PCMR(0)`
303
304			`/* Switch on DMMU - cause tlb miss*/`
305			`l.mfspr r4,r0,SPR_SR`
306			`l.ori r4,r4,SPR_SR_DME`
307			`l.mtspr r0,r4,SPR_SR`
308
309			`l.sw 0(r0),r6`
310			`/* Miss should occur here */`
311
312			`/* Check PCCR incremented */`
313			`l.mfspr r6,r1,SPR_PCCR(0)`
314			`l.sfeq r6,r0`
315			`l.bf fail`
316
317			`/* End of loop */`
318			`l.sfeqi r1,7 /* Finished checking all 8 regs? */`
319			`l.bnf pcr_dtlbm /* check next set */`
320			`l.addi r1,r1,1 /* increment set counter */`
321
322
323			`/* Check instruction cache miss counter */`
324			`icache_miss_test:`
325			`/* Check if IC present and skip enabling otherwise */`
326			`l.mfspr r3,r0,SPR_UPR`
327			`l.andi r4,r3,SPR_UPR_ICP`
328			`l.sfeq r4,r0`
329			`l.bf dcache_miss_test`
330			`l.nop`
331
332			`/* r1 - counter of which counter (0-7) we're using */`
333			`l.movhi r1,0`
334
335
336			`/* use r5 to hold pcmr value */`
337			`l.ori r5,r0,(SPR_PCMR_CISM \| SPR_PCMR_ICM \| SPR_PCMR_UMRA)`
338			`/* report pcmr value */`
339			`l.or r3,r5,r5`
340			`l.nop NOP_REPORT`
341
342			`pcr_icmiss:`
343			`/* report which counter we're using */`
344			`l.or r3,r1,r1`
345			`l.nop NOP_REPORT`
346			`/* clear (0) pccr */`
347			`l.mtspr r1,r0,SPR_PCCR(0)`
348			`/* Load pcmr with appropriate mode */`
349			`/* use r5 to hold pcmr value */`
350			`l.ori r5,r0,(SPR_PCMR_CISM \| SPR_PCMR_ICM \| SPR_PCMR_UMRA)`
351			`l.mtspr r1,r5,SPR_PCMR(0)`
352
353			`/* Disable IC */`
354			`l.mfspr r6,r0,SPR_SR`
355			`l.addi r5,r0,-1`
356			`l.xori r5,r5,SPR_SR_ICE`
357			`l.and r5,r6,r5`
358			`l.mtspr r0,r5,SPR_SR`
359
360			`/* Establish cache block size`
361			`If BS=0, 16;`
362			`If BS=1, 32;`
363			`r14 contain block size`
364			`*/`
365			`l.mfspr r3,r0,SPR_ICCFGR`
366			`l.andi r4,r3,SPR_ICCFGR_CBS`
367			`l.srli r5,r4,7`
368			`l.ori r6,r0,16`
369			`l.sll r14,r6,r5`
370
371			`/* Establish number of cache sets`
372			`r7 contains number of cache sets`
373			`r5 contains log(# of cache sets)`
374			`*/`
375			`l.andi r4,r3,SPR_ICCFGR_NCS`
376			`l.srli r5,r4,3`
377			`l.ori r6,r0,1`
378			`l.sll r7,r6,r5`
379
380			`/* Invalidate IC */`
381			`l.addi r6,r0,0`
382			`l.sll r5,r14,r5`
383
384			`.L7:`
385			`l.mtspr r0,r6,SPR_ICBIR`
386			`l.sfne r6,r5`
387			`l.bf .L7`
388			`l.add r6,r6,r14`
389
390			`/* Enable IC */`
391			`l.mfspr r6,r0,SPR_SR`
392			`l.ori r6,r6,SPR_SR_ICE`
393			`l.mtspr r0,r6,SPR_SR`
394			`l.nop`
395			`l.nop`
396			`l.nop`
397			`l.nop`
398
399			`/* Should have had at least 1 miss, check this */`
400			`l.mfspr r6,r1,SPR_PCCR(0)`
401			`l.sfeq r6,r0`
402			`l.bf fail`
403			`l.nop`
404
405			`/* End of loop */`
406			`l.sfeqi r1,7 /* Finished checking all 8 regs? */`
407			`l.bnf pcr_icmiss /* check next set */`
408			`l.addi r1,r1,1 /* increment set counter */`
409
410
411
412			`dcache_miss_test:`
413
414			`/* Check if DC present and skip enabling otherwise */`
415			`l.mfspr r3,r0,SPR_UPR`
416			`l.andi r4,r3,SPR_UPR_DCP`
417			`l.sfeq r4,r0`
418			`l.bf dcache_miss_test_done`
419			`l.nop`
420
421			`/* r1 - counter of which counter (0-7) we're using */`
422			`l.movhi r1,0`
423
424			`/* use r5 to hold pcmr value */`
425			`l.ori r5,r0,(SPR_PCMR_CISM \| SPR_PCMR_DCM \| SPR_PCMR_UMRA)`
426			`/* report pcmr value */`
427			`l.or r3,r5,r5`
428			`l.nop NOP_REPORT`
429
430			`pcr_dcmiss:`
431			`/* report which counter we're using */`
432			`l.or r3,r1,r1`
433			`l.nop NOP_REPORT`
434			`/* clear (0) pccr */`
435			`l.mtspr r1,r0,SPR_PCCR(0)`
436			`/* Load pcmr with appropriate mode */`
437			`/* use r5 to hold pcmr value */`
438			`l.ori r5,r0,(SPR_PCMR_CISM \| SPR_PCMR_DCM \| SPR_PCMR_UMRA)`
439			`l.mtspr r1,r5,SPR_PCMR(0)`
440
441			`/* Disable DC */`
442			`l.mfspr r6,r0,SPR_SR`
443			`l.addi r5,r0,-1`
444			`l.xori r5,r5,SPR_SR_DCE`
445			`l.and r5,r6,r5`
446			`l.mtspr r0,r5,SPR_SR`
447			`/* Establish cache block size`
448			`If BS=0, 16;`
449			`If BS=1, 32;`
450			`r14 contain block size`
451			`*/`
452			`l.mfspr r3,r0,SPR_DCCFGR`
453			`l.andi r4,r3,SPR_DCCFGR_CBS`
454			`l.srli r5,r4,7`
455			`l.ori r6,r0,16`
456			`l.sll r14,r6,r5`
457			`/* Establish number of cache sets`
458			`r7 contains number of cache sets`
459			`r5 contains log(# of cache sets)`
460			`*/`
461			`l.andi r4,r3,SPR_DCCFGR_NCS`
462			`l.srli r5,r4,3`
463			`l.ori r6,r0,1`
464			`l.sll r7,r6,r5`
465			`/* Invalidate DC */`
466			`l.addi r6,r0,0`
467			`l.sll r5,r14,r5`
468			`.L9:`
469			`l.mtspr r0,r6,SPR_DCBIR`
470			`l.sfne r6,r5`
471			`l.bf .L9`
472			`l.add r6,r6,r14`
473			`/* Enable DC */`
474			`l.mfspr r6,r0,SPR_SR`
475			`l.ori r6,r6,SPR_SR_DCE`
476			`l.mtspr r0,r6,SPR_SR`
477
478			`/* Should trigger a dcache miss */`
479			`l.sw 0(r0),r6`
480			`/* Should trigger another dcache miss */`
481			`l.lwz r6,0x1000(r0)`
482
483			`/* Should have had 2 misses */`
484			`l.mfspr r6,r1,SPR_PCCR(0)`
485			`l.sfnei r6,2`
486			`l.bf fail`
487			`l.nop`
488
489			`/* End of loop */`
490			`l.sfeqi r1,7 /* Finished checking all 8 regs? */`
491			`l.bnf pcr_dcmiss /* check next set */`
492			`l.addi r1,r1,1 /* increment set counter */`
493
494			`dcache_miss_test_done:`
495
496			`finish_ok:`
497			`l.movhi r3,0xdead`
498			`l.ori r3,r3,0xdead`
499			`l.nop NOP_REPORT`
500			`l.ori r3,r0,0`
501			`l.nop NOP_EXIT`
502
503			`fail:`
504			`l.ori r3,r0,0x1234`
505			`l.nop NOP_EXIT`
506
507			`unhandled_except:`
508			`l.addi r3,r9,-8`
509			`l.nop NOP_REPORT`
510			`l.nop NOP_EXIT`
511