OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [support/] [board.h] - Blame information for rev 214

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 90 jeremybenn
/* board.h -- Board definitions to match Or1ksim.
2
 
3
   Copyright (C) 2001 Simon Srot, srot@opencores.org
4
   Copyright (C) 2008, 2010 Embecosm Limited
5
 
6
   Contributor Simon Srot <srot@opencores.org>
7
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
8
 
9
   This file is part of OpenRISC 1000 Architectural Simulator.
10
 
11
   This program is free software; you can redistribute it and/or modify it
12
   under the terms of the GNU General Public License as published by the Free
13
   Software Foundation; either version 3 of the License, or (at your option)
14
   any later version.
15
 
16
   This program is distributed in the hope that it will be useful, but WITHOUT
17
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
   more details.
20
 
21
   You should have received a copy of the GNU General Public License along
22
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
23
 
24
/* ----------------------------------------------------------------------------
25
   This code is commented throughout for use with Doxygen.
26
   --------------------------------------------------------------------------*/
27
 
28
#ifndef _BOARD_H_
29
#define _BOARD_H_
30
 
31
#define MC_CSR_VAL      0x0B000300
32
#define MC_MASK_VAL     0x000003f0
33
#define FLASH_BASE_ADDR 0xf0000000
34
#define FLASH_TMS_VAL   0x00000103
35
#define SDRAM_BASE_ADDR 0x00000000
36
#define SDRAM_TMS_VAL   0x19220057
37
 
38
 
39
#define UART_BASE       0x90000000
40
#define UART_IRQ        2
41
#define ETH_BASE        0x92000000
42
#define ETH_IRQ         4
43
#define KBD_BASE_ADD    0x94000000
44
#define KBD_IRQ         5
45
#define MC_BASE_ADDR    0x93000000
46 93 jeremybenn
#define GENERIC_BASE    0x98000000
47 90 jeremybenn
#define DMA_BASE        0xb8000000
48
 
49
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.