OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [support/] [int.c] - Blame information for rev 214

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 90 jeremybenn
/* int.c -- Interrupt handling for Or1ksim tests.
2
 
3
   Copyright (C) 2001 Simon Srot, srot@opencores.org
4
   Copyright (C) 2008, 2010 Embecosm Limited
5
 
6
   Contributor Simon Srot <srot@opencores.org>
7
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
8
 
9
   This file is part of OpenRISC 1000 Architectural Simulator.
10
 
11
   This program is free software; you can redistribute it and/or modify it
12
   under the terms of the GNU General Public License as published by the Free
13
   Software Foundation; either version 3 of the License, or (at your option)
14
   any later version.
15
 
16
   This program is distributed in the hope that it will be useful, but WITHOUT
17
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
   more details.
20
 
21
   You should have received a copy of the GNU General Public License along
22
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
23
 
24
/* ----------------------------------------------------------------------------
25
   This code is commented throughout for use with Doxygen.
26
   --------------------------------------------------------------------------*/
27
 
28
/* This file is part of test microkernel for OpenRISC 1000. */
29
 
30
#include "support.h"
31
#include "spr-defs.h"
32
#include "int.h"
33
 
34
/* Interrupt handlers table */
35
struct ihnd int_handlers[MAX_INT_HANDLERS];
36
 
37
/* Initialize routine */
38
int int_init()
39
{
40
  int i;
41
 
42
  for(i = 0; i < MAX_INT_HANDLERS; i++) {
43
    int_handlers[i].handler = 0;
44
    int_handlers[i].arg = 0;
45
  }
46
 
47
  return 0;
48
}
49
 
50
/* Add interrupt handler */
51
int int_add(unsigned long vect, void (* handler)(void *), void *arg)
52
{
53
  if(vect >= MAX_INT_HANDLERS)
54
    return -1;
55
 
56
  int_handlers[vect].handler = handler;
57
  int_handlers[vect].arg = arg;
58
 
59
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
60
 
61
  return 0;
62
}
63
 
64
/* Disable interrupt */
65
int int_disable(unsigned long vect)
66
{
67
  if(vect >= MAX_INT_HANDLERS)
68
    return -1;
69
 
70
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << vect));
71
 
72
  return 0;
73
}
74
 
75
/* Enable interrupt */
76
int int_enable(unsigned long vect)
77
{
78
  if(vect >= MAX_INT_HANDLERS)
79
    return -1;
80
 
81
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
82
 
83
  return 0;
84
}
85
 
86
/* Main interrupt handler */
87
void int_main()
88
{
89
  unsigned long picsr = mfspr(SPR_PICSR);
90
  unsigned long i = 0;
91
 
92
  mtspr(SPR_PICSR, 0);
93
 
94
  while(i < 32) {
95
    if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) {
96
      (*int_handlers[i].handler)(int_handlers[i].arg);
97
      mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(0x00000001L << i));
98
    }
99
    i++;
100
  }
101
}
102
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.