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1 538 julius
/* spr-defs.h - Special purpose registers definitions file
2 233 julius
 
3
   Copyright (C) 2000 Damjan Lampret
4
   Copyright (C) 2008, 2010 Embecosm Limited
5
 
6
   Contributor Damjan Lampret <lampret@opencores.org>
7
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
8 90 jeremybenn
 
9 233 julius
   This file is part of OpenRISC 1000 Architectural Simulator.
10
 
11
   This program is free software; you can redistribute it and/or modify it
12
   under the terms of the GNU General Public License as published by the Free
13
   Software Foundation; either version 3 of the License, or (at your option)
14
   any later version.
15
 
16
   This program is distributed in the hope that it will be useful, but WITHOUT
17
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
   more details.
20
 
21
   You should have received a copy of the GNU General Public License along
22
   with this program.  If not, see <http:  www.gnu.org/licenses/>.  */
23
 
24
/* ----------------------------------------------------------------------------
25
   This code is commented throughout for use with Doxygen.
26
   --------------------------------------------------------------------------*/
27
 
28
/* This file is part of test microkernel for OpenRISC 1000. */
29
/* spr-defs.h -- Defines OR1K architecture specific special-purpose registers
30
 
31 90 jeremybenn
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
32
   Copyright (C) 2008 Embecosm Limited
33
 
34
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
35
 
36
   This file is part of OpenRISC 1000 Architectural Simulator.
37
 
38
   This program is free software; you can redistribute it and/or modify it
39
   under the terms of the GNU General Public License as published by the Free
40
   Software Foundation; either version 3 of the License, or (at your option)
41
   any later version.
42
 
43
   This program is distributed in the hope that it will be useful, but WITHOUT
44
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
45
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
46
   more details.
47
 
48
   You should have received a copy of the GNU General Public License along
49
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
50
 
51 233 julius
/* This program is commented throughout in a fashion suitable for processing
52
   with Doxygen. */
53 90 jeremybenn
 
54
 
55 233 julius
#ifndef SPR_DEFS__H
56
#define SPR_DEFS__H
57
 
58
/* Definition of special-purpose registers (SPRs). */
59
 
60 90 jeremybenn
#define MAX_GRPS (32)
61
#define MAX_SPRS_PER_GRP_BITS (11)
62
#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
63
#define MAX_SPRS (0x10000)
64
 
65
/* Base addresses for the groups */
66
#define SPRGROUP_SYS    (0<< MAX_SPRS_PER_GRP_BITS)
67
#define SPRGROUP_DMMU   (1<< MAX_SPRS_PER_GRP_BITS)
68
#define SPRGROUP_IMMU   (2<< MAX_SPRS_PER_GRP_BITS)
69
#define SPRGROUP_DC     (3<< MAX_SPRS_PER_GRP_BITS)
70
#define SPRGROUP_IC     (4<< MAX_SPRS_PER_GRP_BITS)
71
#define SPRGROUP_MAC    (5<< MAX_SPRS_PER_GRP_BITS)
72
#define SPRGROUP_D      (6<< MAX_SPRS_PER_GRP_BITS)
73
#define SPRGROUP_PC     (7<< MAX_SPRS_PER_GRP_BITS)
74
#define SPRGROUP_PM     (8<< MAX_SPRS_PER_GRP_BITS)
75
#define SPRGROUP_PIC    (9<< MAX_SPRS_PER_GRP_BITS)
76
#define SPRGROUP_TT     (10<< MAX_SPRS_PER_GRP_BITS)
77 233 julius
#define SPRGROUP_FP     (11<< MAX_SPRS_PER_GRP_BITS)
78 90 jeremybenn
 
79
/* System control and status group */
80
#define SPR_VR          (SPRGROUP_SYS + 0)
81
#define SPR_UPR         (SPRGROUP_SYS + 1)
82
#define SPR_CPUCFGR     (SPRGROUP_SYS + 2)
83
#define SPR_DMMUCFGR    (SPRGROUP_SYS + 3)
84
#define SPR_IMMUCFGR    (SPRGROUP_SYS + 4)
85
#define SPR_DCCFGR      (SPRGROUP_SYS + 5)
86
#define SPR_ICCFGR      (SPRGROUP_SYS + 6)
87
#define SPR_DCFGR       (SPRGROUP_SYS + 7)
88
#define SPR_PCCFGR      (SPRGROUP_SYS + 8)
89
#define SPR_NPC         (SPRGROUP_SYS + 16)  /* CZ 21/06/01 */
90
#define SPR_SR          (SPRGROUP_SYS + 17)  /* CZ 21/06/01 */
91
#define SPR_PPC         (SPRGROUP_SYS + 18)  /* CZ 21/06/01 */
92 233 julius
#define SPR_FPCSR       (SPRGROUP_SYS + 20)  /* CZ 21/06/01 */
93 90 jeremybenn
#define SPR_EPCR_BASE   (SPRGROUP_SYS + 32)  /* CZ 21/06/01 */
94
#define SPR_EPCR_LAST   (SPRGROUP_SYS + 47)  /* CZ 21/06/01 */
95
#define SPR_EEAR_BASE   (SPRGROUP_SYS + 48)
96
#define SPR_EEAR_LAST   (SPRGROUP_SYS + 63)
97
#define SPR_ESR_BASE    (SPRGROUP_SYS + 64)
98
#define SPR_ESR_LAST    (SPRGROUP_SYS + 79)
99 233 julius
#define SPR_GPR_BASE    (SPRGROUP_SYS + 1024)
100 90 jeremybenn
 
101
/* Data MMU group */
102
#define SPR_DMMUCR      (SPRGROUP_DMMU + 0)
103 538 julius
#define SPR_DTLBEIR     (SPRGROUP_DMMU + 2)
104 90 jeremybenn
#define SPR_DTLBMR_BASE(WAY)    (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
105
#define SPR_DTLBMR_LAST(WAY)    (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
106
#define SPR_DTLBTR_BASE(WAY)    (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
107
#define SPR_DTLBTR_LAST(WAY)    (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
108
 
109
/* Instruction MMU group */
110
#define SPR_IMMUCR      (SPRGROUP_IMMU + 0)
111 538 julius
#define SPR_ITLBEIR     (SPRGROUP_IMMU + 2)
112 90 jeremybenn
#define SPR_ITLBMR_BASE(WAY)    (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
113
#define SPR_ITLBMR_LAST(WAY)    (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
114
#define SPR_ITLBTR_BASE(WAY)    (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
115
#define SPR_ITLBTR_LAST(WAY)    (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
116
 
117
/* Data cache group */
118
#define SPR_DCCR        (SPRGROUP_DC + 0)
119
#define SPR_DCBPR       (SPRGROUP_DC + 1)
120
#define SPR_DCBFR       (SPRGROUP_DC + 2)
121
#define SPR_DCBIR       (SPRGROUP_DC + 3)
122
#define SPR_DCBWR       (SPRGROUP_DC + 4)
123
#define SPR_DCBLR       (SPRGROUP_DC + 5)
124
#define SPR_DCR_BASE(WAY)       (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
125
#define SPR_DCR_LAST(WAY)       (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
126
 
127
/* Instruction cache group */
128
#define SPR_ICCR        (SPRGROUP_IC + 0)
129
#define SPR_ICBPR       (SPRGROUP_IC + 1)
130
#define SPR_ICBIR       (SPRGROUP_IC + 2)
131
#define SPR_ICBLR       (SPRGROUP_IC + 3)
132
#define SPR_ICR_BASE(WAY)       (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
133
#define SPR_ICR_LAST(WAY)       (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
134
 
135
/* MAC group */
136
#define SPR_MACLO       (SPRGROUP_MAC + 1)
137
#define SPR_MACHI       (SPRGROUP_MAC + 2)
138
 
139
/* Debug group */
140
#define SPR_DVR(N)      (SPRGROUP_D + (N))
141
#define SPR_DCR(N)      (SPRGROUP_D + 8 + (N))
142
#define SPR_DMR1        (SPRGROUP_D + 16)
143
#define SPR_DMR2        (SPRGROUP_D + 17)
144
#define SPR_DWCR0       (SPRGROUP_D + 18)
145
#define SPR_DWCR1       (SPRGROUP_D + 19)
146
#define SPR_DSR         (SPRGROUP_D + 20)
147
#define SPR_DRR         (SPRGROUP_D + 21)
148
 
149
/* Performance counters group */
150
#define SPR_PCCR(N)     (SPRGROUP_PC + (N))
151
#define SPR_PCMR(N)     (SPRGROUP_PC + 8 + (N))
152
 
153
/* Power management group */
154
#define SPR_PMR (SPRGROUP_PM + 0)
155
 
156
/* PIC group */
157
#define SPR_PICMR (SPRGROUP_PIC + 0)
158 538 julius
#define SPR_PICPR (SPRGROUP_PIC + 1)
159 90 jeremybenn
#define SPR_PICSR (SPRGROUP_PIC + 2)
160
 
161
/* Tick Timer group */
162
#define SPR_TTMR (SPRGROUP_TT + 0)
163
#define SPR_TTCR (SPRGROUP_TT + 1)
164
 
165
/*
166
 * Bit definitions for the Version Register
167
 *
168
 */
169 233 julius
#define SPR_VR_VER      0xff000000  /* Processor version */
170
#define SPR_VR_CFG      0x00ff0000  /* Processor configuration */
171 385 jeremybenn
#define SPR_VR_RES      0x0000ffc0  /* Reserved */
172 90 jeremybenn
#define SPR_VR_REV      0x0000003f  /* Processor revision */
173
 
174 233 julius
#define SPR_VR_VER_OFF  24
175
#define SPR_VR_CFG_OFF  16
176
#define SPR_VR_REV_OFF  0
177
 
178 90 jeremybenn
/*
179
 * Bit definitions for the Unit Present Register
180
 *
181
 */
182
#define SPR_UPR_UP         0x00000001  /* UPR present */
183
#define SPR_UPR_DCP        0x00000002  /* Data cache present */
184
#define SPR_UPR_ICP        0x00000004  /* Instruction cache present */
185
#define SPR_UPR_DMP        0x00000008  /* Data MMU present */
186
#define SPR_UPR_IMP        0x00000010  /* Instruction MMU present */
187
#define SPR_UPR_MP         0x00000020  /* MAC present */
188
#define SPR_UPR_DUP        0x00000040  /* Debug unit present */
189
#define SPR_UPR_PCUP       0x00000080  /* Performance counters unit present */
190
#define SPR_UPR_PMP        0x00000100  /* Power management present */
191
#define SPR_UPR_PICP       0x00000200  /* PIC present */
192
#define SPR_UPR_TTP        0x00000400  /* Tick timer present */
193
#define SPR_UPR_RES        0x00fe0000  /* Reserved */
194
#define SPR_UPR_CUP        0xff000000  /* Context units present */
195
 
196
/*
197
 * JPB: Bit definitions for the CPU configuration register
198
 *
199
 */
200
#define SPR_CPUCFGR_NSGF   0x0000000f  /* Number of shadow GPR files */
201
#define SPR_CPUCFGR_CGF    0x00000010  /* Custom GPR file */
202
#define SPR_CPUCFGR_OB32S  0x00000020  /* ORBIS32 supported */
203
#define SPR_CPUCFGR_OB64S  0x00000040  /* ORBIS64 supported */
204
#define SPR_CPUCFGR_OF32S  0x00000080  /* ORFPX32 supported */
205
#define SPR_CPUCFGR_OF64S  0x00000100  /* ORFPX64 supported */
206
#define SPR_CPUCFGR_OV64S  0x00000200  /* ORVDX64 supported */
207
#define SPR_CPUCFGR_RES    0xfffffc00  /* Reserved */
208
 
209
/*
210
 * JPB: Bit definitions for the Debug configuration register and other
211
 * constants.
212
 *
213
 */
214
 
215
#define SPR_DCFGR_NDP      0x00000007  /* Number of matchpoints mask */
216
#define SPR_DCFGR_NDP1     0x00000000  /* One matchpoint supported */
217
#define SPR_DCFGR_NDP2     0x00000001  /* Two matchpoints supported */
218
#define SPR_DCFGR_NDP3     0x00000002  /* Three matchpoints supported */
219
#define SPR_DCFGR_NDP4     0x00000003  /* Four matchpoints supported */
220
#define SPR_DCFGR_NDP5     0x00000004  /* Five matchpoints supported */
221
#define SPR_DCFGR_NDP6     0x00000005  /* Six matchpoints supported */
222
#define SPR_DCFGR_NDP7     0x00000006  /* Seven matchpoints supported */
223
#define SPR_DCFGR_NDP8     0x00000007  /* Eight matchpoints supported */
224 233 julius
#define SPR_DCFGR_WPCI     0x00000008  /* Watchpoint counters implemented */
225 90 jeremybenn
 
226
#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \
227
                               2 == n ? SPR_DCFGR_NDP2 : \
228
                               3 == n ? SPR_DCFGR_NDP3 : \
229
                               4 == n ? SPR_DCFGR_NDP4 : \
230
                               5 == n ? SPR_DCFGR_NDP5 : \
231
                               6 == n ? SPR_DCFGR_NDP6 : \
232
                               7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8)
233
#define MAX_MATCHPOINTS  8
234
#define MAX_WATCHPOINTS  (MAX_MATCHPOINTS + 2)
235
 
236
/*
237
 * Bit definitions for the Supervision Register
238
 *
239
 */
240
#define SPR_SR_SM          0x00000001  /* Supervisor Mode */
241
#define SPR_SR_TEE         0x00000002  /* Tick timer Exception Enable */
242
#define SPR_SR_IEE         0x00000004  /* Interrupt Exception Enable */
243
#define SPR_SR_DCE         0x00000008  /* Data Cache Enable */
244
#define SPR_SR_ICE         0x00000010  /* Instruction Cache Enable */
245
#define SPR_SR_DME         0x00000020  /* Data MMU Enable */
246
#define SPR_SR_IME         0x00000040  /* Instruction MMU Enable */
247
#define SPR_SR_LEE         0x00000080  /* Little Endian Enable */
248
#define SPR_SR_CE          0x00000100  /* CID Enable */
249
#define SPR_SR_F           0x00000200  /* Condition Flag */
250
#define SPR_SR_CY          0x00000400  /* Carry flag */
251
#define SPR_SR_OV          0x00000800  /* Overflow flag */
252
#define SPR_SR_OVE         0x00001000  /* Overflow flag Exception */
253
#define SPR_SR_DSX         0x00002000  /* Delay Slot Exception */
254
#define SPR_SR_EPH         0x00004000  /* Exception Prefix High */
255
#define SPR_SR_FO          0x00008000  /* Fixed one */
256
#define SPR_SR_SUMRA       0x00010000  /* Supervisor SPR read access */
257
#define SPR_SR_RES         0x0ffe0000  /* Reserved */
258
#define SPR_SR_CID         0xf0000000  /* Context ID */
259
 
260
/*
261
 * Bit definitions for the Data MMU Control Register
262
 *
263
 */
264
#define SPR_DMMUCR_P2S     0x0000003e  /* Level 2 Page Size */
265
#define SPR_DMMUCR_P1S     0x000007c0  /* Level 1 Page Size */
266
#define SPR_DMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
267
#define SPR_DMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
268
 
269
/*
270
 * Bit definitions for the Instruction MMU Control Register
271
 *
272
 */
273
#define SPR_IMMUCR_P2S     0x0000003e  /* Level 2 Page Size */
274
#define SPR_IMMUCR_P1S     0x000007c0  /* Level 1 Page Size */
275
#define SPR_IMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
276
#define SPR_IMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
277
 
278
/*
279
 * Bit definitions for the Data TLB Match Register
280
 *
281
 */
282
#define SPR_DTLBMR_V       0x00000001  /* Valid */
283
#define SPR_DTLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
284
#define SPR_DTLBMR_CID     0x0000003c  /* Context ID */
285
#define SPR_DTLBMR_LRU     0x000000c0  /* Least Recently Used */
286 538 julius
#define SPR_DTLBMR_VPN     0xffffe000  /* Virtual Page Number */
287 90 jeremybenn
 
288
/*
289
 * Bit definitions for the Data TLB Translate Register
290
 *
291
 */
292
#define SPR_DTLBTR_CC      0x00000001  /* Cache Coherency */
293
#define SPR_DTLBTR_CI      0x00000002  /* Cache Inhibit */
294
#define SPR_DTLBTR_WBC     0x00000004  /* Write-Back Cache */
295
#define SPR_DTLBTR_WOM     0x00000008  /* Weakly-Ordered Memory */
296
#define SPR_DTLBTR_A       0x00000010  /* Accessed */
297
#define SPR_DTLBTR_D       0x00000020  /* Dirty */
298
#define SPR_DTLBTR_URE     0x00000040  /* User Read Enable */
299
#define SPR_DTLBTR_UWE     0x00000080  /* User Write Enable */
300
#define SPR_DTLBTR_SRE     0x00000100  /* Supervisor Read Enable */
301
#define SPR_DTLBTR_SWE     0x00000200  /* Supervisor Write Enable */
302 538 julius
#define SPR_DTLBTR_PPN     0xffffe000  /* Physical Page Number */
303 90 jeremybenn
 
304
/*
305
 * Bit definitions for the Instruction TLB Match Register
306
 *
307
 */
308
#define SPR_ITLBMR_V       0x00000001  /* Valid */
309
#define SPR_ITLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
310
#define SPR_ITLBMR_CID     0x0000003c  /* Context ID */
311
#define SPR_ITLBMR_LRU     0x000000c0  /* Least Recently Used */
312 538 julius
#define SPR_ITLBMR_VPN     0xffffe000  /* Virtual Page Number */
313 90 jeremybenn
 
314
/*
315
 * Bit definitions for the Instruction TLB Translate Register
316
 *
317
 */
318
#define SPR_ITLBTR_CC      0x00000001  /* Cache Coherency */
319
#define SPR_ITLBTR_CI      0x00000002  /* Cache Inhibit */
320
#define SPR_ITLBTR_WBC     0x00000004  /* Write-Back Cache */
321
#define SPR_ITLBTR_WOM     0x00000008  /* Weakly-Ordered Memory */
322
#define SPR_ITLBTR_A       0x00000010  /* Accessed */
323
#define SPR_ITLBTR_D       0x00000020  /* Dirty */
324
#define SPR_ITLBTR_SXE     0x00000040  /* User Read Enable */
325
#define SPR_ITLBTR_UXE     0x00000080  /* User Write Enable */
326 538 julius
#define SPR_ITLBTR_PPN     0xffffe000  /* Physical Page Number */
327 90 jeremybenn
 
328
/*
329
 * Bit definitions for Data Cache Control register
330
 *
331
 */
332
#define SPR_DCCR_EW        0x000000ff  /* Enable ways */
333
 
334
/*
335
 * Bit definitions for Insn Cache Control register
336
 *
337
 */
338
#define SPR_ICCR_EW        0x000000ff  /* Enable ways */
339
 
340
/*
341
 * Bit definitions for Data Cache Configuration Register
342
 *
343
 */
344
 
345
#define SPR_DCCFGR_NCW          0x00000007
346
#define SPR_DCCFGR_NCS          0x00000078
347
#define SPR_DCCFGR_CBS          0x00000080
348
#define SPR_DCCFGR_CWS          0x00000100
349
#define SPR_DCCFGR_CCRI         0x00000200
350
#define SPR_DCCFGR_CBIRI        0x00000400
351
#define SPR_DCCFGR_CBPRI        0x00000800
352
#define SPR_DCCFGR_CBLRI        0x00001000
353
#define SPR_DCCFGR_CBFRI        0x00002000
354
#define SPR_DCCFGR_CBWBRI       0x00004000
355
 
356 233 julius
#define SPR_DCCFGR_NCW_OFF      0
357
#define SPR_DCCFGR_NCS_OFF      3
358
#define SPR_DCCFGR_CBS_OFF      7
359
 
360 90 jeremybenn
/*
361
 * Bit definitions for Instruction Cache Configuration Register
362
 *
363
 */
364
#define SPR_ICCFGR_NCW          0x00000007
365
#define SPR_ICCFGR_NCS          0x00000078
366
#define SPR_ICCFGR_CBS          0x00000080
367
#define SPR_ICCFGR_CCRI         0x00000200
368
#define SPR_ICCFGR_CBIRI        0x00000400
369
#define SPR_ICCFGR_CBPRI        0x00000800
370
#define SPR_ICCFGR_CBLRI        0x00001000
371
 
372 233 julius
#define SPR_ICCFGR_NCW_OFF      0
373
#define SPR_ICCFGR_NCS_OFF      3
374
#define SPR_ICCFGR_CBS_OFF      7
375
 
376 90 jeremybenn
/*
377
 * Bit definitions for Data MMU Configuration Register
378
 *
379
 */
380
 
381
#define SPR_DMMUCFGR_NTW        0x00000003
382
#define SPR_DMMUCFGR_NTS        0x0000001C
383
#define SPR_DMMUCFGR_NAE        0x000000E0
384
#define SPR_DMMUCFGR_CRI        0x00000100
385
#define SPR_DMMUCFGR_PRI        0x00000200
386
#define SPR_DMMUCFGR_TEIRI      0x00000400
387
#define SPR_DMMUCFGR_HTR        0x00000800
388
 
389 233 julius
#define SPR_DMMUCFGR_NTW_OFF    0
390
#define SPR_DMMUCFGR_NTS_OFF    2
391
 
392 90 jeremybenn
/*
393
 * Bit definitions for Instruction MMU Configuration Register
394
 *
395
 */
396
 
397
#define SPR_IMMUCFGR_NTW        0x00000003
398
#define SPR_IMMUCFGR_NTS        0x0000001C
399
#define SPR_IMMUCFGR_NAE        0x000000E0
400
#define SPR_IMMUCFGR_CRI        0x00000100
401
#define SPR_IMMUCFGR_PRI        0x00000200
402
#define SPR_IMMUCFGR_TEIRI      0x00000400
403
#define SPR_IMMUCFGR_HTR        0x00000800
404
 
405 233 julius
#define SPR_IMMUCFGR_NTW_OFF    0
406
#define SPR_IMMUCFGR_NTS_OFF    2
407
 
408 90 jeremybenn
/*
409
 * Bit definitions for Debug Control registers
410
 *
411
 */
412
#define SPR_DCR_DP      0x00000001  /* DVR/DCR present */
413
#define SPR_DCR_CC      0x0000000e  /* Compare condition */
414
#define SPR_DCR_SC      0x00000010  /* Signed compare */
415
#define SPR_DCR_CT      0x000000e0  /* Compare to */
416
 
417
/* Bit results with SPR_DCR_CC mask */
418
#define SPR_DCR_CC_MASKED 0x00000000
419
#define SPR_DCR_CC_EQUAL  0x00000002
420
#define SPR_DCR_CC_LESS   0x00000004
421
#define SPR_DCR_CC_LESSE  0x00000006
422
#define SPR_DCR_CC_GREAT  0x00000008
423
#define SPR_DCR_CC_GREATE 0x0000000a
424
#define SPR_DCR_CC_NEQUAL 0x0000000c
425
 
426
/* Bit results with SPR_DCR_CT mask */
427
#define SPR_DCR_CT_DISABLED 0x00000000
428
#define SPR_DCR_CT_IFEA     0x00000020
429
#define SPR_DCR_CT_LEA      0x00000040
430
#define SPR_DCR_CT_SEA      0x00000060
431
#define SPR_DCR_CT_LD       0x00000080
432
#define SPR_DCR_CT_SD       0x000000a0
433
#define SPR_DCR_CT_LSEA     0x000000c0
434
#define SPR_DCR_CT_LSD      0x000000e0
435
/* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */
436
 
437
/*
438
 * Bit definitions for Debug Mode 1 register
439
 *
440
 */
441
#define SPR_DMR1_CW       0x000fffff  /* Chain register pair data */
442
#define SPR_DMR1_CW0_AND  0x00000001
443
#define SPR_DMR1_CW0_OR   0x00000002
444
#define SPR_DMR1_CW0      (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR)
445
#define SPR_DMR1_CW1_AND  0x00000004
446
#define SPR_DMR1_CW1_OR   0x00000008
447
#define SPR_DMR1_CW1      (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR)
448
#define SPR_DMR1_CW2_AND  0x00000010
449
#define SPR_DMR1_CW2_OR   0x00000020
450
#define SPR_DMR1_CW2      (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR)
451
#define SPR_DMR1_CW3_AND  0x00000040
452
#define SPR_DMR1_CW3_OR   0x00000080
453
#define SPR_DMR1_CW3      (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR)
454
#define SPR_DMR1_CW4_AND  0x00000100
455
#define SPR_DMR1_CW4_OR   0x00000200
456
#define SPR_DMR1_CW4      (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR)
457
#define SPR_DMR1_CW5_AND  0x00000400
458
#define SPR_DMR1_CW5_OR   0x00000800
459
#define SPR_DMR1_CW5      (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)
460
#define SPR_DMR1_CW6_AND  0x00001000
461
#define SPR_DMR1_CW6_OR   0x00002000
462
#define SPR_DMR1_CW6      (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR)
463
#define SPR_DMR1_CW7_AND  0x00004000
464
#define SPR_DMR1_CW7_OR   0x00008000
465
#define SPR_DMR1_CW7      (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR)
466
#define SPR_DMR1_CW8_AND  0x00010000
467
#define SPR_DMR1_CW8_OR   0x00020000
468
#define SPR_DMR1_CW8      (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR)
469
#define SPR_DMR1_CW9_AND  0x00040000
470
#define SPR_DMR1_CW9_OR   0x00080000
471
#define SPR_DMR1_CW9      (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR)
472
#define SPR_DMR1_RES1      0x00300000  /* Reserved */
473
#define SPR_DMR1_ST       0x00400000  /* Single-step trace*/
474
#define SPR_DMR1_BT       0x00800000  /* Branch trace */
475
#define SPR_DMR1_RES2     0xff000000  /* Reserved */
476
 
477
/*
478
 * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
479
 *
480
 */
481
#define SPR_DMR2_WCE0      0x00000001  /* Watchpoint counter 0 enable */
482
#define SPR_DMR2_WCE1      0x00000002  /* Watchpoint counter 0 enable */
483
#define SPR_DMR2_AWTC      0x00000ffc  /* Assign watchpoints to counters */
484
#define SPR_DMR2_AWTC_OFF           2  /* Bit offset to AWTC field */
485
#define SPR_DMR2_WGB       0x003ff000  /* Watchpoints generating breakpoint */
486
#define SPR_DMR2_WGB_OFF           12  /* Bit offset to WGB field */
487
#define SPR_DMR2_WBS       0xffc00000  /* JPB: Watchpoint status */
488
#define SPR_DMR2_WBS_OFF           22  /* Bit offset to WBS field */
489
 
490
/*
491
 * Bit definitions for Debug watchpoint counter registers
492
 *
493
 */
494
#define SPR_DWCR_COUNT      0x0000ffff  /* Count */
495
#define SPR_DWCR_MATCH      0xffff0000  /* Match */
496
#define SPR_DWCR_MATCH_OFF          16  /* Match bit offset */
497
 
498
/*
499
 * Bit definitions for Debug stop register
500
 *
501
 */
502
#define SPR_DSR_RSTE    0x00000001  /* Reset exception */
503
#define SPR_DSR_BUSEE   0x00000002  /* Bus error exception */
504
#define SPR_DSR_DPFE    0x00000004  /* Data Page Fault exception */
505
#define SPR_DSR_IPFE    0x00000008  /* Insn Page Fault exception */
506
#define SPR_DSR_TTE     0x00000010  /* Tick Timer exception */
507
#define SPR_DSR_AE      0x00000020  /* Alignment exception */
508
#define SPR_DSR_IIE     0x00000040  /* Illegal Instruction exception */
509
#define SPR_DSR_IE      0x00000080  /* Interrupt exception */
510
#define SPR_DSR_DME     0x00000100  /* DTLB miss exception */
511
#define SPR_DSR_IME     0x00000200  /* ITLB miss exception */
512
#define SPR_DSR_RE      0x00000400  /* Range exception */
513
#define SPR_DSR_SCE     0x00000800  /* System call exception */
514 233 julius
#define SPR_DSR_FPE     0x00001000  /* Floating Point Exception */
515 90 jeremybenn
#define SPR_DSR_TE      0x00002000  /* Trap exception */
516
 
517
/*
518
 * Bit definitions for Debug reason register
519
 *
520
 */
521
#define SPR_DRR_RSTE    0x00000001  /* Reset exception */
522
#define SPR_DRR_BUSEE   0x00000002  /* Bus error exception */
523
#define SPR_DRR_DPFE    0x00000004  /* Data Page Fault exception */
524
#define SPR_DRR_IPFE    0x00000008  /* Insn Page Fault exception */
525
#define SPR_DRR_TTE     0x00000010  /* Tick Timer exception */
526
#define SPR_DRR_AE      0x00000020  /* Alignment exception */
527
#define SPR_DRR_IIE     0x00000040  /* Illegal Instruction exception */
528
#define SPR_DRR_IE      0x00000080  /* Interrupt exception */
529
#define SPR_DRR_DME     0x00000100  /* DTLB miss exception */
530
#define SPR_DRR_IME     0x00000200  /* ITLB miss exception */
531
#define SPR_DRR_RE      0x00000400  /* Range exception */
532
#define SPR_DRR_SCE     0x00000800  /* System call exception */
533 233 julius
#define SPR_DRR_FPE     0x00001000  /* Floating Point Exception */
534
#define SPR_DRR_TE      0x00002000  /* Trap exception */
535 90 jeremybenn
 
536
/*
537
 * Bit definitions for Performance counters mode registers
538
 *
539
 */
540
#define SPR_PCMR_CP     0x00000001  /* Counter present */
541
#define SPR_PCMR_UMRA   0x00000002  /* User mode read access */
542
#define SPR_PCMR_CISM   0x00000004  /* Count in supervisor mode */
543
#define SPR_PCMR_CIUM   0x00000008  /* Count in user mode */
544
#define SPR_PCMR_LA     0x00000010  /* Load access event */
545
#define SPR_PCMR_SA     0x00000020  /* Store access event */
546
#define SPR_PCMR_IF     0x00000040  /* Instruction fetch event*/
547
#define SPR_PCMR_DCM    0x00000080  /* Data cache miss event */
548
#define SPR_PCMR_ICM    0x00000100  /* Insn cache miss event */
549
#define SPR_PCMR_IFS    0x00000200  /* Insn fetch stall event */
550
#define SPR_PCMR_LSUS   0x00000400  /* LSU stall event */
551
#define SPR_PCMR_BS     0x00000800  /* Branch stall event */
552
#define SPR_PCMR_DTLBM  0x00001000  /* DTLB miss event */
553
#define SPR_PCMR_ITLBM  0x00002000  /* ITLB miss event */
554
#define SPR_PCMR_DDS    0x00004000  /* Data dependency stall event */
555
#define SPR_PCMR_WPE    0x03ff8000  /* Watchpoint events */
556
 
557
/*
558
 * Bit definitions for the Power management register
559
 *
560
 */
561
#define SPR_PMR_SDF     0x0000000f  /* Slow down factor */
562
#define SPR_PMR_DME     0x00000010  /* Doze mode enable */
563
#define SPR_PMR_SME     0x00000020  /* Sleep mode enable */
564
#define SPR_PMR_DCGE    0x00000040  /* Dynamic clock gating enable */
565
#define SPR_PMR_SUME    0x00000080  /* Suspend mode enable */
566
 
567
/*
568
 * Bit definitions for PICMR
569
 *
570
 */
571
#define SPR_PICMR_IUM   0xfffffffc  /* Interrupt unmask */
572
 
573
/*
574 538 julius
 * Bit definitions for PICPR
575
 *
576
 */
577
#define SPR_PICPR_IPRIO 0xfffffffc  /* Interrupt priority */
578
 
579
/*
580 90 jeremybenn
 * Bit definitions for PICSR
581
 *
582
 */
583
#define SPR_PICSR_IS    0xffffffff  /* Interrupt status */
584
 
585
/*
586
 * Bit definitions for Tick Timer Control Register
587
 *
588
 */
589 538 julius
#define SPR_TTCR_CNT    0xffffffff  /* Count, time period */
590
#define SPR_TTMR_TP     0x0fffffff  /* Time period */
591 90 jeremybenn
#define SPR_TTMR_IP     0x10000000  /* Interrupt Pending */
592
#define SPR_TTMR_IE     0x20000000  /* Interrupt Enable */
593
#define SPR_TTMR_DI     0x00000000  /* Disabled */
594
#define SPR_TTMR_RT     0x40000000  /* Restart tick */
595
#define SPR_TTMR_SR     0x80000000  /* Single run */
596
#define SPR_TTMR_CR     0xc0000000  /* Continuous run */
597
#define SPR_TTMR_M      0xc0000000  /* Tick mode */
598
 
599
/*
600 233 julius
 * Bit definitions for the FP Control Status Register
601
 *
602
 */
603
#define SPR_FPCSR_FPEE  0x00000001  /* Floating Point Exception Enable */
604
#define SPR_FPCSR_RM    0x00000006  /* Rounding Mode */
605
#define SPR_FPCSR_OVF   0x00000008  /* Overflow Flag */
606
#define SPR_FPCSR_UNF   0x00000010  /* Underflow Flag */
607
#define SPR_FPCSR_SNF   0x00000020  /* SNAN Flag */
608
#define SPR_FPCSR_QNF   0x00000040  /* QNAN Flag */
609
#define SPR_FPCSR_ZF    0x00000080  /* Zero Flag */
610
#define SPR_FPCSR_IXF   0x00000100  /* Inexact Flag */
611
#define SPR_FPCSR_IVF   0x00000200  /* Invalid Flag */
612
#define SPR_FPCSR_INF   0x00000400  /* Infinity Flag */
613
#define SPR_FPCSR_DZF   0x00000800  /* Divide By Zero Flag */
614
#define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \
615
                        SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF |  \
616
                        SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF)
617
 
618
#define FPCSR_RM_RN (0<<1)
619
#define FPCSR_RM_RZ (1<<1)
620
#define FPCSR_RM_RIP (2<<1)
621
#define FPCSR_RM_RIN (3<<1)
622
 
623
/*
624 90 jeremybenn
 * l.nop constants
625
 *
626
 */
627
#define NOP_NOP          0x0000      /* Normal nop instruction */
628
#define NOP_EXIT         0x0001      /* End of simulation */
629
#define NOP_REPORT       0x0002      /* Simple report */
630 233 julius
/*#define NOP_PRINTF       0x0003       Simprintf instruction (obsolete)*/
631 90 jeremybenn
#define NOP_PUTC         0x0004      /* JPB: Simputc instruction */
632
#define NOP_CNT_RESET    0x0005      /* Reset statistics counters */
633
#define NOP_GET_TICKS    0x0006      /* JPB: Get # ticks running */
634
#define NOP_GET_PS       0x0007      /* JPB: Get picosecs/cycle */
635 460 jeremybenn
#define NOP_TRACE_ON     0x0008      /* Turn on tracing */
636
#define NOP_TRACE_OFF    0x0009      /* Turn off tracing */
637 483 jeremybenn
#define NOP_RANDOM       0x000a      /* Return 4 random bytes */
638
#define NOP_OR1KSIM      0x000b      /* Return non-zero if this is Or1ksim */
639 233 julius
 
640
#endif  /* SPR_DEFS__H */

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