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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [support/] [spr-defs.h] - Blame information for rev 214

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1 90 jeremybenn
/* spr_defs.h -- Defines OR1K architecture specific special-purpose registers
2
 
3
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4
   Copyright (C) 2008 Embecosm Limited
5
 
6
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
7
 
8
   This file is part of OpenRISC 1000 Architectural Simulator.
9
 
10
   This program is free software; you can redistribute it and/or modify it
11
   under the terms of the GNU General Public License as published by the Free
12
   Software Foundation; either version 3 of the License, or (at your option)
13
   any later version.
14
 
15
   This program is distributed in the hope that it will be useful, but WITHOUT
16
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18
   more details.
19
 
20
   You should have received a copy of the GNU General Public License along
21
   with this program.  If not, see <http://www.gnu.org/licenses/>. */
22
 
23
 
24
/* Definition of special-purpose registers (SPRs). This is just a copy of
25
   cpu/or1k/spr_defs.h. It really should not be duplicated here. */
26
 
27
#define MAX_GRPS (32)
28
#define MAX_SPRS_PER_GRP_BITS (11)
29
#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
30
#define MAX_SPRS (0x10000)
31
 
32
/* Base addresses for the groups */
33
#define SPRGROUP_SYS    (0<< MAX_SPRS_PER_GRP_BITS)
34
#define SPRGROUP_DMMU   (1<< MAX_SPRS_PER_GRP_BITS)
35
#define SPRGROUP_IMMU   (2<< MAX_SPRS_PER_GRP_BITS)
36
#define SPRGROUP_DC     (3<< MAX_SPRS_PER_GRP_BITS)
37
#define SPRGROUP_IC     (4<< MAX_SPRS_PER_GRP_BITS)
38
#define SPRGROUP_MAC    (5<< MAX_SPRS_PER_GRP_BITS)
39
#define SPRGROUP_D      (6<< MAX_SPRS_PER_GRP_BITS)
40
#define SPRGROUP_PC     (7<< MAX_SPRS_PER_GRP_BITS)
41
#define SPRGROUP_PM     (8<< MAX_SPRS_PER_GRP_BITS)
42
#define SPRGROUP_PIC    (9<< MAX_SPRS_PER_GRP_BITS)
43
#define SPRGROUP_TT     (10<< MAX_SPRS_PER_GRP_BITS)
44
 
45
/* System control and status group */
46
#define SPR_VR          (SPRGROUP_SYS + 0)
47
#define SPR_UPR         (SPRGROUP_SYS + 1)
48
#define SPR_CPUCFGR     (SPRGROUP_SYS + 2)
49
#define SPR_DMMUCFGR    (SPRGROUP_SYS + 3)
50
#define SPR_IMMUCFGR    (SPRGROUP_SYS + 4)
51
#define SPR_DCCFGR      (SPRGROUP_SYS + 5)
52
#define SPR_ICCFGR      (SPRGROUP_SYS + 6)
53
#define SPR_DCFGR       (SPRGROUP_SYS + 7)
54
#define SPR_PCCFGR      (SPRGROUP_SYS + 8)
55
#define SPR_NPC         (SPRGROUP_SYS + 16)  /* CZ 21/06/01 */
56
#define SPR_SR          (SPRGROUP_SYS + 17)  /* CZ 21/06/01 */
57
#define SPR_PPC         (SPRGROUP_SYS + 18)  /* CZ 21/06/01 */
58
#define SPR_EPCR_BASE   (SPRGROUP_SYS + 32)  /* CZ 21/06/01 */
59
#define SPR_EPCR_LAST   (SPRGROUP_SYS + 47)  /* CZ 21/06/01 */
60
#define SPR_EEAR_BASE   (SPRGROUP_SYS + 48)
61
#define SPR_EEAR_LAST   (SPRGROUP_SYS + 63)
62
#define SPR_ESR_BASE    (SPRGROUP_SYS + 64)
63
#define SPR_ESR_LAST    (SPRGROUP_SYS + 79)
64
 
65
/* Data MMU group */
66
#define SPR_DMMUCR      (SPRGROUP_DMMU + 0)
67
#define SPR_DTLBMR_BASE(WAY)    (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
68
#define SPR_DTLBMR_LAST(WAY)    (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
69
#define SPR_DTLBTR_BASE(WAY)    (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
70
#define SPR_DTLBTR_LAST(WAY)    (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
71
 
72
/* Instruction MMU group */
73
#define SPR_IMMUCR      (SPRGROUP_IMMU + 0)
74
#define SPR_ITLBMR_BASE(WAY)    (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
75
#define SPR_ITLBMR_LAST(WAY)    (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
76
#define SPR_ITLBTR_BASE(WAY)    (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
77
#define SPR_ITLBTR_LAST(WAY)    (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
78
 
79
/* Data cache group */
80
#define SPR_DCCR        (SPRGROUP_DC + 0)
81
#define SPR_DCBPR       (SPRGROUP_DC + 1)
82
#define SPR_DCBFR       (SPRGROUP_DC + 2)
83
#define SPR_DCBIR       (SPRGROUP_DC + 3)
84
#define SPR_DCBWR       (SPRGROUP_DC + 4)
85
#define SPR_DCBLR       (SPRGROUP_DC + 5)
86
#define SPR_DCR_BASE(WAY)       (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
87
#define SPR_DCR_LAST(WAY)       (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
88
 
89
/* Instruction cache group */
90
#define SPR_ICCR        (SPRGROUP_IC + 0)
91
#define SPR_ICBPR       (SPRGROUP_IC + 1)
92
#define SPR_ICBIR       (SPRGROUP_IC + 2)
93
#define SPR_ICBLR       (SPRGROUP_IC + 3)
94
#define SPR_ICR_BASE(WAY)       (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
95
#define SPR_ICR_LAST(WAY)       (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
96
 
97
/* MAC group */
98
#define SPR_MACLO       (SPRGROUP_MAC + 1)
99
#define SPR_MACHI       (SPRGROUP_MAC + 2)
100
 
101
/* Debug group */
102
#define SPR_DVR(N)      (SPRGROUP_D + (N))
103
#define SPR_DCR(N)      (SPRGROUP_D + 8 + (N))
104
#define SPR_DMR1        (SPRGROUP_D + 16)
105
#define SPR_DMR2        (SPRGROUP_D + 17)
106
#define SPR_DWCR0       (SPRGROUP_D + 18)
107
#define SPR_DWCR1       (SPRGROUP_D + 19)
108
#define SPR_DSR         (SPRGROUP_D + 20)
109
#define SPR_DRR         (SPRGROUP_D + 21)
110
 
111
/* Performance counters group */
112
#define SPR_PCCR(N)     (SPRGROUP_PC + (N))
113
#define SPR_PCMR(N)     (SPRGROUP_PC + 8 + (N))
114
 
115
/* Power management group */
116
#define SPR_PMR (SPRGROUP_PM + 0)
117
 
118
/* PIC group */
119
#define SPR_PICMR (SPRGROUP_PIC + 0)
120
#define SPR_PICPR (SPRGROUP_PIC + 1)
121
#define SPR_PICSR (SPRGROUP_PIC + 2)
122
 
123
/* Tick Timer group */
124
#define SPR_TTMR (SPRGROUP_TT + 0)
125
#define SPR_TTCR (SPRGROUP_TT + 1)
126
 
127
/*
128
 * Bit definitions for the Version Register
129
 *
130
 */
131
#define SPR_VR_VER      0xffff0000  /* Processor version */
132
#define SPR_VR_REV      0x0000003f  /* Processor revision */
133
 
134
/*
135
 * Bit definitions for the Unit Present Register
136
 *
137
 */
138
#define SPR_UPR_UP         0x00000001  /* UPR present */
139
#define SPR_UPR_DCP        0x00000002  /* Data cache present */
140
#define SPR_UPR_ICP        0x00000004  /* Instruction cache present */
141
#define SPR_UPR_DMP        0x00000008  /* Data MMU present */
142
#define SPR_UPR_IMP        0x00000010  /* Instruction MMU present */
143
#define SPR_UPR_MP         0x00000020  /* MAC present */
144
#define SPR_UPR_DUP        0x00000040  /* Debug unit present */
145
#define SPR_UPR_PCUP       0x00000080  /* Performance counters unit present */
146
#define SPR_UPR_PMP        0x00000100  /* Power management present */
147
#define SPR_UPR_PICP       0x00000200  /* PIC present */
148
#define SPR_UPR_TTP        0x00000400  /* Tick timer present */
149
#define SPR_UPR_RES        0x00fe0000  /* Reserved */
150
#define SPR_UPR_CUP        0xff000000  /* Context units present */
151
 
152
/*
153
 * JPB: Bit definitions for the CPU configuration register
154
 *
155
 */
156
#define SPR_CPUCFGR_NSGF   0x0000000f  /* Number of shadow GPR files */
157
#define SPR_CPUCFGR_CGF    0x00000010  /* Custom GPR file */
158
#define SPR_CPUCFGR_OB32S  0x00000020  /* ORBIS32 supported */
159
#define SPR_CPUCFGR_OB64S  0x00000040  /* ORBIS64 supported */
160
#define SPR_CPUCFGR_OF32S  0x00000080  /* ORFPX32 supported */
161
#define SPR_CPUCFGR_OF64S  0x00000100  /* ORFPX64 supported */
162
#define SPR_CPUCFGR_OV64S  0x00000200  /* ORVDX64 supported */
163
#define SPR_CPUCFGR_RES    0xfffffc00  /* Reserved */
164
 
165
/*
166
 * JPB: Bit definitions for the Debug configuration register and other
167
 * constants.
168
 *
169
 */
170
 
171
#define SPR_DCFGR_NDP      0x00000007  /* Number of matchpoints mask */
172
#define SPR_DCFGR_NDP1     0x00000000  /* One matchpoint supported */
173
#define SPR_DCFGR_NDP2     0x00000001  /* Two matchpoints supported */
174
#define SPR_DCFGR_NDP3     0x00000002  /* Three matchpoints supported */
175
#define SPR_DCFGR_NDP4     0x00000003  /* Four matchpoints supported */
176
#define SPR_DCFGR_NDP5     0x00000004  /* Five matchpoints supported */
177
#define SPR_DCFGR_NDP6     0x00000005  /* Six matchpoints supported */
178
#define SPR_DCFGR_NDP7     0x00000006  /* Seven matchpoints supported */
179
#define SPR_DCFGR_NDP8     0x00000007  /* Eight matchpoints supported */
180
#define SPR_DCFGR_WPCI     0x00000080  /* Watchpoint counters implemented */
181
 
182
#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \
183
                               2 == n ? SPR_DCFGR_NDP2 : \
184
                               3 == n ? SPR_DCFGR_NDP3 : \
185
                               4 == n ? SPR_DCFGR_NDP4 : \
186
                               5 == n ? SPR_DCFGR_NDP5 : \
187
                               6 == n ? SPR_DCFGR_NDP6 : \
188
                               7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8)
189
#define MAX_MATCHPOINTS  8
190
#define MAX_WATCHPOINTS  (MAX_MATCHPOINTS + 2)
191
 
192
/*
193
 * Bit definitions for the Supervision Register
194
 *
195
 */
196
#define SPR_SR_SM          0x00000001  /* Supervisor Mode */
197
#define SPR_SR_TEE         0x00000002  /* Tick timer Exception Enable */
198
#define SPR_SR_IEE         0x00000004  /* Interrupt Exception Enable */
199
#define SPR_SR_DCE         0x00000008  /* Data Cache Enable */
200
#define SPR_SR_ICE         0x00000010  /* Instruction Cache Enable */
201
#define SPR_SR_DME         0x00000020  /* Data MMU Enable */
202
#define SPR_SR_IME         0x00000040  /* Instruction MMU Enable */
203
#define SPR_SR_LEE         0x00000080  /* Little Endian Enable */
204
#define SPR_SR_CE          0x00000100  /* CID Enable */
205
#define SPR_SR_F           0x00000200  /* Condition Flag */
206
#define SPR_SR_CY          0x00000400  /* Carry flag */
207
#define SPR_SR_OV          0x00000800  /* Overflow flag */
208
#define SPR_SR_OVE         0x00001000  /* Overflow flag Exception */
209
#define SPR_SR_DSX         0x00002000  /* Delay Slot Exception */
210
#define SPR_SR_EPH         0x00004000  /* Exception Prefix High */
211
#define SPR_SR_FO          0x00008000  /* Fixed one */
212
#define SPR_SR_SUMRA       0x00010000  /* Supervisor SPR read access */
213
#define SPR_SR_RES         0x0ffe0000  /* Reserved */
214
#define SPR_SR_CID         0xf0000000  /* Context ID */
215
 
216
/*
217
 * Bit definitions for the Data MMU Control Register
218
 *
219
 */
220
#define SPR_DMMUCR_P2S     0x0000003e  /* Level 2 Page Size */
221
#define SPR_DMMUCR_P1S     0x000007c0  /* Level 1 Page Size */
222
#define SPR_DMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
223
#define SPR_DMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
224
 
225
/*
226
 * Bit definitions for the Instruction MMU Control Register
227
 *
228
 */
229
#define SPR_IMMUCR_P2S     0x0000003e  /* Level 2 Page Size */
230
#define SPR_IMMUCR_P1S     0x000007c0  /* Level 1 Page Size */
231
#define SPR_IMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
232
#define SPR_IMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
233
 
234
/*
235
 * Bit definitions for the Data TLB Match Register
236
 *
237
 */
238
#define SPR_DTLBMR_V       0x00000001  /* Valid */
239
#define SPR_DTLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
240
#define SPR_DTLBMR_CID     0x0000003c  /* Context ID */
241
#define SPR_DTLBMR_LRU     0x000000c0  /* Least Recently Used */
242
#define SPR_DTLBMR_VPN     0xfffff000  /* Virtual Page Number */
243
 
244
/*
245
 * Bit definitions for the Data TLB Translate Register
246
 *
247
 */
248
#define SPR_DTLBTR_CC      0x00000001  /* Cache Coherency */
249
#define SPR_DTLBTR_CI      0x00000002  /* Cache Inhibit */
250
#define SPR_DTLBTR_WBC     0x00000004  /* Write-Back Cache */
251
#define SPR_DTLBTR_WOM     0x00000008  /* Weakly-Ordered Memory */
252
#define SPR_DTLBTR_A       0x00000010  /* Accessed */
253
#define SPR_DTLBTR_D       0x00000020  /* Dirty */
254
#define SPR_DTLBTR_URE     0x00000040  /* User Read Enable */
255
#define SPR_DTLBTR_UWE     0x00000080  /* User Write Enable */
256
#define SPR_DTLBTR_SRE     0x00000100  /* Supervisor Read Enable */
257
#define SPR_DTLBTR_SWE     0x00000200  /* Supervisor Write Enable */
258
#define SPR_DTLBTR_PPN     0xfffff000  /* Physical Page Number */
259
 
260
/*
261
 * Bit definitions for the Instruction TLB Match Register
262
 *
263
 */
264
#define SPR_ITLBMR_V       0x00000001  /* Valid */
265
#define SPR_ITLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
266
#define SPR_ITLBMR_CID     0x0000003c  /* Context ID */
267
#define SPR_ITLBMR_LRU     0x000000c0  /* Least Recently Used */
268
#define SPR_ITLBMR_VPN     0xfffff000  /* Virtual Page Number */
269
 
270
/*
271
 * Bit definitions for the Instruction TLB Translate Register
272
 *
273
 */
274
#define SPR_ITLBTR_CC      0x00000001  /* Cache Coherency */
275
#define SPR_ITLBTR_CI      0x00000002  /* Cache Inhibit */
276
#define SPR_ITLBTR_WBC     0x00000004  /* Write-Back Cache */
277
#define SPR_ITLBTR_WOM     0x00000008  /* Weakly-Ordered Memory */
278
#define SPR_ITLBTR_A       0x00000010  /* Accessed */
279
#define SPR_ITLBTR_D       0x00000020  /* Dirty */
280
#define SPR_ITLBTR_SXE     0x00000040  /* User Read Enable */
281
#define SPR_ITLBTR_UXE     0x00000080  /* User Write Enable */
282
#define SPR_ITLBTR_PPN     0xfffff000  /* Physical Page Number */
283
 
284
/*
285
 * Bit definitions for Data Cache Control register
286
 *
287
 */
288
#define SPR_DCCR_EW        0x000000ff  /* Enable ways */
289
 
290
/*
291
 * Bit definitions for Insn Cache Control register
292
 *
293
 */
294
#define SPR_ICCR_EW        0x000000ff  /* Enable ways */
295
 
296
/*
297
 * Bit definitions for Data Cache Configuration Register
298
 *
299
 */
300
 
301
#define SPR_DCCFGR_NCW          0x00000007
302
#define SPR_DCCFGR_NCS          0x00000078
303
#define SPR_DCCFGR_CBS          0x00000080
304
#define SPR_DCCFGR_CWS          0x00000100
305
#define SPR_DCCFGR_CCRI         0x00000200
306
#define SPR_DCCFGR_CBIRI        0x00000400
307
#define SPR_DCCFGR_CBPRI        0x00000800
308
#define SPR_DCCFGR_CBLRI        0x00001000
309
#define SPR_DCCFGR_CBFRI        0x00002000
310
#define SPR_DCCFGR_CBWBRI       0x00004000
311
 
312
/*
313
 * Bit definitions for Instruction Cache Configuration Register
314
 *
315
 */
316
#define SPR_ICCFGR_NCW          0x00000007
317
#define SPR_ICCFGR_NCS          0x00000078
318
#define SPR_ICCFGR_CBS          0x00000080
319
#define SPR_ICCFGR_CCRI         0x00000200
320
#define SPR_ICCFGR_CBIRI        0x00000400
321
#define SPR_ICCFGR_CBPRI        0x00000800
322
#define SPR_ICCFGR_CBLRI        0x00001000
323
 
324
/*
325
 * Bit definitions for Data MMU Configuration Register
326
 *
327
 */
328
 
329
#define SPR_DMMUCFGR_NTW        0x00000003
330
#define SPR_DMMUCFGR_NTS        0x0000001C
331
#define SPR_DMMUCFGR_NAE        0x000000E0
332
#define SPR_DMMUCFGR_CRI        0x00000100
333
#define SPR_DMMUCFGR_PRI        0x00000200
334
#define SPR_DMMUCFGR_TEIRI      0x00000400
335
#define SPR_DMMUCFGR_HTR        0x00000800
336
 
337
/*
338
 * Bit definitions for Instruction MMU Configuration Register
339
 *
340
 */
341
 
342
#define SPR_IMMUCFGR_NTW        0x00000003
343
#define SPR_IMMUCFGR_NTS        0x0000001C
344
#define SPR_IMMUCFGR_NAE        0x000000E0
345
#define SPR_IMMUCFGR_CRI        0x00000100
346
#define SPR_IMMUCFGR_PRI        0x00000200
347
#define SPR_IMMUCFGR_TEIRI      0x00000400
348
#define SPR_IMMUCFGR_HTR        0x00000800
349
 
350
/*
351
 * Bit definitions for Debug Control registers
352
 *
353
 */
354
#define SPR_DCR_DP      0x00000001  /* DVR/DCR present */
355
#define SPR_DCR_CC      0x0000000e  /* Compare condition */
356
#define SPR_DCR_SC      0x00000010  /* Signed compare */
357
#define SPR_DCR_CT      0x000000e0  /* Compare to */
358
 
359
/* Bit results with SPR_DCR_CC mask */
360
#define SPR_DCR_CC_MASKED 0x00000000
361
#define SPR_DCR_CC_EQUAL  0x00000002
362
#define SPR_DCR_CC_LESS   0x00000004
363
#define SPR_DCR_CC_LESSE  0x00000006
364
#define SPR_DCR_CC_GREAT  0x00000008
365
#define SPR_DCR_CC_GREATE 0x0000000a
366
#define SPR_DCR_CC_NEQUAL 0x0000000c
367
 
368
/* Bit results with SPR_DCR_CT mask */
369
#define SPR_DCR_CT_DISABLED 0x00000000
370
#define SPR_DCR_CT_IFEA     0x00000020
371
#define SPR_DCR_CT_LEA      0x00000040
372
#define SPR_DCR_CT_SEA      0x00000060
373
#define SPR_DCR_CT_LD       0x00000080
374
#define SPR_DCR_CT_SD       0x000000a0
375
#define SPR_DCR_CT_LSEA     0x000000c0
376
#define SPR_DCR_CT_LSD      0x000000e0
377
/* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */
378
 
379
/*
380
 * Bit definitions for Debug Mode 1 register
381
 *
382
 */
383
#define SPR_DMR1_CW       0x000fffff  /* Chain register pair data */
384
#define SPR_DMR1_CW0_AND  0x00000001
385
#define SPR_DMR1_CW0_OR   0x00000002
386
#define SPR_DMR1_CW0      (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR)
387
#define SPR_DMR1_CW1_AND  0x00000004
388
#define SPR_DMR1_CW1_OR   0x00000008
389
#define SPR_DMR1_CW1      (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR)
390
#define SPR_DMR1_CW2_AND  0x00000010
391
#define SPR_DMR1_CW2_OR   0x00000020
392
#define SPR_DMR1_CW2      (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR)
393
#define SPR_DMR1_CW3_AND  0x00000040
394
#define SPR_DMR1_CW3_OR   0x00000080
395
#define SPR_DMR1_CW3      (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR)
396
#define SPR_DMR1_CW4_AND  0x00000100
397
#define SPR_DMR1_CW4_OR   0x00000200
398
#define SPR_DMR1_CW4      (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR)
399
#define SPR_DMR1_CW5_AND  0x00000400
400
#define SPR_DMR1_CW5_OR   0x00000800
401
#define SPR_DMR1_CW5      (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)
402
#define SPR_DMR1_CW6_AND  0x00001000
403
#define SPR_DMR1_CW6_OR   0x00002000
404
#define SPR_DMR1_CW6      (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR)
405
#define SPR_DMR1_CW7_AND  0x00004000
406
#define SPR_DMR1_CW7_OR   0x00008000
407
#define SPR_DMR1_CW7      (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR)
408
#define SPR_DMR1_CW8_AND  0x00010000
409
#define SPR_DMR1_CW8_OR   0x00020000
410
#define SPR_DMR1_CW8      (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR)
411
#define SPR_DMR1_CW9_AND  0x00040000
412
#define SPR_DMR1_CW9_OR   0x00080000
413
#define SPR_DMR1_CW9      (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR)
414
#define SPR_DMR1_RES1      0x00300000  /* Reserved */
415
#define SPR_DMR1_ST       0x00400000  /* Single-step trace*/
416
#define SPR_DMR1_BT       0x00800000  /* Branch trace */
417
#define SPR_DMR1_RES2     0xff000000  /* Reserved */
418
 
419
/*
420
 * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
421
 *
422
 */
423
#define SPR_DMR2_WCE0      0x00000001  /* Watchpoint counter 0 enable */
424
#define SPR_DMR2_WCE1      0x00000002  /* Watchpoint counter 0 enable */
425
#define SPR_DMR2_AWTC      0x00000ffc  /* Assign watchpoints to counters */
426
#define SPR_DMR2_AWTC_OFF           2  /* Bit offset to AWTC field */
427
#define SPR_DMR2_WGB       0x003ff000  /* Watchpoints generating breakpoint */
428
#define SPR_DMR2_WGB_OFF           12  /* Bit offset to WGB field */
429
#define SPR_DMR2_WBS       0xffc00000  /* JPB: Watchpoint status */
430
#define SPR_DMR2_WBS_OFF           22  /* Bit offset to WBS field */
431
 
432
/*
433
 * Bit definitions for Debug watchpoint counter registers
434
 *
435
 */
436
#define SPR_DWCR_COUNT      0x0000ffff  /* Count */
437
#define SPR_DWCR_MATCH      0xffff0000  /* Match */
438
#define SPR_DWCR_MATCH_OFF          16  /* Match bit offset */
439
 
440
/*
441
 * Bit definitions for Debug stop register
442
 *
443
 */
444
#define SPR_DSR_RSTE    0x00000001  /* Reset exception */
445
#define SPR_DSR_BUSEE   0x00000002  /* Bus error exception */
446
#define SPR_DSR_DPFE    0x00000004  /* Data Page Fault exception */
447
#define SPR_DSR_IPFE    0x00000008  /* Insn Page Fault exception */
448
#define SPR_DSR_TTE     0x00000010  /* Tick Timer exception */
449
#define SPR_DSR_AE      0x00000020  /* Alignment exception */
450
#define SPR_DSR_IIE     0x00000040  /* Illegal Instruction exception */
451
#define SPR_DSR_IE      0x00000080  /* Interrupt exception */
452
#define SPR_DSR_DME     0x00000100  /* DTLB miss exception */
453
#define SPR_DSR_IME     0x00000200  /* ITLB miss exception */
454
#define SPR_DSR_RE      0x00000400  /* Range exception */
455
#define SPR_DSR_SCE     0x00000800  /* System call exception */
456
#define SPR_DSR_SSE     0x00001000  /* Single Step Exception */
457
#define SPR_DSR_TE      0x00002000  /* Trap exception */
458
 
459
/*
460
 * Bit definitions for Debug reason register
461
 *
462
 */
463
#define SPR_DRR_RSTE    0x00000001  /* Reset exception */
464
#define SPR_DRR_BUSEE   0x00000002  /* Bus error exception */
465
#define SPR_DRR_DPFE    0x00000004  /* Data Page Fault exception */
466
#define SPR_DRR_IPFE    0x00000008  /* Insn Page Fault exception */
467
#define SPR_DRR_TTE     0x00000010  /* Tick Timer exception */
468
#define SPR_DRR_AE      0x00000020  /* Alignment exception */
469
#define SPR_DRR_IIE     0x00000040  /* Illegal Instruction exception */
470
#define SPR_DRR_IE      0x00000080  /* Interrupt exception */
471
#define SPR_DRR_DME     0x00000100  /* DTLB miss exception */
472
#define SPR_DRR_IME     0x00000200  /* ITLB miss exception */
473
#define SPR_DRR_RE      0x00000400  /* Range exception */
474
#define SPR_DRR_SCE     0x00000800  /* System call exception */
475
#define SPR_DRR_TE      0x00001000  /* Trap exception */
476
 
477
/*
478
 * Bit definitions for Performance counters mode registers
479
 *
480
 */
481
#define SPR_PCMR_CP     0x00000001  /* Counter present */
482
#define SPR_PCMR_UMRA   0x00000002  /* User mode read access */
483
#define SPR_PCMR_CISM   0x00000004  /* Count in supervisor mode */
484
#define SPR_PCMR_CIUM   0x00000008  /* Count in user mode */
485
#define SPR_PCMR_LA     0x00000010  /* Load access event */
486
#define SPR_PCMR_SA     0x00000020  /* Store access event */
487
#define SPR_PCMR_IF     0x00000040  /* Instruction fetch event*/
488
#define SPR_PCMR_DCM    0x00000080  /* Data cache miss event */
489
#define SPR_PCMR_ICM    0x00000100  /* Insn cache miss event */
490
#define SPR_PCMR_IFS    0x00000200  /* Insn fetch stall event */
491
#define SPR_PCMR_LSUS   0x00000400  /* LSU stall event */
492
#define SPR_PCMR_BS     0x00000800  /* Branch stall event */
493
#define SPR_PCMR_DTLBM  0x00001000  /* DTLB miss event */
494
#define SPR_PCMR_ITLBM  0x00002000  /* ITLB miss event */
495
#define SPR_PCMR_DDS    0x00004000  /* Data dependency stall event */
496
#define SPR_PCMR_WPE    0x03ff8000  /* Watchpoint events */
497
 
498
/*
499
 * Bit definitions for the Power management register
500
 *
501
 */
502
#define SPR_PMR_SDF     0x0000000f  /* Slow down factor */
503
#define SPR_PMR_DME     0x00000010  /* Doze mode enable */
504
#define SPR_PMR_SME     0x00000020  /* Sleep mode enable */
505
#define SPR_PMR_DCGE    0x00000040  /* Dynamic clock gating enable */
506
#define SPR_PMR_SUME    0x00000080  /* Suspend mode enable */
507
 
508
/*
509
 * Bit definitions for PICMR
510
 *
511
 */
512
#define SPR_PICMR_IUM   0xfffffffc  /* Interrupt unmask */
513
 
514
/*
515
 * Bit definitions for PICPR
516
 *
517
 */
518
#define SPR_PICPR_IPRIO 0xfffffffc  /* Interrupt priority */
519
 
520
/*
521
 * Bit definitions for PICSR
522
 *
523
 */
524
#define SPR_PICSR_IS    0xffffffff  /* Interrupt status */
525
 
526
/*
527
 * Bit definitions for Tick Timer Control Register
528
 *
529
 */
530
#define SPR_TTCR_PERIOD 0x0fffffff  /* Time Period */
531
#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
532
#define SPR_TTMR_IP     0x10000000  /* Interrupt Pending */
533
#define SPR_TTMR_IE     0x20000000  /* Interrupt Enable */
534
#define SPR_TTMR_DI     0x00000000  /* Disabled */
535
#define SPR_TTMR_RT     0x40000000  /* Restart tick */
536
#define SPR_TTMR_SR     0x80000000  /* Single run */
537
#define SPR_TTMR_CR     0xc0000000  /* Continuous run */
538
#define SPR_TTMR_M      0xc0000000  /* Tick mode */
539
 
540
/*
541
 * l.nop constants
542
 *
543
 */
544
#define NOP_NOP          0x0000      /* Normal nop instruction */
545
#define NOP_EXIT         0x0001      /* End of simulation */
546
#define NOP_REPORT       0x0002      /* Simple report */
547
/*#define NOP_PRINTF       0x0003      Simprintf instruction now obsolete */
548
#define NOP_PUTC         0x0004      /* JPB: Simputc instruction */
549
#define NOP_CNT_RESET    0x0005      /* Reset statistics counters */
550
#define NOP_GET_TICKS    0x0006      /* JPB: Get # ticks running */
551
#define NOP_GET_PS       0x0007      /* JPB: Get picosecs/cycle */
552
#define NOP_REPORT_FIRST 0x0400      /* Report with number */
553
#define NOP_REPORT_LAST  0x03ff      /* Report with number */

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