OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [support/] [support.h] - Blame information for rev 124

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 90 jeremybenn
/* support.h Support headers for testing Or1ksim.
2
 
3
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
4
   Copyright (C) 2010 Embecosm Limited
5
 
6
   Contributor Damjan Lampret <lampret@opencores.org>
7
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
8
 
9
   This file is part of OpenRISC 1000 Architectural Simulator.
10
 
11
   This program is free software; you can redistribute it and/or modify it
12
   under the terms of the GNU General Public License as published by the Free
13
   Software Foundation; either version 3 of the License, or (at your option)
14
   any later version.
15
 
16
   This program is distributed in the hope that it will be useful, but WITHOUT
17
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
   more details.
20
 
21
   You should have received a copy of the GNU General Public License along
22
   with this program.  If not, see <http:  www.gnu.org/licenses/>.  */
23
 
24
/* ----------------------------------------------------------------------------
25
   This code is commented throughout for use with Doxygen.
26
   --------------------------------------------------------------------------*/
27
 
28
/* This file should is included in each C test. It calls main () function and
29
   add support for basic functions */
30
 
31
#ifndef SUPPORT_H
32
#define SUPPORT_H
33
 
34
#include <stdarg.h>
35
#include <stddef.h>
36
#include <limits.h>
37
 
38
 
39
/*! Convenience macros for accessing memory. */
40
#define REG8(add)  *((volatile unsigned char *)  (add))
41
#define REG16(add) *((volatile unsigned short *) (add))
42
#define REG32(add) *((volatile unsigned long *)  (add))
43
 
44
/* Start function */
45
extern void  reset ();
46
 
47
/* Return a value by making a syscall */
48
extern void exit (int i) __attribute__ ((__noreturn__));
49
 
50
/* Version of putchar that works with Or1ksim */
51
extern int  putchar (int  c);
52
 
53
/* Version of puts that works with Or1ksim */
54
extern int  puts (const char *str);
55
 
56
/* Restricted version of printf that works with Or1ksim */
57
extern int  printf (const char *fmt,
58
                    ...);
59
 
60
/* Prints out a value */
61
extern void  report (unsigned long int  value);
62
 
63
/* Read the simulator timer */
64
extern unsigned long int  read_timer ();
65
 
66
/* For writing into SPR. */
67
extern void  mtspr (unsigned long int  spr,
68
                    unsigned long int  value);
69
 
70
/* For reading SPR. */
71
extern unsigned long int  mfspr (unsigned long int  spr);
72
 
73
/* memcpy clone */
74
extern void *memcpy (void *__restrict         __dest,
75
                     __const void *__restrict __src,
76
                     size_t                   __n);
77
 
78
/* Externally used exception handlers */
79
extern unsigned long int  excpt_buserr;
80
extern unsigned long int  excpt_dpfault;
81
extern unsigned long int  excpt_ipfault;
82
extern unsigned long int  excpt_tick;
83
extern unsigned long int  excpt_align;
84
extern unsigned long int  excpt_illinsn;
85
extern unsigned long int  excpt_int;
86
extern unsigned long int  excpt_dtlbmiss;
87
extern unsigned long int  excpt_itlbmiss;
88
extern unsigned long int  excpt_range;
89
extern unsigned long int  excpt_syscall;
90
extern unsigned long int  excpt_break;
91
extern unsigned long int  excpt_trap;
92
 
93
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.