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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [uos/] [except-or32.S] - Blame information for rev 352

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1 90 jeremybenn
/* except-or32.S  Microkernel exception handler for Or1ksim
2
 
3
   Copyright (C) 2000 Damjan Lampret
4
   Copyright (C) 2010 Embecosm Limited
5
 
6
   Contributor Damjan Lampret 
7
   Contributor Jeremy Bennett 
8
 
9
   This file is part of OpenRISC 1000 Architectural Simulator.
10
 
11
   This program is free software; you can redistribute it and/or modify it
12
   under the terms of the GNU General Public License as published by the Free
13
   Software Foundation; either version 3 of the License, or (at your option)
14
   any later version.
15
 
16
   This program is distributed in the hope that it will be useful, but WITHOUT
17
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19
   more details.
20
 
21
   You should have received a copy of the GNU General Public License along
22
   with this program.  If not, see .  */
23
 
24
/* ----------------------------------------------------------------------------
25
   This code is commented throughout for use with Doxygen.
26
   --------------------------------------------------------------------------*/
27
 
28
        /* This file is part of test microkernel for OpenRISC 1000. */
29
 
30
#include "spr-defs.h"
31
#include "board.h"
32
 
33
#define MC_CSR          (0x00)
34
#define MC_POC          (0x04)
35
#define MC_BA_MASK      (0x08)
36
#define MC_CSC(i)       (0x10 + (i) * 8)
37
#define MC_TMS(i)       (0x14 + (i) * 8)
38
 
39
 
40
/*
41
 * Context is saved to area pointed by pointer in R3. Original
42
 * R3 is at memory location 0 and task's PC is at memory location 4.
43
 */
44
#define SAVEREGS                                        \
45
        l.lwz   r3,0(r3);                               \
46
        l.sw    4(r3),r1;                               \
47
        l.sw    8(r3),r2;                               \
48
        l.lwz   r2,0(r0);       /* saving original r3*/ \
49
        l.sw    12(r3),r2;                              \
50
        l.sw    16(r3),r4;                              \
51
        l.sw    20(r3),r5;                              \
52
        l.sw    24(r3),r6;                              \
53
        l.sw    28(r3),r7;                              \
54
        l.sw    32(r3),r8;                              \
55
        l.sw    36(r3),r9;                              \
56
        l.sw    40(r3),r10;                             \
57
        l.sw    44(r3),r11;                             \
58
        l.sw    48(r3),r12;                             \
59
        l.sw    52(r3),r13;                             \
60
        l.sw    56(r3),r14;                             \
61
        l.sw    60(r3),r15;                             \
62
        l.sw    64(r3),r16;                             \
63
        l.sw    68(r3),r17;                             \
64
        l.sw    72(r3),r18;                             \
65
        l.sw    76(r3),r19;                             \
66
        l.sw    80(r3),r20;                             \
67
        l.sw    84(r3),r21;                             \
68
        l.sw    88(r3),r22;                             \
69
        l.sw    92(r3),r23;                             \
70
        l.sw    96(r3),r24;                             \
71
        l.sw    100(r3),r25;                            \
72
        l.sw    104(r3),r26;                            \
73
        l.sw    108(r3),r27;                            \
74
        l.sw    112(r3),r28;                            \
75
        l.sw    116(r3),r29;                            \
76
        l.sw    120(r3),r30;                            \
77
        l.sw    124(r3),r31;                            \
78
        l.lwz   r2,4(r0);       /* saving original PC*/ \
79
        l.sw    0(r3),r2;                               \
80
                                                        \
81
        l.mfspr r2,r0,SPR_ESR_BASE;                             \
82
        l.sw    128(r3),r2      /* saving SR */
83
 
84
/*
85
 * Pointer to context is in R3. All registers are loaded and execution is
86
 * transfered to the loaded context's task
87
 */
88
#define LOADREGS_N_GO                           \
89
        l.lwz   r3,0(r3);                       \
90
        l.lwz   r2,0(r3);       /* prepare PC*/ \
91
        l.mtspr r0,r2,SPR_EPCR_BASE;            \
92
                                                \
93
        l.lwz   r2,128(r3);     /* prepare SR*/ \
94
        l.mtspr r0,r2,SPR_ESR_BASE;                     \
95
                                                \
96
        l.lwz   r1,4(r3);                       \
97
        l.lwz   r2,8(r3);                       \
98
        l.lwz   r4,16(r3);                      \
99
        l.lwz   r5,20(r3);                      \
100
        l.lwz   r6,24(r3);                      \
101
        l.lwz   r7,28(r3);                      \
102
        l.lwz   r8,32(r3);                      \
103
        l.lwz   r9,36(r3);                      \
104
        l.lwz   r10,40(r3);                     \
105
        l.lwz   r11,44(r3);                     \
106
        l.lwz   r12,48(r3);                     \
107
        l.lwz   r13,52(r3);                     \
108
        l.lwz   r14,56(r3);                     \
109
        l.lwz   r15,60(r3);                     \
110
        l.lwz   r16,64(r3);                     \
111
        l.lwz   r17,68(r3);                     \
112
        l.lwz   r18,72(r3);                     \
113
        l.lwz   r19,76(r3);                     \
114
        l.lwz   r20,80(r3);                     \
115
        l.lwz   r21,84(r3);                     \
116
        l.lwz   r22,88(r3);                     \
117
        l.lwz   r23,92(r3);                     \
118
        l.lwz   r24,96(r3);                     \
119
        l.lwz   r25,100(r3);                    \
120
        l.lwz   r26,104(r3);                    \
121
        l.lwz   r27,108(r3);                    \
122
        l.lwz   r28,112(r3);                    \
123
        l.lwz   r29,116(r3);                    \
124
        l.lwz   r30,120(r3);                    \
125
        l.lwz   r31,124(r3);                    \
126
                                                \
127
        l.lwz   r3,12(r3);      /* prepare r3*/ \
128
                                                \
129
        l.rfe;                  /* Call task */ \
130
        l.nop
131
 
132
/*
133
 * All registers are loaded from save area.
134
 */
135
#define LOADREGS                                \
136
        l.lwz   r3,0(r3);                       \
137
        l.lwz   r2,0(r3);       /* prepare PC*/ \
138
        l.mtspr r0,r2,SPR_EPCR_BASE;            \
139
                                                \
140
        l.lwz   r2,128(r3);     /* prepare SR*/ \
141
        l.mtspr r0,r2,SPR_ESR_BASE;                     \
142
                                                \
143
        l.lwz   r1,4(r3);                       \
144
        l.lwz   r2,8(r3);                       \
145
        l.lwz   r4,16(r3);                      \
146
        l.lwz   r5,20(r3);                      \
147
        l.lwz   r6,24(r3);                      \
148
        l.lwz   r7,28(r3);                      \
149
        l.lwz   r8,32(r3);                      \
150
        l.lwz   r9,36(r3);                      \
151
        l.lwz   r10,40(r3);                     \
152
        l.lwz   r11,44(r3);                     \
153
        l.lwz   r12,48(r3);                     \
154
        l.lwz   r13,52(r3);                     \
155
        l.lwz   r14,56(r3);                     \
156
        l.lwz   r15,60(r3);                     \
157
        l.lwz   r16,64(r3);                     \
158
        l.lwz   r17,68(r3);                     \
159
        l.lwz   r18,72(r3);                     \
160
        l.lwz   r19,76(r3);                     \
161
        l.lwz   r20,80(r3);                     \
162
        l.lwz   r21,84(r3);                     \
163
        l.lwz   r22,88(r3);                     \
164
        l.lwz   r23,92(r3);                     \
165
        l.lwz   r24,96(r3);                     \
166
        l.lwz   r25,100(r3);                    \
167
        l.lwz   r26,104(r3);                    \
168
        l.lwz   r27,108(r3);                    \
169
        l.lwz   r28,112(r3);                    \
170
        l.lwz   r29,116(r3);                    \
171
        l.lwz   r30,120(r3);                    \
172
        l.lwz   r31,124(r3);                    \
173
                                                \
174
        l.lwz   r3,12(r3);      /* prepare r3*/
175
 
176
/*
177
 * Set new PC in saved context
178
 */
179
#define SET_CONTEXTPC(AREA,SUBROUTINE,TMPREG)   \
180
        l.lwz   AREA,0(AREA);                   \
181
        l.movhi TMPREG,hi(SUBROUTINE);          \
182
        l.addi  TMPREG,r0,lo(SUBROUTINE);       \
183
        l.sw    0(AREA),TMPREG;
184
 
185
/*
186
 * Printf via or1ksim hook
187
 */
188
#if KERNEL_OUTPUT
189
#define PRINTF(REG,STR)                         \
190
        l.movhi REG,hi(STR);                    \
191
        l.addi  REG,r0,lo(STR);                 \
192
        l.nop   NOP_PRINTF
193
#else
194
#define PRINTF(REG,STR)
195
#endif
196
 
197
/*
198
 * Reset Exception handler
199
 */
200
.org 0x100
201 346 jeremybenn
reset_vector:
202 90 jeremybenn
 
203
  l.movhi r3,hi(MC_BASE_ADDR)
204
  l.ori   r3,r3,lo(MC_BASE_ADDR)
205
 
206
  l.addi  r4,r3,MC_CSC(0)
207
  l.movhi r5,hi(FLASH_BASE_ADDR)
208
  l.srai  r5,r5,6
209
  l.ori   r5,r5,0x0025
210
  l.sw    0(r4),r5
211
 
212
  l.addi  r4,r3,MC_TMS(0)
213
  l.movhi r5,hi(FLASH_TMS_VAL)
214
  l.ori   r5,r5,lo(FLASH_TMS_VAL)
215
  l.sw    0(r4),r5
216
 
217
  l.addi  r4,r3,MC_BA_MASK
218
  l.addi  r5,r0,MC_MASK_VAL
219
  l.sw    0(r4),r5
220
 
221
  l.addi  r4,r3,MC_CSR
222
  l.movhi r5,hi(MC_CSR_VAL)
223
  l.ori   r5,r5,lo(MC_CSR_VAL)
224
  l.sw    0(r4),r5
225
 
226
  l.addi  r4,r3,MC_TMS(1)
227
  l.movhi r5,hi(SDRAM_TMS_VAL)
228
  l.ori   r5,r5,lo(SDRAM_TMS_VAL)
229
  l.sw    0(r4),r5
230
 
231
  l.addi  r4,r3,MC_CSC(1)
232
  l.movhi r5,hi(SDRAM_BASE_ADDR)
233
  l.srai  r5,r5,6
234
  l.ori   r5,r5,0x0411
235
  l.sw    0(r4),r5
236
 
237
  l.jr    r9
238
  l.nop
239
 
240
  /* Copy data section */
241
  l.movhi r3,hi(_src_beg)
242
  l.ori   r3,r3,lo(_src_beg)
243
  l.addi  r4,r0,0x200
244
  l.movhi r5,hi(_except_end)
245
  l.ori   r5,r5,lo(_except_end)
246
  l.movhi r6,hi(_except_beg)
247
  l.ori   r6,r6,lo(_except_beg)
248
  l.sub   r5,r6,r5
249
1:
250
  l.lwz   r6,0(r3)
251
  l.sw    0(r4),r6
252
  l.addi  r3,r3,4
253
  l.addi  r4,r4,4
254
  l.addi  r5,r5,-4
255
  l.sfgtsi r5,0
256
  l.bf    1b
257
  l.nop
258
 
259
  l.movhi r4,hi(_dst_beg)
260
  l.ori   r4,r4,lo(_dst_beg)
261
  l.movhi r5,hi(_dst_end)
262
  l.ori   r5,r5,lo(_dst_end)
263
  l.sub   r5,r5,r4
264
  l.sfeqi r5,0
265
  l.bf    2f
266
  l.nop
267
1:
268
  l.lwz   r6,0(r3)
269
  l.sw    0(r4),r6
270
  l.addi  r3,r3,4
271
  l.addi  r4,r4,4
272
  l.addi  r5,r5,-4
273
  l.sfgtsi r5,0
274
  l.bf          1b
275
  l.nop
276
 
277
2:
278
 
279
 
280 346 jeremybenn
  l.movhi r2,hi(reset)
281
  l.ori   r2,r2,lo(reset)
282 90 jeremybenn
  l.jr    r2
283
  l.nop
284
 
285
/*
286 346 jeremybenn
 * Switch to a new context pointed by task_context
287 90 jeremybenn
 */
288 346 jeremybenn
.global dispatch
289 90 jeremybenn
.align 4
290 346 jeremybenn
dispatch:
291 90 jeremybenn
        /* load user task GPRs and PC */
292 346 jeremybenn
        l.movhi r3,hi(task_context)
293
        l.addi  r3,r0,lo(task_context)
294 90 jeremybenn
        LOADREGS_N_GO
295
 
296
.section .except, "ax"
297
 
298
/*
299
 * Bus Error Exception handler
300
 */
301
.org 0x0200
302 346 jeremybenn
buserr:
303 90 jeremybenn
        l.nop
304
        l.sw    0(r0),r3        /* Save r3 */
305 346 jeremybenn
        PRINTF(r3, buserr_str)
306
hang:
307
        l.j     hang
308 90 jeremybenn
        l.nop
309
 
310 346 jeremybenn
buserr_str:
311 90 jeremybenn
        .ascii  "Bus error exception.\n\000"
312
 
313
/*
314
 * External Interrupt Exception handler
315
 */
316
.org 0x800
317 346 jeremybenn
extint:
318 90 jeremybenn
        l.nop
319
        l.sw    0(r0),r3        /* Save r3 */
320 346 jeremybenn
        PRINTF(r3,extint_str)
321 90 jeremybenn
        l.mfspr r3,r0,SPR_EPCR_BASE     /* Get EPCR */
322
        l.sw    4(r0),r3        /* and save it */
323
 
324
        /* now save user task context */
325 346 jeremybenn
        l.movhi r3,hi(task_context)
326
        l.addi  r3,r0,lo(task_context)
327 90 jeremybenn
        SAVEREGS
328
 
329
        /* set kernel context's PC to kernel's scheduler */
330 346 jeremybenn
        l.movhi r3,hi(kernel_context)
331
        l.addi  r3,r0,lo(kernel_context)
332
        SET_CONTEXTPC(r3,int_main,r4)
333 90 jeremybenn
 
334
        /* load kernel context */
335 346 jeremybenn
        l.movhi r3,hi(kernel_context)
336
        l.addi  r3,r0,lo(kernel_context)
337 90 jeremybenn
        LOADREGS
338
 
339 346 jeremybenn
        l.movhi r3,hi(int_main)
340
        l.addi  r3,r0,lo(int_main)
341 90 jeremybenn
        l.jr    r3
342
        l.nop
343
 
344 346 jeremybenn
extint_str:
345 90 jeremybenn
        .ascii  "External interrupt exception.\n\000"
346
 
347
/*
348
 * System Call Exception handler
349
 */
350
.org 0x0c00
351 346 jeremybenn
syscall:
352 90 jeremybenn
        l.nop
353
        l.sw    0(r0),r3        /* Save r3 */
354 346 jeremybenn
        PRINTF(r3,syscall_str)
355 90 jeremybenn
        l.mfspr r3,r0,SPR_EPCR_BASE     /* Get EPCR */
356
        l.addi  r3,r3,4         /* increment because EPCR instruction was already executed */
357
        l.sw    4(r0),r3        /* and save it */
358
 
359
        /* now save user task context */
360 346 jeremybenn
        l.movhi r3,hi(task_context)
361
        l.addi  r3,r0,lo(task_context)
362 90 jeremybenn
        SAVEREGS
363
 
364
        /* set kernel context's PC to kernel's syscall entry */
365 346 jeremybenn
        l.movhi r3,hi(kernel_context)
366
        l.addi  r3,r0,lo(kernel_context)
367
        SET_CONTEXTPC(r3,kernel_syscall,r4)
368 90 jeremybenn
 
369
        /* load kernel context */
370 346 jeremybenn
        l.movhi r3,hi(kernel_context)
371
        l.addi  r3,r0,lo(kernel_context)
372 90 jeremybenn
        LOADREGS_N_GO
373
 
374 346 jeremybenn
syscall_str:
375 90 jeremybenn
        .ascii  "System call exception.\n\000"
376
 
377
 

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