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/* except-or32.S  Microkernel exception handler for Or1ksim
 
   Copyright (C) 2000 Damjan Lampret
   Copyright (C) 2010 Embecosm Limited
 
   Contributor Damjan Lampret 
   Contributor Jeremy Bennett 
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see .  */
 
/* ----------------------------------------------------------------------------
   This code is commented throughout for use with Doxygen.
   --------------------------------------------------------------------------*/
 
        /* This file is part of test microkernel for OpenRISC 1000. */
 
#include "spr-defs.h"
#include "board.h"
 
#define MC_CSR          (0x00)
#define MC_POC          (0x04)
#define MC_BA_MASK      (0x08)
#define MC_CSC(i)       (0x10 + (i) * 8)
#define MC_TMS(i)       (0x14 + (i) * 8)
 
 
/*
 * Context is saved to area pointed by pointer in R3. Original
 * R3 is at memory location 0 and task's PC is at memory location 4.
 */
#define SAVEREGS                                        \
        l.lwz   r3,0(r3);                               \
        l.sw    4(r3),r1;                               \
        l.sw    8(r3),r2;                               \
        l.lwz   r2,0(r0);       /* saving original r3*/ \
        l.sw    12(r3),r2;                              \
        l.sw    16(r3),r4;                              \
        l.sw    20(r3),r5;                              \
        l.sw    24(r3),r6;                              \
        l.sw    28(r3),r7;                              \
        l.sw    32(r3),r8;                              \
        l.sw    36(r3),r9;                              \
        l.sw    40(r3),r10;                             \
        l.sw    44(r3),r11;                             \
        l.sw    48(r3),r12;                             \
        l.sw    52(r3),r13;                             \
        l.sw    56(r3),r14;                             \
        l.sw    60(r3),r15;                             \
        l.sw    64(r3),r16;                             \
        l.sw    68(r3),r17;                             \
        l.sw    72(r3),r18;                             \
        l.sw    76(r3),r19;                             \
        l.sw    80(r3),r20;                             \
        l.sw    84(r3),r21;                             \
        l.sw    88(r3),r22;                             \
        l.sw    92(r3),r23;                             \
        l.sw    96(r3),r24;                             \
        l.sw    100(r3),r25;                            \
        l.sw    104(r3),r26;                            \
        l.sw    108(r3),r27;                            \
        l.sw    112(r3),r28;                            \
        l.sw    116(r3),r29;                            \
        l.sw    120(r3),r30;                            \
        l.sw    124(r3),r31;                            \
        l.lwz   r2,4(r0);       /* saving original PC*/ \
        l.sw    0(r3),r2;                               \
                                                        \
        l.mfspr r2,r0,SPR_ESR_BASE;                             \
        l.sw    128(r3),r2      /* saving SR */
 
/*
 * Pointer to context is in R3. All registers are loaded and execution is
 * transfered to the loaded context's task
 */
#define LOADREGS_N_GO                           \
        l.lwz   r3,0(r3);                       \
        l.lwz   r2,0(r3);       /* prepare PC*/ \
        l.mtspr r0,r2,SPR_EPCR_BASE;            \
                                                \
        l.lwz   r2,128(r3);     /* prepare SR*/ \
        l.mtspr r0,r2,SPR_ESR_BASE;                     \
                                                \
        l.lwz   r1,4(r3);                       \
        l.lwz   r2,8(r3);                       \
        l.lwz   r4,16(r3);                      \
        l.lwz   r5,20(r3);                      \
        l.lwz   r6,24(r3);                      \
        l.lwz   r7,28(r3);                      \
        l.lwz   r8,32(r3);                      \
        l.lwz   r9,36(r3);                      \
        l.lwz   r10,40(r3);                     \
        l.lwz   r11,44(r3);                     \
        l.lwz   r12,48(r3);                     \
        l.lwz   r13,52(r3);                     \
        l.lwz   r14,56(r3);                     \
        l.lwz   r15,60(r3);                     \
        l.lwz   r16,64(r3);                     \
        l.lwz   r17,68(r3);                     \
        l.lwz   r18,72(r3);                     \
        l.lwz   r19,76(r3);                     \
        l.lwz   r20,80(r3);                     \
        l.lwz   r21,84(r3);                     \
        l.lwz   r22,88(r3);                     \
        l.lwz   r23,92(r3);                     \
        l.lwz   r24,96(r3);                     \
        l.lwz   r25,100(r3);                    \
        l.lwz   r26,104(r3);                    \
        l.lwz   r27,108(r3);                    \
        l.lwz   r28,112(r3);                    \
        l.lwz   r29,116(r3);                    \
        l.lwz   r30,120(r3);                    \
        l.lwz   r31,124(r3);                    \
                                                \
        l.lwz   r3,12(r3);      /* prepare r3*/ \
                                                \
        l.rfe;                  /* Call task */ \
        l.nop
 
/*
 * All registers are loaded from save area.
 */
#define LOADREGS                                \
        l.lwz   r3,0(r3);                       \
        l.lwz   r2,0(r3);       /* prepare PC*/ \
        l.mtspr r0,r2,SPR_EPCR_BASE;            \
                                                \
        l.lwz   r2,128(r3);     /* prepare SR*/ \
        l.mtspr r0,r2,SPR_ESR_BASE;                     \
                                                \
        l.lwz   r1,4(r3);                       \
        l.lwz   r2,8(r3);                       \
        l.lwz   r4,16(r3);                      \
        l.lwz   r5,20(r3);                      \
        l.lwz   r6,24(r3);                      \
        l.lwz   r7,28(r3);                      \
        l.lwz   r8,32(r3);                      \
        l.lwz   r9,36(r3);                      \
        l.lwz   r10,40(r3);                     \
        l.lwz   r11,44(r3);                     \
        l.lwz   r12,48(r3);                     \
        l.lwz   r13,52(r3);                     \
        l.lwz   r14,56(r3);                     \
        l.lwz   r15,60(r3);                     \
        l.lwz   r16,64(r3);                     \
        l.lwz   r17,68(r3);                     \
        l.lwz   r18,72(r3);                     \
        l.lwz   r19,76(r3);                     \
        l.lwz   r20,80(r3);                     \
        l.lwz   r21,84(r3);                     \
        l.lwz   r22,88(r3);                     \
        l.lwz   r23,92(r3);                     \
        l.lwz   r24,96(r3);                     \
        l.lwz   r25,100(r3);                    \
        l.lwz   r26,104(r3);                    \
        l.lwz   r27,108(r3);                    \
        l.lwz   r28,112(r3);                    \
        l.lwz   r29,116(r3);                    \
        l.lwz   r30,120(r3);                    \
        l.lwz   r31,124(r3);                    \
                                                \
        l.lwz   r3,12(r3);      /* prepare r3*/
 
/*
 * Set new PC in saved context
 */
#define SET_CONTEXTPC(AREA,SUBROUTINE,TMPREG)   \
        l.lwz   AREA,0(AREA);                   \
        l.movhi TMPREG,hi(SUBROUTINE);          \
        l.addi  TMPREG,r0,lo(SUBROUTINE);       \
        l.sw    0(AREA),TMPREG;
 
/*
 * Printf via or1ksim hook
 */
#if KERNEL_OUTPUT
#define PRINTF(REG,STR)                         \
        l.movhi REG,hi(STR);                    \
        l.addi  REG,r0,lo(STR);                 \
        l.nop   NOP_PRINTF
#else
#define PRINTF(REG,STR)
#endif
 
/*
 * Reset Exception handler
 */
.org 0x100
reset_vector:
 
  // Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
  // and indeed it is not when simulating the or1200 Verilog core.
  l.andi  r0,r0,0x0
 
  l.movhi r3,hi(MC_BASE_ADDR)
  l.ori   r3,r3,lo(MC_BASE_ADDR)
 
  l.addi  r4,r3,MC_CSC(0)
  l.movhi r5,hi(FLASH_BASE_ADDR)
  l.srai  r5,r5,6
  l.ori   r5,r5,0x0025
  l.sw    0(r4),r5
 
  l.addi  r4,r3,MC_TMS(0)
  l.movhi r5,hi(FLASH_TMS_VAL)
  l.ori   r5,r5,lo(FLASH_TMS_VAL)
  l.sw    0(r4),r5
 
  l.addi  r4,r3,MC_BA_MASK
  l.addi  r5,r0,MC_MASK_VAL
  l.sw    0(r4),r5
 
  l.addi  r4,r3,MC_CSR
  l.movhi r5,hi(MC_CSR_VAL)
  l.ori   r5,r5,lo(MC_CSR_VAL)
  l.sw    0(r4),r5
 
  l.addi  r4,r3,MC_TMS(1)
  l.movhi r5,hi(SDRAM_TMS_VAL)
  l.ori   r5,r5,lo(SDRAM_TMS_VAL)
  l.sw    0(r4),r5
 
  l.addi  r4,r3,MC_CSC(1)
  l.movhi r5,hi(SDRAM_BASE_ADDR)
  l.srai  r5,r5,6
  l.ori   r5,r5,0x0411
  l.sw    0(r4),r5
 
  l.jr    r9
  l.nop
 
  /* Copy data section */
  l.movhi r3,hi(_src_beg)
  l.ori   r3,r3,lo(_src_beg)
  l.addi  r4,r0,0x200
  l.movhi r5,hi(_except_end)
  l.ori   r5,r5,lo(_except_end)
  l.movhi r6,hi(_except_beg)
  l.ori   r6,r6,lo(_except_beg)
  l.sub   r5,r6,r5
1:
  l.lwz   r6,0(r3)
  l.sw    0(r4),r6
  l.addi  r3,r3,4
  l.addi  r4,r4,4
  l.addi  r5,r5,-4
  l.sfgtsi r5,0
  l.bf    1b
  l.nop
 
  l.movhi r4,hi(_dst_beg)
  l.ori   r4,r4,lo(_dst_beg)
  l.movhi r5,hi(_dst_end)
  l.ori   r5,r5,lo(_dst_end)
  l.sub   r5,r5,r4
  l.sfeqi r5,0
  l.bf    2f
  l.nop
1:
  l.lwz   r6,0(r3)
  l.sw    0(r4),r6
  l.addi  r3,r3,4
  l.addi  r4,r4,4
  l.addi  r5,r5,-4
  l.sfgtsi r5,0
  l.bf          1b
  l.nop
 
2:
 
 
  l.movhi r2,hi(reset)
  l.ori   r2,r2,lo(reset)
  l.jr    r2
  l.nop
 
/*
 * Switch to a new context pointed by task_context
 */
.global dispatch
.align 4
dispatch:
        /* load user task GPRs and PC */
        l.movhi r3,hi(task_context)
        l.addi  r3,r0,lo(task_context)
        LOADREGS_N_GO
 
.section .except, "ax"
 
/*
 * Bus Error Exception handler
 */
.org 0x0200
buserr:
        l.nop
        l.sw    0(r0),r3        /* Save r3 */
        PRINTF(r3, buserr_str)
hang:
        l.j     hang
        l.nop
 
buserr_str:
        .ascii  "Bus error exception.\n\000"
 
/*
 * External Interrupt Exception handler
 */
.org 0x800
extint:
        l.nop
        l.sw    0(r0),r3        /* Save r3 */
        PRINTF(r3,extint_str)
        l.mfspr r3,r0,SPR_EPCR_BASE     /* Get EPCR */
        l.sw    4(r0),r3        /* and save it */
 
        /* now save user task context */
        l.movhi r3,hi(task_context)
        l.addi  r3,r0,lo(task_context)
        SAVEREGS
 
        /* set kernel context's PC to kernel's scheduler */
        l.movhi r3,hi(kernel_context)
        l.addi  r3,r0,lo(kernel_context)
        SET_CONTEXTPC(r3,int_main,r4)
 
        /* load kernel context */
        l.movhi r3,hi(kernel_context)
        l.addi  r3,r0,lo(kernel_context)
        LOADREGS
 
        l.movhi r3,hi(int_main)
        l.addi  r3,r0,lo(int_main)
        l.jr    r3
        l.nop
 
extint_str:
        .ascii  "External interrupt exception.\n\000"
 
/*
 * System Call Exception handler
 */
.org 0x0c00
syscall:
        l.nop
        l.sw    0(r0),r3        /* Save r3 */
        PRINTF(r3,syscall_str)
        l.mfspr r3,r0,SPR_EPCR_BASE     /* Get EPCR */
        l.addi  r3,r3,4         /* increment because EPCR instruction was already executed */
        l.sw    4(r0),r3        /* and save it */
 
        /* now save user task context */
        l.movhi r3,hi(task_context)
        l.addi  r3,r0,lo(task_context)
        SAVEREGS
 
        /* set kernel context's PC to kernel's syscall entry */
        l.movhi r3,hi(kernel_context)
        l.addi  r3,r0,lo(kernel_context)
        SET_CONTEXTPC(r3,kernel_syscall,r4)
 
        /* load kernel context */
        l.movhi r3,hi(kernel_context)
        l.addi  r3,r0,lo(kernel_context)
        LOADREGS_N_GO
 
syscall_str:
        .ascii  "System call exception.\n\000"
 
 

Line No.	Rev	Author	Line
1	90	jeremybenn	`/* except-or32.S Microkernel exception handler for Or1ksim`
2
3			`Copyright (C) 2000 Damjan Lampret`
4			`Copyright (C) 2010 Embecosm Limited`
5
6			`Contributor Damjan Lampret`
7			`Contributor Jeremy Bennett`
8
9			`This file is part of OpenRISC 1000 Architectural Simulator.`
10
11			`This program is free software; you can redistribute it and/or modify it`
12			`under the terms of the GNU General Public License as published by the Free`
13			`Software Foundation; either version 3 of the License, or (at your option)`
14			`any later version.`
15
16			`This program is distributed in the hope that it will be useful, but WITHOUT`
17			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
18			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
19			`more details.`
20
21			`You should have received a copy of the GNU General Public License along`
22			`with this program. If not, see . */`
23
24			`/* ----------------------------------------------------------------------------`
25			`This code is commented throughout for use with Doxygen.`
26			`--------------------------------------------------------------------------*/`
27
28			`/* This file is part of test microkernel for OpenRISC 1000. */`
29
30			`#include "spr-defs.h"`
31			`#include "board.h"`
32
33			`#define MC_CSR (0x00)`
34			`#define MC_POC (0x04)`
35			`#define MC_BA_MASK (0x08)`
36			`#define MC_CSC(i) (0x10 + (i) * 8)`
37			`#define MC_TMS(i) (0x14 + (i) * 8)`
38
39
40			`/*`
41			`* Context is saved to area pointed by pointer in R3. Original`
42			`* R3 is at memory location 0 and task's PC is at memory location 4.`
43			`*/`
44			`#define SAVEREGS \`
45			`l.lwz r3,0(r3); \`
46			`l.sw 4(r3),r1; \`
47			`l.sw 8(r3),r2; \`
48			`l.lwz r2,0(r0); /* saving original r3*/ \`
49			`l.sw 12(r3),r2; \`
50			`l.sw 16(r3),r4; \`
51			`l.sw 20(r3),r5; \`
52			`l.sw 24(r3),r6; \`
53			`l.sw 28(r3),r7; \`
54			`l.sw 32(r3),r8; \`
55			`l.sw 36(r3),r9; \`
56			`l.sw 40(r3),r10; \`
57			`l.sw 44(r3),r11; \`
58			`l.sw 48(r3),r12; \`
59			`l.sw 52(r3),r13; \`
60			`l.sw 56(r3),r14; \`
61			`l.sw 60(r3),r15; \`
62			`l.sw 64(r3),r16; \`
63			`l.sw 68(r3),r17; \`
64			`l.sw 72(r3),r18; \`
65			`l.sw 76(r3),r19; \`
66			`l.sw 80(r3),r20; \`
67			`l.sw 84(r3),r21; \`
68			`l.sw 88(r3),r22; \`
69			`l.sw 92(r3),r23; \`
70			`l.sw 96(r3),r24; \`
71			`l.sw 100(r3),r25; \`
72			`l.sw 104(r3),r26; \`
73			`l.sw 108(r3),r27; \`
74			`l.sw 112(r3),r28; \`
75			`l.sw 116(r3),r29; \`
76			`l.sw 120(r3),r30; \`
77			`l.sw 124(r3),r31; \`
78			`l.lwz r2,4(r0); /* saving original PC*/ \`
79			`l.sw 0(r3),r2; \`
80			`\`
81			`l.mfspr r2,r0,SPR_ESR_BASE; \`
82			`l.sw 128(r3),r2 /* saving SR */`
83
84			`/*`
85			`* Pointer to context is in R3. All registers are loaded and execution is`
86			`* transfered to the loaded context's task`
87			`*/`
88			`#define LOADREGS_N_GO \`
89			`l.lwz r3,0(r3); \`
90			`l.lwz r2,0(r3); /* prepare PC*/ \`
91			`l.mtspr r0,r2,SPR_EPCR_BASE; \`
92			`\`
93			`l.lwz r2,128(r3); /* prepare SR*/ \`
94			`l.mtspr r0,r2,SPR_ESR_BASE; \`
95			`\`
96			`l.lwz r1,4(r3); \`
97			`l.lwz r2,8(r3); \`
98			`l.lwz r4,16(r3); \`
99			`l.lwz r5,20(r3); \`
100			`l.lwz r6,24(r3); \`
101			`l.lwz r7,28(r3); \`
102			`l.lwz r8,32(r3); \`
103			`l.lwz r9,36(r3); \`
104			`l.lwz r10,40(r3); \`
105			`l.lwz r11,44(r3); \`
106			`l.lwz r12,48(r3); \`
107			`l.lwz r13,52(r3); \`
108			`l.lwz r14,56(r3); \`
109			`l.lwz r15,60(r3); \`
110			`l.lwz r16,64(r3); \`
111			`l.lwz r17,68(r3); \`
112			`l.lwz r18,72(r3); \`
113			`l.lwz r19,76(r3); \`
114			`l.lwz r20,80(r3); \`
115			`l.lwz r21,84(r3); \`
116			`l.lwz r22,88(r3); \`
117			`l.lwz r23,92(r3); \`
118			`l.lwz r24,96(r3); \`
119			`l.lwz r25,100(r3); \`
120			`l.lwz r26,104(r3); \`
121			`l.lwz r27,108(r3); \`
122			`l.lwz r28,112(r3); \`
123			`l.lwz r29,116(r3); \`
124			`l.lwz r30,120(r3); \`
125			`l.lwz r31,124(r3); \`
126			`\`
127			`l.lwz r3,12(r3); /* prepare r3*/ \`
128			`\`
129			`l.rfe; /* Call task */ \`
130			`l.nop`
131
132			`/*`
133			`* All registers are loaded from save area.`
134			`*/`
135			`#define LOADREGS \`
136			`l.lwz r3,0(r3); \`
137			`l.lwz r2,0(r3); /* prepare PC*/ \`
138			`l.mtspr r0,r2,SPR_EPCR_BASE; \`
139			`\`
140			`l.lwz r2,128(r3); /* prepare SR*/ \`
141			`l.mtspr r0,r2,SPR_ESR_BASE; \`
142			`\`
143			`l.lwz r1,4(r3); \`
144			`l.lwz r2,8(r3); \`
145			`l.lwz r4,16(r3); \`
146			`l.lwz r5,20(r3); \`
147			`l.lwz r6,24(r3); \`
148			`l.lwz r7,28(r3); \`
149			`l.lwz r8,32(r3); \`
150			`l.lwz r9,36(r3); \`
151			`l.lwz r10,40(r3); \`
152			`l.lwz r11,44(r3); \`
153			`l.lwz r12,48(r3); \`
154			`l.lwz r13,52(r3); \`
155			`l.lwz r14,56(r3); \`
156			`l.lwz r15,60(r3); \`
157			`l.lwz r16,64(r3); \`
158			`l.lwz r17,68(r3); \`
159			`l.lwz r18,72(r3); \`
160			`l.lwz r19,76(r3); \`
161			`l.lwz r20,80(r3); \`
162			`l.lwz r21,84(r3); \`
163			`l.lwz r22,88(r3); \`
164			`l.lwz r23,92(r3); \`
165			`l.lwz r24,96(r3); \`
166			`l.lwz r25,100(r3); \`
167			`l.lwz r26,104(r3); \`
168			`l.lwz r27,108(r3); \`
169			`l.lwz r28,112(r3); \`
170			`l.lwz r29,116(r3); \`
171			`l.lwz r30,120(r3); \`
172			`l.lwz r31,124(r3); \`
173			`\`
174			`l.lwz r3,12(r3); /* prepare r3*/`
175
176			`/*`
177			`* Set new PC in saved context`
178			`*/`
179			`#define SET_CONTEXTPC(AREA,SUBROUTINE,TMPREG) \`
180			`l.lwz AREA,0(AREA); \`
181			`l.movhi TMPREG,hi(SUBROUTINE); \`
182			`l.addi TMPREG,r0,lo(SUBROUTINE); \`
183			`l.sw 0(AREA),TMPREG;`
184
185			`/*`
186			`* Printf via or1ksim hook`
187			`*/`
188			`#if KERNEL_OUTPUT`
189			`#define PRINTF(REG,STR) \`
190			`l.movhi REG,hi(STR); \`
191			`l.addi REG,r0,lo(STR); \`
192			`l.nop NOP_PRINTF`
193			`#else`
194			`#define PRINTF(REG,STR)`
195			`#endif`
196
197			`/*`
198			`* Reset Exception handler`
199			`*/`
200			`.org 0x100`
201	346	jeremybenn	`reset_vector:`
202	90	jeremybenn
203	787	jeremybenn	`// Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,`
204			`// and indeed it is not when simulating the or1200 Verilog core.`
205			`l.andi r0,r0,0x0`
206
207	90	jeremybenn	`l.movhi r3,hi(MC_BASE_ADDR)`
208			`l.ori r3,r3,lo(MC_BASE_ADDR)`
209
210			`l.addi r4,r3,MC_CSC(0)`
211			`l.movhi r5,hi(FLASH_BASE_ADDR)`
212			`l.srai r5,r5,6`
213			`l.ori r5,r5,0x0025`
214			`l.sw 0(r4),r5`
215
216			`l.addi r4,r3,MC_TMS(0)`
217			`l.movhi r5,hi(FLASH_TMS_VAL)`
218			`l.ori r5,r5,lo(FLASH_TMS_VAL)`
219			`l.sw 0(r4),r5`
220
221			`l.addi r4,r3,MC_BA_MASK`
222			`l.addi r5,r0,MC_MASK_VAL`
223			`l.sw 0(r4),r5`
224
225			`l.addi r4,r3,MC_CSR`
226			`l.movhi r5,hi(MC_CSR_VAL)`
227			`l.ori r5,r5,lo(MC_CSR_VAL)`
228			`l.sw 0(r4),r5`
229
230			`l.addi r4,r3,MC_TMS(1)`
231			`l.movhi r5,hi(SDRAM_TMS_VAL)`
232			`l.ori r5,r5,lo(SDRAM_TMS_VAL)`
233			`l.sw 0(r4),r5`
234
235			`l.addi r4,r3,MC_CSC(1)`
236			`l.movhi r5,hi(SDRAM_BASE_ADDR)`
237			`l.srai r5,r5,6`
238			`l.ori r5,r5,0x0411`
239			`l.sw 0(r4),r5`
240
241			`l.jr r9`
242			`l.nop`
243
244			`/* Copy data section */`
245			`l.movhi r3,hi(_src_beg)`
246			`l.ori r3,r3,lo(_src_beg)`
247			`l.addi r4,r0,0x200`
248			`l.movhi r5,hi(_except_end)`
249			`l.ori r5,r5,lo(_except_end)`
250			`l.movhi r6,hi(_except_beg)`
251			`l.ori r6,r6,lo(_except_beg)`
252			`l.sub r5,r6,r5`
253			`1:`
254			`l.lwz r6,0(r3)`
255			`l.sw 0(r4),r6`
256			`l.addi r3,r3,4`
257			`l.addi r4,r4,4`
258			`l.addi r5,r5,-4`
259			`l.sfgtsi r5,0`
260			`l.bf 1b`
261			`l.nop`
262
263			`l.movhi r4,hi(_dst_beg)`
264			`l.ori r4,r4,lo(_dst_beg)`
265			`l.movhi r5,hi(_dst_end)`
266			`l.ori r5,r5,lo(_dst_end)`
267			`l.sub r5,r5,r4`
268			`l.sfeqi r5,0`
269			`l.bf 2f`
270			`l.nop`
271			`1:`
272			`l.lwz r6,0(r3)`
273			`l.sw 0(r4),r6`
274			`l.addi r3,r3,4`
275			`l.addi r4,r4,4`
276			`l.addi r5,r5,-4`
277			`l.sfgtsi r5,0`
278			`l.bf 1b`
279			`l.nop`
280
281			`2:`
282
283
284	346	jeremybenn	`l.movhi r2,hi(reset)`
285			`l.ori r2,r2,lo(reset)`
286	90	jeremybenn	`l.jr r2`
287			`l.nop`
288
289			`/*`
290	346	jeremybenn	`* Switch to a new context pointed by task_context`
291	90	jeremybenn	`*/`
292	346	jeremybenn	`.global dispatch`
293	90	jeremybenn	`.align 4`
294	346	jeremybenn	`dispatch:`
295	90	jeremybenn	`/* load user task GPRs and PC */`
296	346	jeremybenn	`l.movhi r3,hi(task_context)`
297			`l.addi r3,r0,lo(task_context)`
298	90	jeremybenn	`LOADREGS_N_GO`
299
300			`.section .except, "ax"`
301
302			`/*`
303			`* Bus Error Exception handler`
304			`*/`
305			`.org 0x0200`
306	346	jeremybenn	`buserr:`
307	90	jeremybenn	`l.nop`
308			`l.sw 0(r0),r3 /* Save r3 */`
309	346	jeremybenn	`PRINTF(r3, buserr_str)`
310			`hang:`
311			`l.j hang`
312	90	jeremybenn	`l.nop`
313
314	346	jeremybenn	`buserr_str:`
315	90	jeremybenn	`.ascii "Bus error exception.\n\000"`
316
317			`/*`
318			`* External Interrupt Exception handler`
319			`*/`
320			`.org 0x800`
321	346	jeremybenn	`extint:`
322	90	jeremybenn	`l.nop`
323			`l.sw 0(r0),r3 /* Save r3 */`
324	346	jeremybenn	`PRINTF(r3,extint_str)`
325	90	jeremybenn	`l.mfspr r3,r0,SPR_EPCR_BASE /* Get EPCR */`
326			`l.sw 4(r0),r3 /* and save it */`
327
328			`/* now save user task context */`
329	346	jeremybenn	`l.movhi r3,hi(task_context)`
330			`l.addi r3,r0,lo(task_context)`
331	90	jeremybenn	`SAVEREGS`
332
333			`/* set kernel context's PC to kernel's scheduler */`
334	346	jeremybenn	`l.movhi r3,hi(kernel_context)`
335			`l.addi r3,r0,lo(kernel_context)`
336			`SET_CONTEXTPC(r3,int_main,r4)`
337	90	jeremybenn
338			`/* load kernel context */`
339	346	jeremybenn	`l.movhi r3,hi(kernel_context)`
340			`l.addi r3,r0,lo(kernel_context)`
341	90	jeremybenn	`LOADREGS`
342
343	346	jeremybenn	`l.movhi r3,hi(int_main)`
344			`l.addi r3,r0,lo(int_main)`
345	90	jeremybenn	`l.jr r3`
346			`l.nop`
347
348	346	jeremybenn	`extint_str:`
349	90	jeremybenn	`.ascii "External interrupt exception.\n\000"`
350
351			`/*`
352			`* System Call Exception handler`
353			`*/`
354			`.org 0x0c00`
355	346	jeremybenn	`syscall:`
356	90	jeremybenn	`l.nop`
357			`l.sw 0(r0),r3 /* Save r3 */`
358	346	jeremybenn	`PRINTF(r3,syscall_str)`
359	90	jeremybenn	`l.mfspr r3,r0,SPR_EPCR_BASE /* Get EPCR */`
360			`l.addi r3,r3,4 /* increment because EPCR instruction was already executed */`
361			`l.sw 4(r0),r3 /* and save it */`
362
363			`/* now save user task context */`
364	346	jeremybenn	`l.movhi r3,hi(task_context)`
365			`l.addi r3,r0,lo(task_context)`
366	90	jeremybenn	`SAVEREGS`
367
368			`/* set kernel context's PC to kernel's syscall entry */`
369	346	jeremybenn	`l.movhi r3,hi(kernel_context)`
370			`l.addi r3,r0,lo(kernel_context)`
371			`SET_CONTEXTPC(r3,kernel_syscall,r4)`
372	90	jeremybenn
373			`/* load kernel context */`
374	346	jeremybenn	`l.movhi r3,hi(kernel_context)`
375			`l.addi r3,r0,lo(kernel_context)`
376	90	jeremybenn	`LOADREGS_N_GO`
377
378	346	jeremybenn	`syscall_str:`
379	90	jeremybenn	`.ascii "System call exception.\n\000"`
380
381

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