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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [uos/] [tick.c] - Blame information for rev 346

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1 90 jeremybenn
/* tick.c.  Microkernel tick handler for Or1ksim
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   Copyright (C) 2000 Damjan Lampret
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   Copyright (C) 2010 Embecosm Limited
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   Contributor Damjan Lampret <lampret@opencores.org>
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   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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   This file is part of OpenRISC 1000 Architectural Simulator.
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   This program is free software; you can redistribute it and/or modify it
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   under the terms of the GNU General Public License as published by the Free
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   Software Foundation; either version 3 of the License, or (at your option)
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   any later version.
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   This program is distributed in the hope that it will be useful, but WITHOUT
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   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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   more details.
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   You should have received a copy of the GNU General Public License along
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   with this program.  If not, see <http:  www.gnu.org/licenses/>.  */
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/* ----------------------------------------------------------------------------
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   This code is commented throughout for use with Doxygen.
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   --------------------------------------------------------------------------*/
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/* This file is part of test microkernel for OpenRISC 1000. */
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#include "spr-defs.h"
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#include "support.h"
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/* Tick timer period */
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unsigned long tick_period;
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/* Inform of tick interrupt */
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void (*tick_inf)();
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/* Tick interrupt routine */
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void tick_int()
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{
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  /* Call inf routine */
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  (*tick_inf)();
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  /* Set new counter period iand clear inet pending bit */
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        mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | (tick_period & SPR_TTMR_PERIOD));
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}
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/* Initialize routine */
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int tick_init(unsigned long period, void (* inf)())
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{
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  /* Save tick timer period and inform routine */
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  tick_period = period;
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  tick_inf = inf;
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  /* Set counter period, enable timer and interrupt */
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  mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | (period & SPR_TTMR_PERIOD));
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  return 0;
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}

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