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[/] [openrisc/] [trunk/] [or1ksim/] [virtex.tim] - Blame information for rev 312

Line No.	Rev	Author	Line
1	19	jeremybenn	`#`
2			`# very draft timing table for FPGA Virtex, sg -5`
3			`# size is in gates, delay in ns`
4			`#`
5			`# instruction_name size_normal size_immediate delay_normal delay_immediate`
6			`#`
7
8			`add 30. 15. 8. 4.`
9			`sub 30. 15. 8. 4.`
10			`and 5. 0. 1. 0.`
11			`or 5. 0. 1. 0.`
12			`xor 10. 2. 1. 0.5`
13			`mul 700. 200. 12. 5.`
14			`srl 100. 1. 24. 12.`
15			`sll 100. 1. 24. 12.`
16			`sra 100. 1. 24. 12.`
17
18			`lb 50. 50. 5. 5.`
19			`lh 50. 50. 5. 5.`
20			`lw 50. 50. 5. 5.`
21			`sb 50. 50. 5. 5.`
22			`sh 50. 50. 5. 5.`
23			`sw 50. 50. 5. 5.`
24
25			`sfeq 20. 10. 5. 2.`
26			`sfne 20. 10. 5. 2.`
27			`sfle 30. 10. 8. 4.`
28			`sflt 30. 10. 8. 4.`
29			`sfgt 30. 10. 8. 4.`
30			`sfge 30. 10. 8. 4.`
31			`bf 50. 50. 1. 1.`
32
33			`lrbb 60. 60. 1. 1.`
34			`cmov 15. 15. 5. 2.`
35			`reg 60. 60. 1. 1.`
36
37			`call 100. 100. 3. 3.`
38			`nop 0. 0. 0. 0.`
39
40