OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or_debug_proxy/] [includes/] [or_debug_proxy.h] - Blame information for rev 731

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 39 julius
/*$$HEADER*/
2
/******************************************************************************/
3
/*                                                                            */
4
/*                    H E A D E R   I N F O R M A T I O N                     */
5
/*                                                                            */
6
/******************************************************************************/
7
 
8
// Project Name                   : OpenRISC Debug Proxy
9
// File Name                      : or_debug_proxy.h
10
// Prepared By                    : jb
11
// Project Start                  : 2008-10-01
12
 
13
/*$$COPYRIGHT NOTICE*/
14
/******************************************************************************/
15
/*                                                                            */
16
/*                      C O P Y R I G H T   N O T I C E                       */
17
/*                                                                            */
18
/******************************************************************************/
19
/*
20
  This library is free software; you can redistribute it and/or
21
  modify it under the terms of the GNU Lesser General Public
22
  License as published by the Free Software Foundation;
23
  version 2.1 of the License, a copy of which is available from
24
  http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt.
25
 
26
  This library is distributed in the hope that it will be useful,
27
  but WITHOUT ANY WARRANTY; without even the implied warranty of
28
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
29
  Lesser General Public License for more details.
30
 
31
  You should have received a copy of the GNU Lesser General Public
32
  License along with this library; if not, write to the Free Software
33
  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
34
*/
35
 
36
/*$$CHANGE HISTORY*/
37
/******************************************************************************/
38
/*                                                                            */
39
/*                         C H A N G E  H I S T O R Y                         */
40
/*                                                                            */
41
/******************************************************************************/
42
 
43
// Date         Version Description
44
//------------------------------------------------------------------------
45
// 081101               First revision                                  jb
46
 
47
#ifndef _OR_DEBUG_PROXY_H_
48
#define _OR_DEBUG_PROXY_H_
49
 
50
#ifndef DEBUG_CMDS
51
#define DEBUG_CMDS 0  // Output the actual commands being sent to the debug unit
52
#endif
53
 
54
#ifndef DEBUG_USB_DRVR_FUNCS
55
#define DEBUG_USB_DRVR_FUNCS 0 // Generate debug output from the USB driver functions
56
#endif
57
 
58
#ifndef DEBUG_GDB_BLOCK_DATA
59
#define DEBUG_GDB_BLOCK_DATA 0  // GDB Socket Block data print out
60
#endif
61
 
62
// This one is defined sometimes in the makefile, so check first
63
#ifndef DEBUG_GDB
64 79 julius
#define DEBUG_GDB 0 // GDB RSP Debugging output enabled
65 39 julius
#endif
66
 
67
#ifndef DEBUG_GDB_DUMP_DATA
68
#define DEBUG_GDB_DUMP_DATA 0  // GDB Socket Debugging - output all data we return to GDB client
69
#endif
70
 
71
#define Boolean uint32_t
72
#define false 0
73
#define true 1
74
 
75
/* Selects crc trailer size in bits. Currently supported: 8 */
76
#define CRC_SIZE (8)
77
 
78
#include <stdint.h>
79
 
80
extern int serverPort;
81
extern int server_fd;
82
 
83
extern int vpi_fd; // should be the descriptor for our connection to the VPI server
84
 
85
extern int current_chain;
86
extern int dbg_chain;
87
 
88 529 julius
extern int no_cpu; /* Don't provide access to anything in the cpu */
89
 
90 39 julius
#define DBGCHAIN_SIZE           4 // Renamed from DC_SIZE due to definition clash with something in <windows.h> --jb 090302
91
#define DC_STATUS_SIZE    4
92
 
93
#define DC_WISHBONE       0
94
#define DC_CPU0           1
95
#define DC_CPU1           2
96
 
97 46 julius
// Defining access types for wishbone
98
#define DBG_WB_WRITE8           0
99
#define DBG_WB_WRITE16          1
100
#define DBG_WB_WRITE32          2
101
#define DBG_WB_READ8            4
102
#define DBG_WB_READ16           5
103
#define DBG_WB_READ32           6
104
 
105
// Defining access types for wishbone
106
#define DBG_CPU_WRITE            2
107
#define DBG_CPU_READ             6
108
 
109 39 julius
// Manually figure the 5-bit reversed values again if they change
110
#define DI_GO          0
111
#define DI_READ_CMD    1
112
#define DI_WRITE_CMD   2
113
#define DI_READ_CTRL   3
114
#define DI_WRITE_CTRL  4
115
 
116
#define DBG_CRC_SIZE      32
117
#define DBG_CRC_POLY      0x04c11db7
118
 
119
#define DBG_ERR_OK        0
120
#define DBG_ERR_INVALID_ENDPOINT 3
121
#define DBG_ERR_CRC       8
122
 
123
#define NUM_SOFT_RETRIES  3
124
#define NUM_HARD_RETRIES  3
125
#define NUM_ACCESS_RETRIES 10
126
 
127
/* setup connection with the target */
128
void dbg_test();
129
/* perform a reset of the debug chain (not of system!) */
130
int dbg_reset();
131
/* set instruction register of JTAG TAP */
132
int dbg_set_tap_ir(uint32_t ir);
133
/* Set "scan chain" of debug unit (NOT JTAG TAP!) */
134
int dbg_set_chain(uint32_t chain);
135 46 julius
/* read a byte from wishbone */
136
int dbg_wb_write8(uint32_t adr, uint8_t data);
137 94 julius
/* read a byte from wishbone */
138
int dbg_wb_read8(uint32_t adr, uint8_t *data);
139 39 julius
/* read a word from wishbone */
140
int dbg_wb_read32(uint32_t adr, uint32_t *data);
141
/* write a word to wishbone */
142
int dbg_wb_write32(uint32_t adr, uint32_t data);
143
/* read a block from wishbone */
144
int dbg_wb_read_block32(uint32_t adr, uint32_t *data, uint32_t len);
145
/* write a block to wishbone */
146
int dbg_wb_write_block32(uint32_t adr, uint32_t *data, uint32_t len);
147
/* read a register from cpu */
148 47 julius
int dbg_cpu0_read(uint32_t adr, uint32_t *data, uint32_t length);
149 39 julius
/* read a register from cpu module */
150
int dbg_cpu0_read_ctrl(uint32_t adr, unsigned char *data);
151
/* write a cpu register */
152 47 julius
int dbg_cpu0_write(uint32_t adr, uint32_t *data, uint32_t length);
153 39 julius
/* write a cpu module register */
154
int dbg_cpu0_write_ctrl(uint32_t adr, unsigned char data);
155
 
156
void print_usage(); // Self explanatory
157
 
158
void check(char *fn, uint32_t l, uint32_t i);
159
 
160
/* Possible errors are listed here.  */
161
enum enum_errors  /* modified <chris@asics.ws> CZ 24/05/01 */
162
{
163
  /* Codes > 0 are for system errors */
164
 
165
  ERR_NONE = 0,
166
  ERR_CRC = -1,
167
  ERR_MEM = -2,
168
  JTAG_PROXY_INVALID_COMMAND = -3,
169
  JTAG_PROXY_SERVER_TERMINATED = -4,
170
  JTAG_PROXY_NO_CONNECTION = -5,
171
  JTAG_PROXY_PROTOCOL_ERROR = -6,
172
  JTAG_PROXY_COMMAND_NOT_IMPLEMENTED = -7,
173
  JTAG_PROXY_INVALID_CHAIN = -8,
174
  JTAG_PROXY_INVALID_ADDRESS = -9,
175
  JTAG_PROXY_ACCESS_EXCEPTION = -10, /* Write to ROM */
176
  JTAG_PROXY_INVALID_LENGTH = -11,
177
  JTAG_PROXY_OUT_OF_MEMORY = -12,
178
};
179
 
180
#endif /* _OR_DEBUG_PROXY_H_ */
181
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.