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[/] [openrisc/] [trunk/] [or_debug_proxy/] [includes/] [or_debug_proxy.h] - Blame information for rev 79

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1 39 julius
/*$$HEADER*/
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/******************************************************************************/
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/*                                                                            */
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/*                    H E A D E R   I N F O R M A T I O N                     */
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/*                                                                            */
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/******************************************************************************/
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// Project Name                   : OpenRISC Debug Proxy
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// File Name                      : or_debug_proxy.h
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// Prepared By                    : jb
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// Project Start                  : 2008-10-01
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/*$$COPYRIGHT NOTICE*/
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/******************************************************************************/
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/*                                                                            */
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/*                      C O P Y R I G H T   N O T I C E                       */
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/*                                                                            */
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/******************************************************************************/
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/*
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  This library is free software; you can redistribute it and/or
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  modify it under the terms of the GNU Lesser General Public
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  License as published by the Free Software Foundation;
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  version 2.1 of the License, a copy of which is available from
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  http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt.
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  This library is distributed in the hope that it will be useful,
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  but WITHOUT ANY WARRANTY; without even the implied warranty of
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  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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  Lesser General Public License for more details.
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  You should have received a copy of the GNU Lesser General Public
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  License along with this library; if not, write to the Free Software
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  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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*/
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/*$$CHANGE HISTORY*/
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/******************************************************************************/
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/*                                                                            */
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/*                         C H A N G E  H I S T O R Y                         */
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/*                                                                            */
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/******************************************************************************/
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// Date         Version Description
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//------------------------------------------------------------------------
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// 081101               First revision                                  jb
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#ifndef _OR_DEBUG_PROXY_H_
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#define _OR_DEBUG_PROXY_H_
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#ifndef DEBUG_CMDS
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#define DEBUG_CMDS 0  // Output the actual commands being sent to the debug unit
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#endif
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#ifndef DEBUG_USB_DRVR_FUNCS
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#define DEBUG_USB_DRVR_FUNCS 0 // Generate debug output from the USB driver functions
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#endif
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#ifndef DEBUG_GDB_BLOCK_DATA
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#define DEBUG_GDB_BLOCK_DATA 0  // GDB Socket Block data print out
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#endif
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// This one is defined sometimes in the makefile, so check first
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#ifndef DEBUG_GDB
64 79 julius
#define DEBUG_GDB 0 // GDB RSP Debugging output enabled
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#endif
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#ifndef DEBUG_GDB_DUMP_DATA
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#define DEBUG_GDB_DUMP_DATA 0  // GDB Socket Debugging - output all data we return to GDB client
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#endif
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#define Boolean uint32_t
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#define false 0
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#define true 1
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/* Selects crc trailer size in bits. Currently supported: 8 */
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#define CRC_SIZE (8)
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#include <stdint.h>
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extern int serverPort;
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extern int server_fd;
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extern int vpi_fd; // should be the descriptor for our connection to the VPI server
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extern int current_chain;
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extern int dbg_chain;
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#define DBGCHAIN_SIZE           4 // Renamed from DC_SIZE due to definition clash with something in <windows.h> --jb 090302
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#define DC_STATUS_SIZE    4
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#define DC_WISHBONE       0
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#define DC_CPU0           1
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#define DC_CPU1           2
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// Defining access types for wishbone
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#define DBG_WB_WRITE8           0
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#define DBG_WB_WRITE16          1
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#define DBG_WB_WRITE32          2
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#define DBG_WB_READ8            4
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#define DBG_WB_READ16           5
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#define DBG_WB_READ32           6
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// Defining access types for wishbone
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#define DBG_CPU_WRITE            2
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#define DBG_CPU_READ             6
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// Manually figure the 5-bit reversed values again if they change
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#define DI_GO          0
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#define DI_READ_CMD    1
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#define DI_WRITE_CMD   2
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#define DI_READ_CTRL   3
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#define DI_WRITE_CTRL  4
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#define DBG_CRC_SIZE      32
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#define DBG_CRC_POLY      0x04c11db7
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#define DBG_ERR_OK        0
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#define DBG_ERR_INVALID_ENDPOINT 3
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#define DBG_ERR_CRC       8
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#define NUM_SOFT_RETRIES  3
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#define NUM_HARD_RETRIES  3
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#define NUM_ACCESS_RETRIES 10
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/* setup connection with the target */
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void dbg_test();
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/* perform a reset of the debug chain (not of system!) */
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int dbg_reset();
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/* set instruction register of JTAG TAP */
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int dbg_set_tap_ir(uint32_t ir);
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/* Set "scan chain" of debug unit (NOT JTAG TAP!) */
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int dbg_set_chain(uint32_t chain);
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/* read a byte from wishbone */
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int dbg_wb_write8(uint32_t adr, uint8_t data);
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/* read a word from wishbone */
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int dbg_wb_read32(uint32_t adr, uint32_t *data);
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/* write a word to wishbone */
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int dbg_wb_write32(uint32_t adr, uint32_t data);
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/* read a block from wishbone */
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int dbg_wb_read_block32(uint32_t adr, uint32_t *data, uint32_t len);
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/* write a block to wishbone */
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int dbg_wb_write_block32(uint32_t adr, uint32_t *data, uint32_t len);
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/* read a register from cpu */
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int dbg_cpu0_read(uint32_t adr, uint32_t *data, uint32_t length);
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/* read a register from cpu module */
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int dbg_cpu0_read_ctrl(uint32_t adr, unsigned char *data);
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/* write a cpu register */
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int dbg_cpu0_write(uint32_t adr, uint32_t *data, uint32_t length);
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/* write a cpu module register */
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int dbg_cpu0_write_ctrl(uint32_t adr, unsigned char data);
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void print_usage(); // Self explanatory
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void check(char *fn, uint32_t l, uint32_t i);
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/* Possible errors are listed here.  */
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enum enum_errors  /* modified <chris@asics.ws> CZ 24/05/01 */
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{
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  /* Codes > 0 are for system errors */
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  ERR_NONE = 0,
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  ERR_CRC = -1,
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  ERR_MEM = -2,
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  JTAG_PROXY_INVALID_COMMAND = -3,
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  JTAG_PROXY_SERVER_TERMINATED = -4,
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  JTAG_PROXY_NO_CONNECTION = -5,
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  JTAG_PROXY_PROTOCOL_ERROR = -6,
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  JTAG_PROXY_COMMAND_NOT_IMPLEMENTED = -7,
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  JTAG_PROXY_INVALID_CHAIN = -8,
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  JTAG_PROXY_INVALID_ADDRESS = -9,
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  JTAG_PROXY_ACCESS_EXCEPTION = -10, /* Write to ROM */
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  JTAG_PROXY_INVALID_LENGTH = -11,
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  JTAG_PROXY_OUT_OF_MEMORY = -12,
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};
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#endif /* _OR_DEBUG_PROXY_H_ */
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