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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] [DebugUnitSC.h] - Blame information for rev 63

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// ----------------------------------------------------------------------------
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// SystemC OpenRISC 1000 Debug Unit: definition
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// Copyright (C) 2008  Embecosm Limited <info@embecosm.com>
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// Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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// This file is part of the GDB interface to the cycle accurate model of the
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// OpenRISC 1000 based system-on-chip, ORPSoC, built using Verilator.
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// This program is free software: you can redistribute it and/or modify it
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// under the terms of the GNU Lesser General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or (at your
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// option) any later version.
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
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// License for more details.
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// You should have received a copy of the GNU Lesser General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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// ----------------------------------------------------------------------------
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// $Id: DebugUnitSC.h 331 2009-03-12 17:01:48Z jeremy $
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#ifndef DEBUG_UNIT_SC__H
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#define DEBUG_UNIT_SC__H
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// Define if no cache is wanted
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#define NOCACHE
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#include <stdint.h>
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#include "systemc"
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#include "jtagsc.h"
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#include "OrpsocAccess.h"
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#include "SprCache.h"
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#include "MemCache.h"
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//-----------------------------------------------------------------------------
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//! Module modeling the OpenRISC 1000 Debug Unit
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//! Provides a high level interface to the GDB Server module with functions to
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//! access SPRs, Wishbone memory and CPU control.
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//! Provides a low level interface to the Embecosm SystemC JTAG interface,
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//! queueing requests to read and write JTAG registers.
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//-----------------------------------------------------------------------------
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class DebugUnitSC
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  : public sc_core::sc_module
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{
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public:
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  // Constructor and destructor
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  DebugUnitSC (sc_core::sc_module_name        name,
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               sc_core::sc_fifo<TapAction *> *_tapActionQueue);
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  ~DebugUnitSC ();
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  // Reset function for the debug unit
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  void      resetDebugUnit ();
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  // Functions to control and report on the CPU
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  void      reset ();
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  void      stall ();
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  void      unstall ();
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  bool      isStalled ();
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  // Functions to access SPRs
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  uint32_t  readSpr (uint16_t  sprNum);
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  void      writeSpr (uint16_t  sprNum,
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                      uint32_t  value);
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  void      andSpr (uint16_t  sprNum,
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                    uint32_t  value);
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  void      orSpr (uint16_t  sprNum,
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                   uint32_t  value);
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  // Functions to access memory
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  uint32_t  readMem32 (uint32_t  addr);
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  bool      writeMem32 (uint32_t  addr,
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                        uint32_t   value);
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  uint8_t   readMem8 (uint32_t  addr);
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  bool      writeMem8 (uint32_t  addr,
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                       uint8_t   value);
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private:
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  // JTAG instructions
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  static const uint32_t  CHAIN_SELECT_IR = 0x3;  //!< Chain Select instruction
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  static const uint32_t  DEBUG_IR        = 0x8;  //!< Debug instruction
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  //! JTAG instruction register length. There is no CRC for this register.
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  static const int  JTAG_IR_LEN       =  4;     //!< JTAG instr reg length
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  // DEBUG UNIT CHAIN data register fields
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  static const int  DUSEL_DR_LEN     = 73;  //!< total DUSEL DR size
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  static const int  DUSEL_SEL_OFF =  0;  //!< start of select field
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  static const int  DUSEL_SEL_LEN =  1;  //!< length of select field
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  static const int  DUSEL_OPCODE_OFF =  DUSEL_SEL_OFF + DUSEL_SEL_LEN;  //!< start of opcode field
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  static const int  DUSEL_OPCODE_LEN =  4;  //!< length of opcode field
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  static const int  DUSEL_CRC_OFF    =  DUSEL_OPCODE_OFF + DUSEL_OPCODE_LEN;  //!< start of CRC field
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  static const int  DUSEL_CRC_LEN    = 32;  //!< length of CRC field
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  static const int  DUSEL_RESP_STATUS_OFF = DUSEL_CRC_OFF + DUSEL_CRC_LEN;
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  static const int  DUSEL_RESP_STATUS_LEN = 4;
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  static const int  DUSEL_RESP_CRC_OFF = DUSEL_RESP_STATUS_OFF + DUSEL_RESP_STATUS_LEN;
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  static const int  DUSEL_RESP_CRC_LEN = 32;
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  static const uint32_t  DBG_CRC32_POLY = 0x04c11db7;
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  // OpenRISC 1000 scan chains (values in DUSEL data register field)
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  static const int  OR1K_SC_UNDEF      = -1;    //!< Undefined OR1K scan chain
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  static const int  OR1K_SC_WISHBONE   =  0;     //!< for memory access
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  static const int  OR1K_SC_CPU0 =  1;          //!< for access to CPU0
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  static const int  OR1K_SC_CPU1 =  2;          //!< for access to CPU1
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  // JTAG RISC_DEBUG (for accessing SPR) data register fields
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  static const int  RISC_DEBUG_DR_LEN    = 74;  //!< Total RISC_DEBUG DR size
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  static const int  RISC_DEBUG_ADDR_OFF  =  0;   //!< start of address field
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  static const int  RISC_DEBUG_ADDR_LEN  = 32;  //!< length of address field
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  static const int  RISC_DEBUG_RW_OFF    = 32;  //!< start of read/write field
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  static const int  RISC_DEBUG_RW_LEN    =  1;  //!< length of read/write field
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  static const int  RISC_DEBUG_DATA_OFF  = 33;  //!< start of data field
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  static const int  RISC_DEBUG_DATA_LEN  = 32;  //!< length of data field
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  static const int  RISC_DEBUG_CRC_OFF   = 65;  //!< start of CRC field
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  static const int  RISC_DEBUG_CRC_LEN   =  8;  //!< length of CRC field
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  static const int  RISC_DEBUG_SPARE_OFF = 73;  //!< start of spare bits
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  static const int  RISC_DEBUG_SPARE_LEN =  1;  //!< length of spare bit field
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  // JTAG REGISTER (for controlling the CPU) data register fields
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  static const int  REGISTER_DR_LEN      = 47;  //!< Total REGISTER DR size
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  static const int  REGISTER_ADDR_OFF    =  0;   //!< start of address field
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  static const int  REGISTER_ADDR_LEN    =  5;  //!< length of address field
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  static const int  REGISTER_RW_OFF      =  5;  //!< start of read/write field
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  static const int  REGISTER_RW_LEN      =  1;  //!< length of read/write field
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  static const int  REGISTER_DATA_OFF    =  6;  //!< start of data field
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  static const int  REGISTER_DATA_LEN    = 32;  //!< length of data field
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  static const int  REGISTER_CRC_OFF     = 38;  //!< start of CRC field
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  static const int  REGISTER_CRC_LEN     =  8;  //!< length of CRC field
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  static const int  REGISTER_SPARE_OFF   = 46;  //!< start of spare bits
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  static const int  REGISTER_SPARE_LEN   =  1;  //!< length of spare bit field
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  // Register addresses for the REGISTER scan chain
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  static const uint8_t  OR1K_RSC_RISCOP = 0x04; //!< Used to reset/stall CPU
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  // Bits for the RISCOP register
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  static const uint32_t  RISCOP_RESET = 0x00000001;     //!< Reset the CPU
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  static const uint32_t  RISCOP_STALL = 0x00000002;     //!< Stall the CPU
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  // JTAG WISHBONE (for accessing SPR) data register fields
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  static const int  WISHBONE_DR_LEN      = 74;  //!< Total WISHBONE DR size
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  static const int  WISHBONE_ADDR_OFF    =  0;   //!< start of address field
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  static const int  WISHBONE_ADDR_LEN    = 32;  //!< length of address field
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  static const int  WISHBONE_RW_OFF      = 32;  //!< start of read/write field
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  static const int  WISHBONE_RW_LEN      =  1;  //!< length of read/write field
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  static const int  WISHBONE_DATA_OFF    = 33;  //!< start of data field
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  static const int  WISHBONE_DATA_LEN    = 32;  //!< length of data field
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  static const int  WISHBONE_CRC_OFF     = 65;  //!< start of CRC field
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  static const int  WISHBONE_CRC_LEN     =  8;  //!< length of CRC field
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  static const int  WISHBONE_SPARE_OFF   = 73;  //!< start of spare bits
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  static const int  WISHBONE_SPARE_LEN   =  1;  //!< length of spare bit field
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  //! The NPC is special, so we need to know about it
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  static const int  SPR_NPC = 0x10;
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  //! The JTAG fifo we queue on
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  sc_core::sc_fifo<TapAction *> *tapActionQueue;
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  //! The processor stall state. When stalled we can use cacheing on
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  //! reads/writes of memory and SPRs.
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  enum {
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    UNKNOWN,
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    STALLED,
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  } stallState;
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  //! The currently selected scan chain
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  int  currentScanChain;
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#ifdef NOCACHE
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  //! Even if no cached, we need to cache the NPC
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  uint32_t  npcCachedValue;
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  //! Cached NPC is valid
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  bool  npcCacheIsValid;
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#else
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  //! The SPR cache
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  SprCache *sprCache;
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  //! The memory cache
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  MemCache *memCache;
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#endif
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  // Functions to control the CPU
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  uint32_t  readRiscop ();
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  void      writeRiscop (uint32_t  value);
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  // Or1k JTAG actions
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  void      selectDebugModule (int chain);
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  uint32_t  readJtagReg (uint32_t  addr);
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  uint32_t  readJtagReg1 (uint32_t   addr,
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                          int        bitSizeNoCrc);
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  uint32_t  readJtagReg1 (uint64_t  *dRegArray,
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                          uint32_t   addr,
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                          int        bitSizeNoCrc);
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  void      writeJtagReg (uint32_t  addr,
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                          uint32_t  data);
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  // Utilities to pack and unpack bits to/from data registers.
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  void clearBits (uint64_t  regArray[],
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                  int       regBits);
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  void packBits (uint64_t  regArray[],
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                 int       fieldOffset,
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                 int       fieldBits,
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                 uint64_t  fieldVal);
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  uint64_t  unpackBits (uint64_t  regArray[],
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                        int       fieldOffset,
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                        int       fieldBits);
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  // Utility to compute CRC-8 the OpenRISC way.
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  uint8_t  crc8 (uint64_t  dataArray[],
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                 int       size);
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  // Utility to compute CRC-32 for the debug unit
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  uint32_t  crc32 (uint64_t  dataArray[],
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                   int       size,
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                   int       offset);
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  // Functions to bitreverse values
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  uint32_t bit_reverse_swar_2(uint32_t x);
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  uint32_t bit_reverse_swar_4(uint32_t x);
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  uint32_t bit_reverse_swar_8(uint32_t x);
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  uint32_t bit_reverse_swar_16(uint32_t x);
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  uint32_t bit_reverse_swar_32(uint32_t x);
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#define BITREV(x,y) bit_reverse_data(x,y)
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  uint32_t bit_reverse_data(uint32_t x, int length);
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};      // DebugUnitSC ()
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#endif  // DEBUG_UNIT_SC__H

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