OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] [MemCache.h] - Blame information for rev 425

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 63 julius
// ----------------------------------------------------------------------------
2
 
3
// Debug Unit memory cache: definition
4
 
5
// Copyright (C) 2008  Embecosm Limited <info@embecosm.com>
6
 
7
// Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
8
 
9
// This file is part of the GDB interface to the cycle accurate model of the
10
// OpenRISC 1000 based system-on-chip, ORPSoC, built using Verilator.
11
 
12
// This program is free software: you can redistribute it and/or modify it
13
// under the terms of the GNU Lesser General Public License as published by
14
// the Free Software Foundation, either version 3 of the License, or (at your
15
// option) any later version.
16
 
17
// This program is distributed in the hope that it will be useful, but WITHOUT
18
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
20
// License for more details.
21
 
22
// You should have received a copy of the GNU Lesser General Public License
23
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
24
 
25
// ----------------------------------------------------------------------------
26
 
27
// $Id: MemCache.h 326 2009-03-07 16:47:31Z jeremy $
28
 
29
#ifndef MEM_CACHE__H
30
#define MEM_CACHE__H
31
 
32
#include <stdint.h>
33
 
34
 
35
//! Module for cacheing memory accesses by the debug unit
36
 
37
//! Memory reads and writes through the Debug Unit via JTAG are time
38
//! consuming - of the order of 1000 CPU clock cycles. However when the
39
//! processor is stalled the values cannot change, other than through the
40
//! debug unit, so it makes sense to cache values.
41
 
42
//! Cacheing the entire memory is too much (it does need to be cleared when
43
//! the processor is unstalled. This class provides a cacheing function using
44
//! a closed hash table.
45
 
46
//! In the event of a clash on write, the old value is replaced by the new
47
//! value.
48
 
49
class MemCache
50
{
51
public:
52
 
53
  // Constructor and destructor
54
  MemCache (int  _tableSize = 1009);
55
  ~MemCache ();
56
 
57
  // Functions
58
  void  clear ();
59
  void  write (uint32_t  addr,
60
               uint32_t  value);
61
  bool  read (uint32_t  addr,
62
              uint32_t &value);
63
 
64
private:
65
 
66
  //! The size of the hash table. A prime number is a good choice.
67
  int  tableSize;
68
 
69
  // The hash table, keyed by address. Done as three parallel vectors,
70
  // allowing unambiguous clearing by use of memset for efficiency.
71
  bool     *tabIsValid;
72
  uint32_t *tabKeyAddr;
73
  uint32_t *tabValue;
74
 
75
 
76
};      // MemCache ()
77
 
78
#endif  // MEM_CACHE__H

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.