OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] [OrpsocMain.h] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  ORPSoC SystemC Testbench header                             ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  ORPSoC Testbench header file                                ////
7
////                                                              ////
8
////  To Do:                                                      ////
9
////                                                              ////
10
////                                                              ////
11
////  Author(s):                                                  ////
12
////      - Jeremy Bennett jeremy.bennett@embecosm.com            ////
13
////      - Julius Baxter jb@orsoc.se                             ////
14
////                                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// SystemC declarations that should be visible anywhere. These should be
44
// consistent with the values used in the Verilog
45
 
46
#ifndef ORPSOC_MAIN__H
47
#define ORPSOC_MAIN__H
48
 
49
//! The Verilog timescale unit (as SystemC timescale unit)
50
#define TIMESCALE_UNIT        SC_NS
51
 
52
//! The number of cycles of reset required
53
#define BENCH_RESET_TIME      10
54
 
55
//! CPU clock Half period in timescale units
56
#define BENCH_CLK_HALFPERIOD  20
57
 
58
#endif  // ORPSOC_MAIN__H

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.