OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] [ResetSC.h] - Blame information for rev 462

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 julius
// ----------------------------------------------------------------------------
2
 
3
// SystemC reset signal generator header
4
 
5
// Copyright (C) 2008  Embecosm Limited <info@embecosm.com>
6
 
7
// Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
8
 
9
// This file is part of the cycle accurate model of the OpenRISC 1000 based
10
// system-on-chip, ORPSoC, built using Verilator.
11
 
12
// This program is free software: you can redistribute it and/or modify it
13
// under the terms of the GNU Lesser General Public License as published by
14
// the Free Software Foundation, either version 3 of the License, or (at your
15
// option) any later version.
16
 
17
// This program is distributed in the hope that it will be useful, but WITHOUT
18
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
20
// License for more details.
21
 
22
// You should have received a copy of the GNU Lesser General Public License
23
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
24
 
25
// ----------------------------------------------------------------------------
26
 
27
// $Id: ResetSC.h 286 2009-02-03 11:19:30Z jeremy $
28
 
29
#ifndef RESET_SC__H
30
#define RESET_SC__H
31
 
32
#include "systemc"
33
 
34
//! Provide a SystemC reset signal at startup
35
 
36
//! The reset signal is driven for a specified number of cycles after
37
//! creation. For convenience synchronous versions of the reset signal are
38
//! provided in both active high and active low formats.
39
 
40 462 julius
class ResetSC:public sc_core::sc_module {
41 6 julius
public:
42
 
43 462 julius
        // Constructor
44
        ResetSC(sc_core::sc_module_name name, int _resetCounter = 5);
45 6 julius
 
46 462 julius
        // Method to drive the reset
47
        void driveReset();
48 6 julius
 
49 462 julius
        // The ports
50
        sc_core::sc_in < bool > clk;
51
        sc_core::sc_out < bool > rst;   // Active high reset
52
        sc_core::sc_out < bool > rstn;  // Active low reset
53 6 julius
 
54
private:
55
 
56 462 julius
        int resetCounter;
57 6 julius
 
58 462 julius
};                              // ResetSC ()
59 6 julius
 
60 462 julius
#endif // RESET_SC__H

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.