OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [include/] [UartSC.h] - Blame information for rev 49

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 julius
// ----------------------------------------------------------------------------
2
 
3
// SystemC Uart: definition
4
 
5
// This file is part of the cycle accurate model of the OpenRISC 1000 based
6
// system-on-chip, ORPSoC, built using Verilator.
7
 
8
// This program is free software: you can redistribute it and/or modify it
9
// under the terms of the GNU Lesser General Public License as published by
10
// the Free Software Foundation, either version 3 of the License, or (at your
11
// option) any later version.
12
 
13
// This program is distributed in the hope that it will be useful, but WITHOUT
14
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
16
// License for more details.
17
 
18
// You should have received a copy of the GNU Lesser General Public License
19
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
20
 
21
// ----------------------------------------------------------------------------
22
 
23
// $Id: $
24
 
25
#ifndef UART_SC__H
26
#define UART_SC__H
27
 
28
#include "systemc.h"
29
 
30
//! Handle UART I/O
31
 
32
class UartSC
33
  : public sc_core::sc_module
34
{
35
public:
36
 
37
  // Constructor
38
  UartSC (sc_core::sc_module_name  name);
39
 
40
  // The ports
41
  sc_in<bool>   clk;
42
  sc_in<bool>   uarttx;
43
  sc_out<bool>   uartrx;
44
 
45
  // Init function
46
  void initUart (int clk_freq_hz, int uart_baud) ;
47
  // Transmit (from ORPSoC) handling function
48
  void checkTx();
49
 
50
private:
51
  int clocks_per_bit;
52
  uint8_t current_char;
53
  int counter;
54
  int bits_received;
55
 
56
};      // UartSC ()
57
 
58
#endif  // UART_SC__H

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.