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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [DebugUnitSC.cpp] - Blame information for rev 178

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// ----------------------------------------------------------------------------
2
 
3
// SystemC OpenRISC 1000 Debug Unit: implementation
4
 
5
// Copyright (C) 2008  Embecosm Limited <info@embecosm.com>
6
// Copyright (C) 2009  ORSoC
7
 
8
// Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
9
// Contributor Julius Baxter <julius@orsoc.se>
10
 
11
// This file is part of the GDB interface to the cycle accurate model of the
12
// OpenRISC 1000 based system-on-chip, ORPSoC, built using Verilator.
13
 
14
// This program is free software: you can redistribute it and/or modify it
15
// under the terms of the GNU Lesser General Public License as published by
16
// the Free Software Foundation, either version 3 of the License, or (at your
17
// option) any later version.
18
 
19
// This program is distributed in the hope that it will be useful, but WITHOUT
20
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
21
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
22
// License for more details.
23
 
24
// You should have received a copy of the GNU Lesser General Public License
25
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
26
 
27
// ----------------------------------------------------------------------------
28
 
29
// $Id$
30
 
31
#include <iostream>
32
#include <iomanip>
33
 
34
#include "DebugUnitSC.h"
35
#include "Utils.h"
36
 
37
 
38
using sc_core::sc_event;
39
using sc_core::sc_fifo;
40
using sc_core::sc_module_name;
41
 
42
 
43
//-----------------------------------------------------------------------------
44
//! Constructor for the Debug Unit
45
 
46
//! This module is entirely subservient to the GDB server. It has no SystemC
47
//! processes of its own. It provides services via calls to its API.
48
 
49
//! The current scan chain is marked as undefined, and the current JTAG scan
50
//! chain is maked as undefined.
51
 
52
//! Caches for SPR and memory access are initialized.
53
 
54
//! This makes use of the Embecosm cycle accurate SystemC JTAG interface.
55
 
56
//! @see Embecosm Application Note 5 "Using JTAG with SystemC: Implementation
57
//!      of a Cycle Accurate Interface"
58
//!      (http://www.embecosm.com/download/ean5.html)
59
 
60
//! @param[in] name             Name of this module, passed to the parent
61
//!                             constructor. 
62
//! @param[in] _tapActionQueue  Pointer to fifo of actions to be performed by
63
//!                             the JTAG interface
64
//-----------------------------------------------------------------------------
65
DebugUnitSC::DebugUnitSC (sc_module_name        name,
66
                          sc_fifo<TapAction *> *_tapActionQueue) :
67
  sc_module (name),
68
  tapActionQueue (_tapActionQueue),
69
  stallState (UNKNOWN),
70
  currentScanChain (OR1K_SC_UNDEF)
71
{
72
#ifdef NOCACHE
73
  npcCacheIsValid = false;              // Always cache NPC
74
#else
75
  sprCache = new SprCache ();
76
  memCache = new MemCache ();
77
#endif
78
 
79
}       // DebugUnitSC ()
80
 
81
 
82
//-----------------------------------------------------------------------------
83
//! Destructor
84
 
85
//! Free up data structures
86
//-----------------------------------------------------------------------------
87
DebugUnitSC::~DebugUnitSC ()
88
{
89
#ifndef NOCACHE
90
  delete  memCache;
91
  delete  sprCache;
92
#endif
93
 
94
}       // ~DebugUnitSC
95
 
96
 
97
//-----------------------------------------------------------------------------
98
//! Reset the Debug Unit
99
 
100
//! This is just a reset of the JTAG. It is quite possible to reset the debug
101
//! unit without resetting the whole target.
102
 
103
//! @note Must be called from a SystemC thread, because of the use of wait()
104
//-----------------------------------------------------------------------------
105
void
106
DebugUnitSC::resetDebugUnit ()
107
{
108
  sc_event       *done = new sc_event();
109
  TapActionReset *resetAction;
110
 
111
  // Create and queue the reset action and wait for it to complete
112
  resetAction = new TapActionReset (done);
113
  tapActionQueue->write (resetAction);
114
  wait (*done);
115
 
116
  delete resetAction;
117
  delete done;
118
 
119
}       // resetDebugUnit ()
120
 
121
 
122
//-----------------------------------------------------------------------------
123
//! Reset the processor
124
 
125
//! Read the RISCOP register, OR in the reset bit and write it back.
126
 
127
//! After reset, the processor is known to be unstalled.
128
//-----------------------------------------------------------------------------
129
void
130
DebugUnitSC::reset ()
131
{
132
  writeRiscop (readRiscop () | RISCOP_RESET);
133
  stallState = UNKNOWN;
134
 
135
}       // reset ()
136
 
137
 
138
//-----------------------------------------------------------------------------
139
//! Stall the processor
140
 
141
//! Read the RISCOP register, OR in the stall bit and write it back.
142
//-----------------------------------------------------------------------------
143
void
144
DebugUnitSC::stall ()
145
{
146
  writeRiscop (/*readRiscop () |*/ RISCOP_STALL);
147
  stallState = STALLED;
148
 
149
}       // stall ()
150
 
151
 
152
//-----------------------------------------------------------------------------
153
//! Unstall the processor
154
 
155
//! Read the RISCOP register, AND out the stall bit and write it back. After
156
//! this the NPC cache will be invalid.
157
 
158
//! @note Don't be tempted to read back for confirmation. Single stepping
159
//!       will already have stalled the processor again!
160
//-----------------------------------------------------------------------------
161
void
162
DebugUnitSC::unstall ()
163
{
164
  writeRiscop (/*readRiscop () & ~RISCOP_STALL*/ 0);
165
  stallState  = UNKNOWN;
166
 
167
#ifdef NOCACHE
168
  npcCacheIsValid = false;              // Always cache NPC
169
#else
170
  // Clear the caches
171
  sprCache->clear ();
172
  memCache->clear ();
173
#endif
174
 
175
}       // unstall ()
176
 
177
 
178
//-----------------------------------------------------------------------------
179
//! Report if the processor is stalled.
180
 
181
//! A stalled processor cannot spontaneously "unstall", so if the stallState
182
//! flag is STALLED, that value is returned. Otherwise the target is
183
//! interrogated to determine the status.
184
 
185
//! @return  TRUE if the processor is known to be stalled
186
//-----------------------------------------------------------------------------
187
bool
188
DebugUnitSC::isStalled ()
189
{
190
  if (STALLED == stallState)
191
    {
192
      return  true;
193
    }
194
 
195
  uint32_t  riscop = readRiscop ();
196
  /* For some reason the reset bit is skipped over somewhere, so we should
197
     just get riscop = 1 if it's stalled */
198
 
199
  //stallState = (RISCOP_STALL == (riscop & RISCOP_STALL)) ? STALLED : UNKNOWN;
200
  stallState = riscop ? STALLED : UNKNOWN;
201
 
202
  return  STALLED == stallState;
203
 
204
}       // isStalled ()
205
 
206
 
207
//-----------------------------------------------------------------------------
208
//! Read the value of an OpenRISC 1000 Special Purpose Register
209
 
210
//! First see if we have the value in the cache, and if so return
211
//! it. Otherwise, select the RISC_DEBUG scan chain and read from JTAG,
212
//! storing the result in the cache.
213
 
214
//! @param[in]  sprNum  The SPR to read
215
 
216
//! @return  The value of the SPR
217
//-----------------------------------------------------------------------------
218
uint32_t
219
DebugUnitSC::readSpr (uint16_t  sprNum)
220
{
221
  uint32_t  cachedValue;
222
 
223
#ifdef NOCACHE
224
  // Always check NPC cache
225
  if ((STALLED == stallState) && (sprNum == SPR_NPC) && npcCacheIsValid)
226
    {
227
      return  npcCachedValue;
228
    }
229
#else
230
  // Use any cached value if we are stalled.
231
  if ((STALLED == stallState) && sprCache->read (sprNum, cachedValue))
232
    {
233
      return  cachedValue;              // Already there, no more to do
234
    }
235
#endif
236
 
237
  // Read the value
238
  selectDebugModule (OR1K_SC_CPU0);
239
  cachedValue = readJtagReg (sprNum);
240
 
241
#ifdef NOCACHE
242
  // Always update the NPC cache
243
  if ((STALLED == stallState) && (sprNum == SPR_NPC))
244
    {
245
      npcCachedValue  = cachedValue;
246
      npcCacheIsValid = true;
247
    }
248
#else
249
  // Update the cache if we are stalled
250
  if (STALLED == stallState)
251
    {
252
      sprCache->write (sprNum, cachedValue, sprNum == SPR_NPC);
253
    }
254
#endif
255
 
256
  return  cachedValue;
257
 
258
}       // readSpr ()
259
 
260
 
261
//-----------------------------------------------------------------------------
262
//! Write the value of an OpenRISC 1000 Special Purpose Register
263
 
264
//! First look to see if we are stalled and the value is cached. If the value
265
//! has not changed, then we need to no more. Otherwise cache the value prior
266
//! to writing it.
267
 
268
//! Select the RISC_DEBUG scan chain and write to JTAG
269
 
270
//! @param[in] sprNum  The SPR to write
271
//! @param[in] value   The value to write
272
//-----------------------------------------------------------------------------
273
void
274
DebugUnitSC::writeSpr (uint16_t  sprNum,
275
                       uint32_t  value)
276
{
277
#ifdef NOCACHE
278
  // Always cache the NPC
279
  if ((STALLED == stallState) && (SPR_NPC == sprNum))
280
    {
281
      // Have we already cached this NPC value?
282
      if (npcCacheIsValid && (value == npcCachedValue))
283
        {
284
          return;
285
        }
286
      else
287
        {
288
          npcCachedValue  = value;
289
          npcCacheIsValid = true;
290
        }
291
    }
292
#else
293
  if (STALLED == stallState)
294
    {
295
      // Have we already cached this value?
296
      uint32_t  cachedValue;
297
      if (sprCache->read (sprNum, cachedValue) &&
298
          (value == cachedValue))
299
        {
300
          return;                               // Already there, no more to do
301
        }
302
      else
303
        {
304
          sprCache->write (sprNum, value, sprNum == SPR_NPC);
305
        }
306
    }
307
#endif
308
 
309
  // Write the SPR
310
  selectDebugModule (OR1K_SC_CPU0);
311
  writeJtagReg (sprNum, value);
312
 
313
}       // writeSpr ()
314
 
315
 
316
//-----------------------------------------------------------------------------
317
//! AND the contents of an SPR with a value
318
 
319
//! A convenience combination of read and write
320
 
321
//! @param[in] sprNum  The SPR to write
322
//! @param[in] value   The value to AND into the register
323
//-----------------------------------------------------------------------------
324
void
325
DebugUnitSC::andSpr (uint16_t  sprNum,
326
                     uint32_t  value)
327
{
328
  writeSpr (sprNum, readSpr (sprNum) & value);
329
 
330
}       // andSpr ()
331
 
332
 
333
//-----------------------------------------------------------------------------
334
//! OR the contents of an SPR with a value
335
 
336
//! A convenience combination of read and write
337
 
338
//! @param[in] sprNum  The SPR to write
339
//! @param[in] value   The value to OR into the register
340
//-----------------------------------------------------------------------------
341
void
342
DebugUnitSC::orSpr (uint16_t  sprNum,
343
                   uint32_t  value)
344
{
345
  writeSpr (sprNum, readSpr (sprNum) | value);
346
 
347
}       // orSpr ()
348
 
349
 
350
//-----------------------------------------------------------------------------
351
//! Read a 32-bit word from the OpenRISC 1000 memory
352
 
353
//! Select the WISHBONE scan chain, then write the register. The data is in
354
//! model endianness and passed on without modification.
355
 
356
//! @todo Provide code to check if the read was from a valid address.
357
 
358
//! @param[in] addr  The address to read from
359
 
360
//! @return  The 32-bit value read
361
//-----------------------------------------------------------------------------
362
uint32_t
363
DebugUnitSC::readMem32 (uint32_t  addr)
364
{
365
  uint32_t  cachedValue;
366
 
367
#ifndef NOCACHE
368
  // Use any cached value if we are stalled.
369
  if ((STALLED == stallState) && memCache->read (addr, cachedValue))
370
    {
371
      return  cachedValue;              // Already there, no more to do
372
    }
373
#endif
374
 
375
  // Read the value
376
  selectDebugModule (OR1K_SC_WISHBONE);
377
  cachedValue = readJtagReg (addr);
378
 
379
#ifndef NOCACHE
380
  // Update the cache if we are stalled
381
  if (STALLED == stallState)
382
    {
383
      memCache->write (addr, cachedValue);
384
    }
385
#endif
386
 
387
  return  cachedValue;
388
 
389
}       // readMem32 ()
390
 
391
 
392
//-----------------------------------------------------------------------------
393
//! Write a 32-bit word to the OpenRISC 1000 memory
394
 
395
//! Select the WISHBONE scan chain, then write the register. The data is in
396
//! model endianness and passed on without modification.
397
 
398
//! @todo Provide code to check if the write was to a valid address.
399
 
400
//! @param[in] addr   The address to write to
401
//! @param[in] value  The 32-bit value to write
402
 
403
//! @return  True if the write was successful. For now all writes are
404
//           successful.
405
//-----------------------------------------------------------------------------
406
bool
407
DebugUnitSC::writeMem32 (uint32_t  addr,
408
                         uint32_t  value)
409
{
410
#ifndef NOCACHE
411
  if (STALLED == stallState)
412
    {
413
      // Have we already cached this value?
414
      uint32_t  cachedValue;
415
      if (memCache->read (addr, cachedValue) &&
416
          (value == cachedValue))
417
        {
418
          return  true;                         // Already there, no more to do
419
        }
420
      else
421
        {
422
          memCache->write (addr, value);        // Write for the future
423
        }
424
    }
425
#endif
426
 
427
  // Write the memory
428
  selectDebugModule (OR1K_SC_WISHBONE);
429
  writeJtagReg (addr, value);
430
 
431
  return  true;
432
 
433
}       // writeMem32 ()
434
 
435
 
436
//-----------------------------------------------------------------------------
437
//! Read a byte from the OpenRISC 1000 main memory
438
 
439
//! All we can get are 32-bits words, so we have to unpick the value.
440
 
441
//! The underlying 32-bit routines take target endian arguments and return
442
//! target endian results. We need to convert to host endianness to access the
443
//! relevant byte.
444
 
445
//! @todo Provide code to check if the read was from a valid address.
446
 
447
//! @note Read bytes from memory mapped devices at your peril!
448
 
449
//! @param[in] addr  The address to read from
450
//! @return  The byte read
451
//-----------------------------------------------------------------------------
452
uint8_t
453
DebugUnitSC::readMem8 (uint32_t  addr)
454
{
455
  uint32_t  word   = Utils::ttohl (readMem32 (addr & 0xfffffffc));
456
  uint8_t  *bytes  = (uint8_t *)(&word);
457
  int       offset = addr & 0x3;
458
 
459
  return  bytes[offset];
460
 
461
}       // readMem8 ()
462
 
463
 
464
//-----------------------------------------------------------------------------
465
//! Write a byte to the OpenRISC 1000 main memory
466
 
467
//! All we can get are 32-bits words, so we have to read the current value and
468
//! construct the new value to write back.
469
 
470
//! The underlying 32-bit routines take target endian arguments and return
471
//! target endian results. We need to convert to host endianness to alter the
472
//! relevant byte.
473
 
474
//! @note Write bytes to memory mapped devices at your peril!
475
 
476
//! @todo Provide code to check if the write was to a valid address.
477
 
478
//! @param[in] addr   The address to write to
479
//! @param[in] value  The byte to write
480
 
481
//! @return  True if the write was successful. For now all writes are
482
//           successful.
483
//-----------------------------------------------------------------------------
484
bool
485
DebugUnitSC::writeMem8 (uint32_t  addr,
486
                        uint8_t   value)
487
{
488
  uint32_t  currWord  = Utils::ttohl (readMem32 (addr & 0xfffffffc));
489
  uint8_t  *currBytes = (uint8_t *)(&currWord);
490
  int       offset    = addr & 0x3;
491
 
492
  currBytes[offset] = value;
493
 
494
  return  writeMem32 (addr & 0xfffffffc, Utils::htotl (currWord));
495
 
496
}       // writeMem8 ()
497
 
498
 
499
//-----------------------------------------------------------------------------
500
//! Get the debug interface CPU0 control register value
501
 
502
//! @return  The value in the RISCOP register
503
//-----------------------------------------------------------------------------
504
uint32_t
505
DebugUnitSC::readRiscop ()
506
{
507
  selectDebugModule (OR1K_SC_CPU0);
508
 
509
  int  drLen;                   // Size of the data register
510
 
511
  uint32_t calc_recv_crc = 0, recv_crc, status_ret;
512
 
513
  drLen = 1+4+32+52+4+32;
514
 
515
  // Initialize the register fields
516
  uint64_t *dRegIn  = new uint64_t [(drLen + 63) / 64];
517
  uint64_t *dRegOut = new uint64_t [(drLen + 63) / 64];
518
 
519
  // Write the READ command
520
  clearBits (dRegIn, drLen);
521
 
522
  packBits (dRegIn, 0, 1, 0);
523
  packBits (dRegIn, 0+1, 4, BITREV(0x3,4)); // We're reading CPU0 control reg
524
  uint32_t crc32_send = crc32 (dRegIn, 0+1+4, 0);
525
  packBits (dRegIn, 0+1+4, 32, BITREV(crc32_send,32));
526
 
527
  // Allocate a SystemC completion event
528
  sc_event *done  = new sc_event();
529
 
530
  // Loop until status is OK and CRCs match.
531
  do
532
    {
533
      TapActionDRScan *dRScan = new TapActionDRScan (done, dRegIn, drLen);
534
      tapActionQueue->write (dRScan);
535
      wait (*done);
536
      dRScan->getDRegOut (dRegOut);
537
      delete dRScan;
538
      status_ret = unpackBits (dRegOut,1+4+32+52,4);
539
      calc_recv_crc = crc32(dRegOut,52+4,1+4+32);
540
      recv_crc = BITREV(unpackBits (dRegOut,1+4+32+52+4,32),32);
541
    }
542
  while ((0 != status_ret) || ( calc_recv_crc != recv_crc));
543
 
544
  // All done
545
  uint32_t  res = BITREV(unpackBits (dRegOut, (1+4+32),2),2);
546
 
547
  delete [] dRegIn;
548
  delete [] dRegOut;
549
  delete  done;
550
  return  res;
551
}       // readRiscop ()
552
 
553
 
554
//-----------------------------------------------------------------------------
555
//! Set the RISCOP control register
556
 
557
//! Convenience function. Select the REGISTER scan chain, write the new value.
558
 
559
//! @param[in] value  The value to write into the RISCOP register
560
//-----------------------------------------------------------------------------
561
void
562
DebugUnitSC::writeRiscop (uint32_t  value)
563
{
564
  selectDebugModule (OR1K_SC_CPU0);
565
 
566
  int  drLen;                   // Size of the data register
567
 
568
  uint32_t calc_recv_crc = 0, recv_crc, status_ret;
569
 
570
  drLen = 1+4+32+52+4+32;
571
 
572
  // Initialize the register fields
573
  uint64_t *dRegIn  = new uint64_t [(drLen + 63) / 64];
574
  uint64_t *dRegOut = new uint64_t [(drLen + 63) / 64];
575
 
576
  // Write the READ command
577
  clearBits (dRegIn, drLen);
578
 
579
  packBits (dRegIn, 0, 1, 0);
580
  packBits (dRegIn, 0+1, 4, BITREV(0x4,4)); // We're writing CPU0 control reg
581
  packBits (dRegIn, 5, 1, value&RISCOP_RESET); // First bit is reset
582
  packBits (dRegIn, 6, 1, (value&RISCOP_STALL)>>1); // Next bit is stall
583
  /* Next 50 bits should be zero */
584
  uint32_t crc32_send = crc32 (dRegIn, 1+4+52, 0);
585
  packBits (dRegIn, 1+4+52, 32, BITREV(crc32_send,32));
586
 
587
  // Allocate a SystemC completion event
588
  sc_event *done  = new sc_event();
589
 
590
  // Loop until status is OK and CRCs match.
591
  do
592
    {
593
      TapActionDRScan *dRScan = new TapActionDRScan (done, dRegIn, drLen);
594
      tapActionQueue->write (dRScan);
595
      wait (*done);
596
      dRScan->getDRegOut (dRegOut);
597
      delete dRScan;
598
      status_ret = unpackBits (dRegOut,1+4+32+52,4);
599
      calc_recv_crc = crc32(dRegOut,4,1+4+52+32);
600
      recv_crc = BITREV(unpackBits (dRegOut,1+4+52+32+4,32),32);
601
    }
602
  while ((0 != status_ret) || ( calc_recv_crc != recv_crc));
603
 
604
  delete [] dRegIn;
605
  delete [] dRegOut;
606
  delete  done;
607
 
608
}       // writeRiscop ()
609
 
610
 
611
//-----------------------------------------------------------------------------
612
//! Select a module attached to the debug module
613
 
614
//! @note Must be called from a SystemC thread, because of the use of wait()
615
 
616
//! @param[in] chain  The desired module
617
//-----------------------------------------------------------------------------
618
void
619
DebugUnitSC::selectDebugModule (int module)
620
{
621
 
622
  if (module == currentScanChain)
623
    {
624
      return;
625
    }
626
  else
627
    {
628
      currentScanChain = module;
629
    }
630
 
631
  sc_event        *done = new sc_event();
632
  TapActionIRScan *iRScan;
633
  TapActionDRScan *dRScan;
634
 
635
  // Create and queue the IR-Scan action for DEBUG (no CRC)
636
  iRScan      = new TapActionIRScan (done, DEBUG_IR, JTAG_IR_LEN);
637
  tapActionQueue->write (iRScan);
638
  wait (*done);
639
 
640
  delete iRScan;
641
 
642
  // Initialize the register fields
643
  uint64_t *dRegIn  = new uint64_t [(DUSEL_DR_LEN + 63) / 64];
644
  uint64_t *dRegOut = new uint64_t [(DUSEL_DR_LEN + 63) / 64];
645
 
646
  clearBits (dRegIn, DUSEL_DR_LEN);
647
  packBits (dRegIn, DUSEL_SEL_OFF, DUSEL_SEL_LEN, 0x1);
648
  packBits (dRegIn, DUSEL_OPCODE_OFF, DUSEL_OPCODE_LEN, bit_reverse_data(module,4));
649
  uint32_t crc32_send = crc32 (dRegIn, DUSEL_CRC_OFF, 0);
650
  packBits (dRegIn, DUSEL_CRC_OFF, DUSEL_CRC_LEN, bit_reverse_data(crc32_send,32) );
651
  uint32_t calc_recv_crc = 0, recv_crc, status_ret;
652
  // Loop until status is OK and CRCs match.
653
  do
654
    {
655
      TapActionDRScan *dRScan = new TapActionDRScan (done, dRegIn, DUSEL_DR_LEN);
656
      tapActionQueue->write (dRScan);
657
      wait (*done);
658
      dRScan->getDRegOut (dRegOut);
659
      delete dRScan;
660
      status_ret = unpackBits (dRegOut, DUSEL_RESP_STATUS_OFF, DUSEL_RESP_STATUS_LEN);
661
      calc_recv_crc = crc32(dRegOut, DUSEL_RESP_STATUS_LEN, DUSEL_RESP_STATUS_OFF);
662
      recv_crc = bit_reverse_data(unpackBits (dRegOut, DUSEL_RESP_CRC_OFF, DUSEL_RESP_CRC_LEN),32);
663
    }
664
  while ((0 != status_ret) || ( calc_recv_crc != recv_crc));
665
 
666
  delete [] dRegIn;
667
  delete [] dRegOut;
668
  delete done;
669
 
670
}       // selectDebugModule()
671
 
672
 
673
//-----------------------------------------------------------------------------
674
//! Read a 32-bit value via the debug interface
675
 
676
//! @note Must be called from a SystemC thread, because of the use of wait()
677
 
678
//! @param[in] addr  The address of the register
679
 
680
//! @return  The register value read
681
//-----------------------------------------------------------------------------
682
uint32_t
683
DebugUnitSC::readJtagReg (uint32_t  addr)
684
{
685
  int  drLen;                   // Size of the data register
686
 
687
  uint32_t calc_recv_crc = 0, recv_crc, status_ret;
688
 
689
  drLen = 125; // Size of write command command (bigger than data read)
690
 
691
  // Initialize the register fields
692
  uint64_t *dRegIn  = new uint64_t [(drLen + 63) / 64];
693
  uint64_t *dRegOut = new uint64_t [(drLen + 63) / 64];
694
 
695
  // Write the READ command
696
  clearBits (dRegIn, drLen);
697
 
698
  packBits (dRegIn, 0, 1, 0);
699
  packBits (dRegIn, 0+1, 4, BITREV(0x2,4)); // We're writing a command
700
  packBits (dRegIn, 1+4, 4, BITREV(0x6,4)); // Access type, 0x6 = 32-bit READ
701
  packBits (dRegIn, 1+4+4, 32, BITREV(addr,32)); // Address
702
  packBits (dRegIn, 1+4+4+32, 16, BITREV(0x3,16)); // Length (always 32-bit,n=(32/8)-1=3)
703
  uint32_t crc32_send = crc32 (dRegIn, 1+4+4+32+16, 0);
704
  packBits (dRegIn, 1+4+4+32+16, 32, BITREV(crc32_send,32));
705
 
706
  // Allocate a SystemC completion event
707
  sc_event *done  = new sc_event();
708
 
709
  // Loop until status is OK and CRCs match.
710
  do
711
    {
712
      TapActionDRScan *dRScan = new TapActionDRScan (done, dRegIn, 125);
713
      tapActionQueue->write (dRScan);
714
      wait (*done);
715
      dRScan->getDRegOut (dRegOut);
716
      delete dRScan;
717
      status_ret = unpackBits (dRegOut,1+4+4+32+16+32,4);
718
      calc_recv_crc = crc32(dRegOut,4,1+4+4+32+16+32);
719
      recv_crc = BITREV(unpackBits (dRegOut,1+4+4+32+16+32+4,32),32);
720
    }
721
  while ((0 != status_ret) || ( calc_recv_crc != recv_crc));
722
 
723
  clearBits (dRegIn, drLen);
724
  packBits (dRegIn, 0, 1, 0);
725
  packBits (dRegIn, 0+1, 4, 0x0); // We're GO'ing command
726
  crc32_send = crc32 (dRegIn,1+4,0);
727
  packBits (dRegIn, 1+4, 32, BITREV(crc32_send,32)); // CRC
728
 
729
  uint32_t  result;
730
  // Loop until status is OK and CRCs match.
731
  do
732
    {
733
      TapActionDRScan *dRScan = new TapActionDRScan (done, dRegIn, (1+4+32+36+((3+1)*8)));
734
      tapActionQueue->write (dRScan);
735
      wait (*done);
736
      dRScan->getDRegOut (dRegOut);
737
      delete dRScan;
738
      status_ret = BITREV(unpackBits (dRegOut,1+4+32+((3+1)*8),4),4);
739
      if (status_ret)
740
        {
741
          printf("readJtagReg(): Addr: 0x%.8x Status err: 0x%x\n",addr,status_ret);
742
          result = 0;
743
          break;
744
        }
745
      calc_recv_crc = crc32(dRegOut,((3+1)*8)+4,1+4+32);
746
      recv_crc = BITREV(unpackBits (dRegOut,1+4+32+((3+1)*8)+4,32),32);
747
      result = BITREV(unpackBits (dRegOut, (1+4+32), ((3+1)*8)),32);
748
 
749
    }
750
  while ((0 != status_ret) || ( calc_recv_crc != recv_crc));
751
 
752
  // All done
753
 
754
  delete [] dRegIn;
755
  delete [] dRegOut;
756
  delete  done;
757
  return  result;
758
 
759
}       // readJtagReg ()
760
 
761
 
762
//-----------------------------------------------------------------------------
763
//! Write a 32-bit value via the debug interface
764
 
765
//! @note Must be called from a SystemC thread, because of the use of wait()
766
 
767
//! @param[in] addr  The address of the register
768
//! @param[in] data  The register data to write
769
//-----------------------------------------------------------------------------
770
void
771
DebugUnitSC::writeJtagReg (uint32_t  addr,
772
                           uint32_t  data)
773
{
774
  int  drLen;                   // Size of the data register
775
 
776
  uint32_t calc_recv_crc = 0, recv_crc, status_ret;
777
 
778
  drLen = 125; // Size of write command command (bigger than data read)
779
 
780
  // Initialize the register fields
781
  uint64_t *dRegIn  = new uint64_t [(drLen + 63) / 64];
782
  uint64_t *dRegOut = new uint64_t [(drLen + 63) / 64];
783
 
784
  // Write the READ command
785
  clearBits (dRegIn, drLen);
786
 
787
  packBits (dRegIn, 0, 1, 0);
788
  packBits (dRegIn, 0+1, 4, BITREV(0x2,4)); // We're writing a command
789
  packBits (dRegIn, 1+4, 4, BITREV(0x2,4)); // Access type, 0x2 = 32-bit WRITE
790
  packBits (dRegIn, 1+4+4, 32, BITREV(addr,32)); // Address
791
  packBits (dRegIn, 1+4+4+32, 16, BITREV(0x3,16)); // Length (always 32-bit,n=(32/8)-1=3)
792
  uint32_t crc32_send = crc32 (dRegIn, 1+4+4+32+16, 0);
793
  packBits (dRegIn, 1+4+4+32+16, 32, BITREV(crc32_send,32));
794
 
795
  // Allocate a SystemC completion event
796
  sc_event *done  = new sc_event();
797
 
798
  // Loop until status is OK and CRCs match.
799
  do
800
    {
801
      TapActionDRScan *dRScan = new TapActionDRScan (done, dRegIn, 125);
802
      tapActionQueue->write (dRScan);
803
      wait (*done);
804
      dRScan->getDRegOut (dRegOut);
805
      delete dRScan;
806
      status_ret = unpackBits (dRegOut,1+4+4+32+16+32,4);
807
      calc_recv_crc = crc32(dRegOut,4,1+4+4+32+16+32);
808
      recv_crc = BITREV(unpackBits (dRegOut,1+4+4+32+16+32+4,32),32);
809
    }
810
  while ((0 != status_ret) || ( calc_recv_crc != recv_crc));
811
 
812
  clearBits (dRegIn, drLen);
813
  packBits (dRegIn, 0, 1, 0);
814
  packBits (dRegIn, 0+1, 4, 0x0); // We're GO'ing command
815
  packBits (dRegIn, 0+1+4, 32, BITREV(data,32)); // Add in data
816
  crc32_send = crc32 (dRegIn,1+4+32,0);
817
  packBits (dRegIn, 1+4+32, 32, BITREV(crc32_send,32)); // CRC
818
 
819
  // Loop until status is OK and CRCs match.
820
  do
821
    {
822
      TapActionDRScan *dRScan = new TapActionDRScan (done, dRegIn, (1+4+((3+1)*8)+32+36));
823
      tapActionQueue->write (dRScan);
824
      wait (*done);
825
      dRScan->getDRegOut (dRegOut);
826
      delete dRScan;
827
      status_ret = unpackBits (dRegOut,1+4+32+32,4);
828
      calc_recv_crc = crc32(dRegOut,4,1+4+32+32);
829
      recv_crc = BITREV(unpackBits (dRegOut,1+4+32+32+4,32),32);
830
    }
831
  while ((0 != status_ret) || ( calc_recv_crc != recv_crc));
832
 
833
  delete [] dRegIn;
834
  delete [] dRegOut;
835
  delete  done;
836
 
837
}       // writeJtagReg ()
838
 
839
 
840
//-----------------------------------------------------------------------------
841
//! Clear the bits in a data register
842
 
843
//! We always clear whole 64-bit words, not just the minimum number of
844
//! bytes. It saves all sorts of confusion when debugging code.
845
 
846
//! @note It is the caller's responsibility to make sure the date register
847
//!       array is large enough.
848
 
849
//! @param[in,out] regArray  The data register to clear
850
//! @param[in]     regBits  Size of the data register (in bits)
851
//-----------------------------------------------------------------------------
852
void
853
DebugUnitSC::clearBits (uint64_t  regArray[],
854
                        int       regBits)
855
{
856
  memset ((char *)regArray, 0, ((regBits + 63) / 64) * 8);
857
 
858
}       // clearBits ()
859
 
860
 
861
//-----------------------------------------------------------------------------
862
//! Set a bit field in a data register
863
 
864
//! The field is cleared, the supplied value masked and then ored into the
865
//! vector.
866
 
867
//! @note It is the caller's responsibility to make sure the date register
868
//!       array is large enough.
869
 
870
//! @param[in,out] regArray     The data register
871
//! @param[in]     fieldOffset  Start of the field (in bits)
872
//! @param[in]     fieldBits    Size of the field (in bits)
873
//! @param[in]     fieldVal     Value to set in the field
874
//-----------------------------------------------------------------------------
875
void
876
DebugUnitSC::packBits (uint64_t  regArray[],
877
                       int       fieldOffset,
878
                       int       fieldBits,
879
                       uint64_t  fieldVal)
880
{
881
  fieldVal &= (1ULL << fieldBits) - 1ULL;       // Mask the supplied value
882
 
883
  int  startWord =  fieldOffset / 64;
884
  int  endWord   = (fieldOffset + fieldBits - 1) / 64;
885
 
886
  fieldOffset = fieldOffset % 64;               // Now refers to target word
887
 
888
  // Deal with the startWord. Get enough bits for the mask and put them in the
889
  // right place
890
  uint64_t startMask   = ((1ULL << fieldBits) - 1ULL) << fieldOffset;
891
 
892
  regArray[startWord] &= ~startMask;
893
  regArray[startWord] |= fieldVal << fieldOffset;
894
 
895
  // If we were all in one word, we can give up now.
896
  if (startWord == endWord)
897
    {
898
      return;
899
    }
900
 
901
  // Deal with the endWord. Get enough bits for the mask. No need to shift
902
  // these up - they're always at the bottom of the word
903
  int       bitsToDo = (fieldOffset + fieldBits) % 64;
904
  uint64_t  endMask  = (1ULL << bitsToDo) - 1ULL;
905
 
906
  regArray[endWord] &= ~endMask;
907
  regArray[endWord] |= fieldVal >> (fieldBits - bitsToDo);
908
 
909
}       // packBits ()
910
 
911
 
912
//-----------------------------------------------------------------------------
913
//! Extract a bit field from a data register
914
 
915
//! The field is cleared, the supplied value masked and then ored into the
916
//! vector.
917
 
918
//! @note It is the caller's responsibility to make sure the date register
919
//!       array is large enough.
920
 
921
//! @param[in,out] regArray     The data register
922
//! @param[in]     fieldOffset  Start of the field (in bits)
923
//! @param[in]     fieldBits    Size of the field (in bits)
924
 
925
//! @return  The value in the field
926
//-----------------------------------------------------------------------------
927
uint64_t
928
DebugUnitSC::unpackBits (uint64_t  regArray[],
929
                         int       fieldOffset,
930
                         int       fieldBits)
931
{
932
  int  startWord = fieldOffset / 64;
933
  int  endWord   = (fieldOffset + fieldBits - 1) / 64;
934
 
935
  fieldOffset = fieldOffset % 64;               // Now refers to target word
936
 
937
  // Deal with the startWord. Get enough bits for the mask and put them in the
938
  // right place
939
  uint64_t  startMask = ((1ULL << fieldBits) - 1ULL) << fieldOffset;
940
  uint64_t  res       = (regArray[startWord] & startMask) >> fieldOffset;
941
 
942
  // If we were all in one word, we can give up now.
943
  if (startWord == endWord)
944
    {
945
      res &= (1ULL << fieldBits) - 1ULL;        // Mask off any unwanted bits
946
      return  res;
947
    }
948
 
949
  // Deal with the endWord. Get enough bits for the mask. No need to shift
950
  // these up - they're always at the bottom of the word
951
  int       bitsToDo = (fieldOffset + fieldBits) % 64;
952
  uint64_t  endMask  = (1ULL << bitsToDo) - 1ULL;
953
 
954
  res = res | ((regArray[endWord] & endMask) << (fieldBits - bitsToDo));
955
  res &= (1ULL << fieldBits) - 1ULL;            // Mask off any unwanted bits
956
  return  res;
957
 
958
}       // unpackBits ()
959
 
960
 
961
//-----------------------------------------------------------------------------
962
//! Compute CRC-8-ATM
963
 
964
//! The data is in an array of uint64_t, for which we use the first size bits
965
//! to compute the CRC.
966
 
967
//! @Note I am using the same algorithm as the ORPSoC debug unit, but I
968
//!       believe its function is broken! I don't believe the data bit should
969
//!       feature in the computation of bits 2 & 1 of the new CRC.
970
 
971
//! @Note I've realized that this is an algorithm for LSB first, so maybe it
972
//!       is correct!
973
 
974
//! @param dataArray  The array of data whose CRC is desired
975
//! @param size       The number of bits in the data
976
//-----------------------------------------------------------------------------
977
uint8_t
978
DebugUnitSC::crc8 (uint64_t  dataArray[],
979
                   int       size)
980
{
981
  uint8_t    crc = 0;
982
 
983
  for (int  i = 0; i < size; i++)
984
    {
985
      uint8_t  d       = (dataArray[i / 64] >> (i % 64)) & 1;
986
      uint8_t  oldCrc7 = (crc >> 7) & 1;
987
      uint8_t  oldCrc1 = (crc >> 1) & 1;
988
      uint8_t  oldCrc0 = (crc >> 0) & 1;
989
      uint8_t  newCrc2 = d ^ oldCrc1 ^ oldCrc7;         // Why d?
990
      uint8_t  newCrc1 = d ^ oldCrc0 ^ oldCrc7;         // Why d?
991
      uint8_t  newCrc0 = d ^ oldCrc7;
992
 
993
      crc = ((crc << 1) & 0xf8) | (newCrc2 << 2) | (newCrc1 << 1) | newCrc0;
994
    }
995
 
996
  return crc;
997
 
998
}       // crc8 ()
999
 
1000
/* Crc of current read or written data.  */
1001
uint32_t crc_r, crc_w = 0;
1002
 
1003
/* Generates new crc, sending in new bit input_bit */
1004
uint32_t
1005
DebugUnitSC::crc32(uint64_t dataArray[],
1006
                   int size,
1007
                   int offset)
1008
{
1009
  uint32_t crc = 0xffffffff;
1010
  for (int  i = offset; i < size+offset; i++)
1011
    {
1012
      uint32_t d = ((dataArray[i / 64] >> (i % 64)) & 1) ? 0xfffffff : 0x0000000;
1013
      uint32_t crc_32 = ((crc >> 31)&1) ? 0xfffffff : 0x0000000;
1014
      crc <<= 1;
1015
      crc = crc ^ ((d ^ crc_32) & DBG_CRC32_POLY);
1016
    }
1017
 
1018
  return crc;
1019
}
1020
 
1021
uint32_t
1022
DebugUnitSC::bit_reverse_swar_2(uint32_t x)
1023
{
1024
  return (((x&0xaaaaaaaa)>>1)|((x&0x55555555)<<1));
1025
}
1026
uint32_t
1027
DebugUnitSC::bit_reverse_swar_4(uint32_t x)
1028
{
1029
  x=(((x&0xaaaaaaaa)>>1)|((x&0x55555555)<<1));
1030
  x=(((x&0xcccccccc)>>2)|((x&0x33333333)<<2));
1031
  return x;
1032
}
1033
uint32_t
1034
DebugUnitSC::bit_reverse_swar_8(uint32_t x)
1035
{
1036
  x=(((x&0xaaaaaaaa)>>1)|((x&0x55555555)<<1));
1037
  x=(((x&0xcccccccc)>>2)|((x&0x33333333)<<2));
1038
  x=(((x&0xf0f0f0f0)>>4)|((x&0x0f0f0f0f)<<4));
1039
  return x;
1040
}
1041
uint32_t
1042
DebugUnitSC::bit_reverse_swar_16(uint32_t x)
1043
{
1044
  x=(((x&0xaaaaaaaa)>>1)|((x&0x55555555)<<1));
1045
  x=(((x&0xcccccccc)>>2)|((x&0x33333333)<<2));
1046
  x=(((x&0xf0f0f0f0)>>4)|((x&0x0f0f0f0f)<<4));
1047
  x=(((x&0xff00ff00)>>8)|((x&0x00ff00ff)<<8));
1048
  return x;
1049
}
1050
uint32_t
1051
DebugUnitSC::bit_reverse_swar_32(uint32_t x)
1052
{
1053
  x=(((x&0xaaaaaaaa)>>1)|((x&0x55555555)<<1));
1054
  x=(((x&0xcccccccc)>>2)|((x&0x33333333)<<2));
1055
  x=(((x&0xf0f0f0f0)>>4)|((x&0x0f0f0f0f)<<4));
1056
  x=(((x&0xff00ff00)>>8)|((x&0x00ff00ff)<<8));
1057
  x=(((x&0xffff0000)>>16)|((x&0x0000ffff)<<16)); // We could be on 64-bit arch!
1058
  return x;
1059
}
1060
 
1061
uint32_t
1062
DebugUnitSC::bit_reverse_data(uint32_t data, int length){
1063
  if (length == 2) return bit_reverse_swar_2(data);
1064
  if (length == 4) return bit_reverse_swar_4(data);
1065
  if (length == 8) return bit_reverse_swar_8(data);
1066
  if (length == 16) return bit_reverse_swar_16(data);
1067
  if (length == 32) return bit_reverse_swar_32(data);
1068
  // Long and laborious way - hopefully never gets called anymore!
1069
  uint32_t reverse=0;
1070
  for (int i=0;i<length;i++) reverse |= (((data>>i)&1)<<(length-1-i));
1071
  return reverse;
1072
}

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