URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [OrpsocAccess.cpp] - Blame information for rev 590

Go to most recent revision | Details | Compare with Previous | View Log


// ----------------------------------------------------------------------------
 
// Access functions for the ORPSoC Verilator model: implementation
 
// Copyright (C) 2008  Embecosm Limited <info@embecosm.com>
 
// Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
// Contributor Julius Baxter <jb@orsoc.se>
 
// This file is part of the cycle accurate model of the OpenRISC 1000 based
// system-on-chip, ORPSoC, built using Verilator.
 
// This program is free software: you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or (at your
// option) any later version.
 
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public
// License for more details.
 
// You should have received a copy of the GNU Lesser General Public License
// along with this program.  If not, see <http://www.gnu.org/licenses/>.
 
// ----------------------------------------------------------------------------
 
// $Id: OrpsocAccess.cpp 303 2009-02-16 11:20:17Z jeremy $
 
#include "OrpsocAccess.h"
 
#include "Vorpsoc_top.h"
#include "Vorpsoc_top_orpsoc_top.h"
#include "Vorpsoc_top_or1200_top.h"
#include "Vorpsoc_top_or1200_cpu.h"
#include "Vorpsoc_top_or1200_ctrl.h"
#include "Vorpsoc_top_or1200_except.h"
#include "Vorpsoc_top_or1200_sprs.h"
#include "Vorpsoc_top_or1200_rf.h"
#include "Vorpsoc_top_or1200_dpram.h"
// Need RAM instantiation has parameters after module name
// Include for ram_wb
#include "Vorpsoc_top_ram_wb__A20_D20_M800000_MB17.h"
// Include for ram_wb_b3
#include "Vorpsoc_top_ram_wb_b3__pi3.h"
 
//! Constructor for the ORPSoC access class
 
//! Initializes the pointers to the various module instances of interest
//! within the Verilator model.
 
//! @param[in] orpsoc  The SystemC Verilated ORPSoC instance
 
OrpsocAccess::OrpsocAccess(Vorpsoc_top * orpsoc_top)
{
        // Assign processor accessor objects
        or1200_ctrl = orpsoc_top->v->or1200_top0->or1200_cpu->or1200_ctrl;
        or1200_except = orpsoc_top->v->or1200_top0->or1200_cpu->or1200_except;
        or1200_sprs = orpsoc_top->v->or1200_top0->or1200_cpu->or1200_sprs;
        rf_a = orpsoc_top->v->or1200_top0->or1200_cpu->or1200_rf->rf_a;
        // Assign main memory accessor objects
        // For old ram_wb: ram_wb_sc_sw = orpsoc_top->v->ram_wb0->ram0;
        //ram_wb_sc_sw = orpsoc_top->v->wb_ram_b3_0;
        wishbone_ram = orpsoc_top->v->ram_wb0->ram_wb_b3_0;
 
        // Assign arbiter accessor object
        //wb_arbiter = orpsoc_top->v->wb_conbus;
 
}                               // OrpsocAccess ()
 
//! Access for the ex_freeze signal
 
//! @return  The value of the or1200_ctrl.ex_freeze signal
 
bool OrpsocAccess::getExFreeze()
{
        return or1200_ctrl->ex_freeze;
 
}                               // getExFreeze ()
 
//! Access for the wb_freeze signal
 
//! @return  The value of the or1200_ctrl.wb_freeze signal
 
bool OrpsocAccess::getWbFreeze()
{
        return or1200_ctrl->wb_freeze;
 
}                               // getWbFreeze ()
 
//! Access for the except_flushpipe signal
 
//! @return  The value of the or1200_except.except_flushpipe signal
 
bool OrpsocAccess::getExceptFlushpipe()
{
        return or1200_except->except_flushpipe;
 
}                               // getExceptFlushpipe ()
 
//! Access for the ex_dslot signal
 
//! @return  The value of the or1200_except.ex_dslot signalfac
 
bool OrpsocAccess::getExDslot()
{
        return or1200_except->ex_dslot;
 
}                               // getExDslot ()
 
//! Access for the except_type value
 
//! @return  The value of the or1200_except.except_type register
 
uint32_t OrpsocAccess::getExceptType()
{
        return (or1200_except->get_except_type) ();
 
}                               // getExceptType ()
 
//! Access for the id_pc register
 
//! @return  The value of the or1200_except.id_pc register
 
uint32_t OrpsocAccess::getIdPC()
{
        return (or1200_except->get_id_pc) ();
 
}                               // getIdPC ()
 
//! Access for the ex_pc register
 
//! @return  The value of the or1200_except.id_ex register
 
uint32_t OrpsocAccess::getExPC()
{
        return (or1200_except->get_ex_pc) ();
 
}                               // getExPC ()
 
//! Access for the wb_pc register
 
//! @return  The value of the or1200_except.wb_pc register
 
uint32_t OrpsocAccess::getWbPC()
{
        return (or1200_except->get_wb_pc) ();
 
}                               // getWbPC ()
 
//! Access for the id_insn register
 
//! @return  The value of the or1200_ctrl.wb_insn register
 
uint32_t OrpsocAccess::getIdInsn()
{
        return (or1200_ctrl->get_id_insn) ();
 
}                               // getIdInsn ()
 
//! Access for the ex_insn register
 
//! @return  The value of the or1200_ctrl.ex_insn register
 
uint32_t OrpsocAccess::getExInsn()
{
        return (or1200_ctrl->get_ex_insn) ();
 
}                               // getExInsn ()
 
//! Access for the wb_insn register
 
//! @return  The value of the or1200_ctrl.wb_insn register
 
uint32_t OrpsocAccess::getWbInsn()
{
        return (or1200_ctrl->get_wb_insn) ();
 
}                               // getWbInsn ()
 
//! Access the Wishbone SRAM memory
 
//! @return  The value of the 32-bit memory word at addr
 
uint32_t OrpsocAccess::get_mem32(uint32_t addr)
{
        return (wishbone_ram->get_mem32) (addr / 4);
 
}                               // get_mem32 ()
 
//! Access a byte from the Wishbone SRAM memory
 
//! @return  The value of the memory byte at addr
 
uint8_t OrpsocAccess::get_mem8(uint32_t addr)
{
 
        uint32_t word;
        static uint32_t cached_word;
        static uint32_t cached_word_addr = 0xffffffff;
        int sel = addr & 0x3;   // Remember which byte we want
        addr = addr / 4;
        if (addr != cached_word_addr) {
                cached_word_addr = addr;
                // Convert address to word number here
                word = (wishbone_ram->get_mem8) (addr);
                cached_word = word;
        } else
                word = cached_word;
 
        switch (sel) {
                /* Big endian word expected */
        case 0:
                return ((word >> 24) & 0xff);
                break;
        case 1:
                return ((word >> 16) & 0xff);
                break;
        case 2:
                return ((word >> 8) & 0xff);
                break;
        case 3:
                return ((word >> 0) & 0xff);
                break;
        default:
                return 0;
        }
 
}                               // get_mem8 ()
 
//! Write value to the Wishbone SRAM memory
 
void OrpsocAccess::set_mem32(uint32_t addr, uint32_t data)
{
        (wishbone_ram->set_mem32) (addr / 4, data);
 
}                               // set_mem32 ()
 
//! Trigger the $readmemh() system call
 
void OrpsocAccess::do_ram_readmemh(void)
{
        (wishbone_ram->do_readmemh) ();
 
}                               // do_ram_readmemh ()
 
//! Access for the OR1200 GPRs
 
//! These are extracted from memory using the Verilog function
 
//! @param[in] regNum  The GPR whose value is wanted
 
//! @return            The value of the GPR
 
uint32_t OrpsocAccess::getGpr(uint32_t regNum)
{
        return (rf_a->get_gpr) (regNum);
 
}                               // getGpr ()
 
//! Access for the OR1200 GPRs
 
//! These are extracted from memory using the Verilog function
 
//! @param[in] regNum  The GPR whose value is wanted
//! @param[in] value   The value of GPR to write
 
void OrpsocAccess::setGpr(uint32_t regNum, uint32_t value)
{
        (rf_a->set_gpr) (regNum, value);
 
}                               // getGpr ()
 
//! Access for the sr register
 
//! @return  The value of the or1200_sprs.sr register
 
uint32_t OrpsocAccess::getSprSr()
{
        return (or1200_sprs->get_sr) ();
 
}                               // getSprSr ()
 
//! Access for the epcr register
 
//! @return  The value of the or1200_sprs.epcr register
 
uint32_t OrpsocAccess::getSprEpcr()
{
        return (or1200_sprs->get_epcr) ();
 
}                               // getSprEpcr ()
 
//! Access for the eear register
 
//! @return  The value of the or1200_sprs.eear register
 
uint32_t OrpsocAccess::getSprEear()
{
        return (or1200_sprs->get_eear) ();
 
}                               // getSprEear ()
 
//! Access for the esr register
 
//! @return  The value of the or1200_sprs.esr register
 
uint32_t OrpsocAccess::getSprEsr()
{
        return (or1200_sprs->get_esr) ();
 
}                               // getSprEsr ()
 
/*
//! Access for the arbiter's grant signal
 
//! @return  The value of the wb_conmax_top.arb signal
 
uint8_t
OrpsocAccess::getWbArbGrant ()
{
  return  (wb_arbiter->get_gnt) ();
 
}       // getWbArbGrant ()
 
//! Arbiter master[mast_num] access functions
 
//! Access for the arbiter's master[mast_num] data in signal
 
//! @return  The value of the wb_conmax_top.m_dat_i[mast_num]
 
uint32_t
OrpsocAccess::getWbArbMastDatI (uint32_t mast_num)
{
  return  (wb_arbiter->get_m_dat_i) (mast_num);
 
}       // getWbArbMastDatI ()
 
//! Access for the arbiter's master[mast_num] data out signal
 
//! @return  The value of the wb_conmax_top.m_dat_o[mast_num]
 
uint32_t
OrpsocAccess::getWbArbMastDatO (uint32_t mast_num)
{
  return  (wb_arbiter->get_m_dat_o) (mast_num);
 
}       // getWbArbMastDatO ()
 
//! Access for the arbiter's master[mast_num] data out
 
//! @return  The value of the wb_conmax_top.m_adr_i[mast_num]
 
uint32_t
OrpsocAccess::getWbArbMastAdrI (uint32_t mast_num)
{
  return  (wb_arbiter->get_m_adr_i) (mast_num);
 
}       // getWbArbMastAdrI ()
 
//! Access for the arbiter's master[mast_num] select signal
 
//! @return  The value of the wb_conmax_top.m_sel_i[mast_num]
 
uint8_t
OrpsocAccess::getWbArbMastSelI (uint32_t mast_num)
{
  return  (wb_arbiter->get_m_sel_i) (mast_num);
 
}       // getWbArbMastSelI ()
 
//! Access for the arbiter's master[mast_num] decoded slave select signal
 
//! @return  The value of the wb_conmax_top.m_ssel_dec[mast_num]
 
uint8_t
OrpsocAccess::getWbArbMastSlaveSelDecoded (uint32_t mast_num)
{
  return  (wb_arbiter->get_m_ssel_dec) (mast_num);
 
}       // getWbArbMastSlaveSelDecoded ()
 
//! Access for the arbiter's master[mast_num] write enable signal
 
//! @return  The value of the wb_conmax_top.m_we_i[mast_num]
 
bool
OrpsocAccess::getWbArbMastWeI (uint32_t mast_num)
{
  return  (wb_arbiter->get_m_we_i) (mast_num);
 
}       // getWbArbMastWeI ()
 
//! Access for the arbiter's master[mast_num] cycle input signal
 
//! @return  The value of the wb_conmax_top.m_cyc_i[mast_num]
 
bool
OrpsocAccess::getWbArbMastCycI (uint32_t mast_num)
{
  return  (wb_arbiter->get_m_cyc_i) (mast_num);
 
}       // getWbArbMastCycI ()
 
//! Access for the arbiter's master[mast_num] strobe input signal
 
//! @return  The value of the wb_conmax_top.m_stb_i[mast_num]
 
bool
OrpsocAccess::getWbArbMastStbI (uint32_t mast_num)
{
  return  (wb_arbiter->get_m_stb_i) (mast_num);
 
}       // getWbArbMastStbI ()
 
//! Access for the arbiter's master[mast_num] ACK output signal
 
//! @return  The value of the wb_conmax_top.m_ack_o[mast_num]
 
bool
OrpsocAccess::getWbArbMastAckO (uint32_t mast_num)
{
  return  (wb_arbiter->get_m_ack_o) (mast_num);
 
}       // getWbArbMastAckO ()
 
//! Access for the arbiter's master[mast_num] error input signal
 
//! @return  The value of the wb_conmax_top.m_err_o[mast_num]
 
bool
OrpsocAccess::getWbArbMastErrO (uint32_t mast_num)
{
  return  (wb_arbiter->get_m_err_o) (mast_num);
 
}       // getWbArbMastErrO ()
 
*/

Line No.	Rev	Author	Line
1	6	julius	`// ----------------------------------------------------------------------------`
2
3			`// Access functions for the ORPSoC Verilator model: implementation`
4
5			`// Copyright (C) 2008 Embecosm Limited <info@embecosm.com>`
6
7			`// Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>`
8	44	julius	`// Contributor Julius Baxter <jb@orsoc.se>`
9	6	julius
10			`// This file is part of the cycle accurate model of the OpenRISC 1000 based`
11			`// system-on-chip, ORPSoC, built using Verilator.`
12
13			`// This program is free software: you can redistribute it and/or modify it`
14			`// under the terms of the GNU Lesser General Public License as published by`
15			`// the Free Software Foundation, either version 3 of the License, or (at your`
16			`// option) any later version.`
17
18			`// This program is distributed in the hope that it will be useful, but WITHOUT`
19			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
20			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public`
21			`// License for more details.`
22
23			`// You should have received a copy of the GNU Lesser General Public License`
24			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
25
26			`// ----------------------------------------------------------------------------`
27
28			`// $Id: OrpsocAccess.cpp 303 2009-02-16 11:20:17Z jeremy $`
29
30			`#include "OrpsocAccess.h"`
31
32			`#include "Vorpsoc_top.h"`
33			`#include "Vorpsoc_top_orpsoc_top.h"`
34			`#include "Vorpsoc_top_or1200_top.h"`
35			`#include "Vorpsoc_top_or1200_cpu.h"`
36			`#include "Vorpsoc_top_or1200_ctrl.h"`
37	44	julius	`#include "Vorpsoc_top_or1200_except.h"`
38			`#include "Vorpsoc_top_or1200_sprs.h"`
39	6	julius	`#include "Vorpsoc_top_or1200_rf.h"`
40			`#include "Vorpsoc_top_or1200_dpram.h"`
41	353	julius	`// Need RAM instantiation has parameters after module name`
42	439	julius	`// Include for ram_wb`
43			`#include "Vorpsoc_top_ram_wb__A20_D20_M800000_MB17.h"`
44			`// Include for ram_wb_b3`
45			`#include "Vorpsoc_top_ram_wb_b3__pi3.h"`
46	6	julius
47			`//! Constructor for the ORPSoC access class`
48
49			`//! Initializes the pointers to the various module instances of interest`
50			`//! within the Verilator model.`
51
52			`//! @param[in] orpsoc The SystemC Verilated ORPSoC instance`
53
54	462	julius	`OrpsocAccess::OrpsocAccess(Vorpsoc_top * orpsoc_top)`
55	6	julius	`{`
56	462	julius	`// Assign processor accessor objects`
57			`or1200_ctrl = orpsoc_top->v->or1200_top0->or1200_cpu->or1200_ctrl;`
58			`or1200_except = orpsoc_top->v->or1200_top0->or1200_cpu->or1200_except;`
59			`or1200_sprs = orpsoc_top->v->or1200_top0->or1200_cpu->or1200_sprs;`
60			`rf_a = orpsoc_top->v->or1200_top0->or1200_cpu->or1200_rf->rf_a;`
61			`// Assign main memory accessor objects`
62			`// For old ram_wb: ram_wb_sc_sw = orpsoc_top->v->ram_wb0->ram0;`
63			`//ram_wb_sc_sw = orpsoc_top->v->wb_ram_b3_0;`
64			`wishbone_ram = orpsoc_top->v->ram_wb0->ram_wb_b3_0;`
65	353	julius
66	462	julius	`// Assign arbiter accessor object`
67			`//wb_arbiter = orpsoc_top->v->wb_conbus;`
68	6	julius
69	462	julius	`} // OrpsocAccess ()`
70	6	julius
71	51	julius	`//! Access for the ex_freeze signal`
72	6	julius
73	51	julius	`//! @return The value of the or1200_ctrl.ex_freeze signal`
74
75	462	julius	`bool OrpsocAccess::getExFreeze()`
76	51	julius	`{`
77	462	julius	`return or1200_ctrl->ex_freeze;`
78	51	julius
79	462	julius	`} // getExFreeze ()`
80	51	julius
81	6	julius	`//! Access for the wb_freeze signal`
82
83			`//! @return The value of the or1200_ctrl.wb_freeze signal`
84
85	462	julius	`bool OrpsocAccess::getWbFreeze()`
86	6	julius	`{`
87	462	julius	`return or1200_ctrl->wb_freeze;`
88	6	julius
89	462	julius	`} // getWbFreeze ()`
90	6	julius
91	44	julius	`//! Access for the except_flushpipe signal`
92	6	julius
93	44	julius	`//! @return The value of the or1200_except.except_flushpipe signal`
94
95	462	julius	`bool OrpsocAccess::getExceptFlushpipe()`
96	44	julius	`{`
97	462	julius	`return or1200_except->except_flushpipe;`
98	44	julius
99	462	julius	`} // getExceptFlushpipe ()`
100	44	julius
101			`//! Access for the ex_dslot signal`
102
103			`//! @return The value of the or1200_except.ex_dslot signalfac`
104
105	462	julius	`bool OrpsocAccess::getExDslot()`
106	44	julius	`{`
107	462	julius	`return or1200_except->ex_dslot;`
108	44	julius
109	462	julius	`} // getExDslot ()`
110	44	julius
111	51	julius	`//! Access for the except_type value`
112
113			`//! @return The value of the or1200_except.except_type register`
114
115	462	julius	`uint32_t OrpsocAccess::getExceptType()`
116	51	julius	`{`
117	462	julius	`return (or1200_except->get_except_type) ();`
118	51	julius
119	462	julius	`} // getExceptType ()`
120	51	julius
121	49	julius	`//! Access for the id_pc register`
122
123			`//! @return The value of the or1200_except.id_pc register`
124
125	462	julius	`uint32_t OrpsocAccess::getIdPC()`
126	49	julius	`{`
127	462	julius	`return (or1200_except->get_id_pc) ();`
128	49	julius
129	462	julius	`} // getIdPC ()`
130	49	julius
131	51	julius	`//! Access for the ex_pc register`
132
133			`//! @return The value of the or1200_except.id_ex register`
134
135	462	julius	`uint32_t OrpsocAccess::getExPC()`
136	51	julius	`{`
137	462	julius	`return (or1200_except->get_ex_pc) ();`
138	51	julius
139	462	julius	`} // getExPC ()`
140	51	julius
141	44	julius	`//! Access for the wb_pc register`
142
143	49	julius	`//! @return The value of the or1200_except.wb_pc register`
144	44	julius
145	462	julius	`uint32_t OrpsocAccess::getWbPC()`
146	44	julius	`{`
147	462	julius	`return (or1200_except->get_wb_pc) ();`
148	44	julius
149	462	julius	`} // getWbPC ()`
150	44	julius
151	51	julius	`//! Access for the id_insn register`
152
153			`//! @return The value of the or1200_ctrl.wb_insn register`
154
155	462	julius	`uint32_t OrpsocAccess::getIdInsn()`
156	51	julius	`{`
157	462	julius	`return (or1200_ctrl->get_id_insn) ();`
158	51	julius
159	462	julius	`} // getIdInsn ()`
160	51	julius
161			`//! Access for the ex_insn register`
162
163			`//! @return The value of the or1200_ctrl.ex_insn register`
164
165	462	julius	`uint32_t OrpsocAccess::getExInsn()`
166	51	julius	`{`
167	462	julius	`return (or1200_ctrl->get_ex_insn) ();`
168	51	julius
169	462	julius	`} // getExInsn ()`
170	51	julius
171	6	julius	`//! Access for the wb_insn register`
172
173			`//! @return The value of the or1200_ctrl.wb_insn register`
174
175	462	julius	`uint32_t OrpsocAccess::getWbInsn()`
176	6	julius	`{`
177	462	julius	`return (or1200_ctrl->get_wb_insn) ();`
178	6	julius
179	462	julius	`} // getWbInsn ()`
180	6	julius
181	51	julius	`//! Access the Wishbone SRAM memory`
182	6	julius
183	66	julius	`//! @return The value of the 32-bit memory word at addr`
184	49	julius
185	462	julius	`uint32_t OrpsocAccess::get_mem32(uint32_t addr)`
186	49	julius	`{`
187	462	julius	`return (wishbone_ram->get_mem32) (addr / 4);`
188	49	julius
189	462	julius	`} // get_mem32 ()`
190	49	julius
191	66	julius	`//! Access a byte from the Wishbone SRAM memory`
192
193			`//! @return The value of the memory byte at addr`
194
195	462	julius	`uint8_t OrpsocAccess::get_mem8(uint32_t addr)`
196	66	julius	`{`
197
198	462	julius	`uint32_t word;`
199			`static uint32_t cached_word;`
200			`static uint32_t cached_word_addr = 0xffffffff;`
201			`int sel = addr & 0x3; // Remember which byte we want`
202			`addr = addr / 4;`
203			`if (addr != cached_word_addr) {`
204			`cached_word_addr = addr;`
205			`// Convert address to word number here`
206			`word = (wishbone_ram->get_mem8) (addr);`
207			`cached_word = word;`
208			`} else`
209			`word = cached_word;`
210	66	julius
211	462	julius	`switch (sel) {`
212			`/* Big endian word expected */`
213			`case 0:`
214			`return ((word >> 24) & 0xff);`
215			`break;`
216			`case 1:`
217			`return ((word >> 16) & 0xff);`
218			`break;`
219			`case 2:`
220			`return ((word >> 8) & 0xff);`
221			`break;`
222			`case 3:`
223			`return ((word >> 0) & 0xff);`
224			`break;`
225			`default:`
226			`return 0;`
227			`}`
228	66	julius
229	462	julius	`} // get_mem8 ()`
230	66	julius
231	51	julius	`//! Write value to the Wishbone SRAM memory`
232
233	462	julius	`void OrpsocAccess::set_mem32(uint32_t addr, uint32_t data)`
234	51	julius	`{`
235	462	julius	`(wishbone_ram->set_mem32) (addr / 4, data);`
236	51	julius
237	462	julius	`} // set_mem32 ()`
238	51	julius
239			`//! Trigger the $readmemh() system call`
240
241	462	julius	`void OrpsocAccess::do_ram_readmemh(void)`
242	51	julius	`{`
243	462	julius	`(wishbone_ram->do_readmemh) ();`
244	51	julius
245	462	julius	`} // do_ram_readmemh ()`
246	51	julius
247	6	julius	`//! Access for the OR1200 GPRs`
248
249			`//! These are extracted from memory using the Verilog function`
250
251			`//! @param[in] regNum The GPR whose value is wanted`
252
253			`//! @return The value of the GPR`
254
255	462	julius	`uint32_t OrpsocAccess::getGpr(uint32_t regNum)`
256	6	julius	`{`
257	462	julius	`return (rf_a->get_gpr) (regNum);`
258	6	julius
259	462	julius	`} // getGpr ()`
260	44	julius
261	462	julius	`//! Access for the OR1200 GPRs`
262	44	julius
263	462	julius	`//! These are extracted from memory using the Verilog function`
264
265			`//! @param[in] regNum The GPR whose value is wanted`
266			`//! @param[in] value The value of GPR to write`
267
268			`void OrpsocAccess::setGpr(uint32_t regNum, uint32_t value)`
269			`{`
270			`(rf_a->set_gpr) (regNum, value);`
271
272			`} // getGpr ()`
273
274	44	julius	`//! Access for the sr register`
275
276			`//! @return The value of the or1200_sprs.sr register`
277
278	462	julius	`uint32_t OrpsocAccess::getSprSr()`
279	44	julius	`{`
280	462	julius	`return (or1200_sprs->get_sr) ();`
281	44	julius
282	462	julius	`} // getSprSr ()`
283	44	julius
284			`//! Access for the epcr register`
285
286			`//! @return The value of the or1200_sprs.epcr register`
287
288	462	julius	`uint32_t OrpsocAccess::getSprEpcr()`
289	44	julius	`{`
290	462	julius	`return (or1200_sprs->get_epcr) ();`
291	44	julius
292	462	julius	`} // getSprEpcr ()`
293	44	julius
294			`//! Access for the eear register`
295
296			`//! @return The value of the or1200_sprs.eear register`
297
298	462	julius	`uint32_t OrpsocAccess::getSprEear()`
299	44	julius	`{`
300	462	julius	`return (or1200_sprs->get_eear) ();`
301	44	julius
302	462	julius	`} // getSprEear ()`
303	44	julius
304			`//! Access for the esr register`
305
306			`//! @return The value of the or1200_sprs.esr register`
307
308	462	julius	`uint32_t OrpsocAccess::getSprEsr()`
309	44	julius	`{`
310	462	julius	`return (or1200_sprs->get_esr) ();`
311	44	julius
312	462	julius	`} // getSprEsr ()`
313	44	julius
314	353	julius	`/*`
315	63	julius	`//! Access for the arbiter's grant signal`
316
317			`//! @return The value of the wb_conmax_top.arb signal`
318
319			`uint8_t`
320			`OrpsocAccess::getWbArbGrant ()`
321			`{`
322			`return (wb_arbiter->get_gnt) ();`
323
324			`} // getWbArbGrant ()`
325
326			`//! Arbiter master[mast_num] access functions`
327
328			`//! Access for the arbiter's master[mast_num] data in signal`
329
330			`//! @return The value of the wb_conmax_top.m_dat_i[mast_num]`
331
332			`uint32_t`
333			`OrpsocAccess::getWbArbMastDatI (uint32_t mast_num)`
334			`{`
335			`return (wb_arbiter->get_m_dat_i) (mast_num);`
336
337			`} // getWbArbMastDatI ()`
338
339			`//! Access for the arbiter's master[mast_num] data out signal`
340
341			`//! @return The value of the wb_conmax_top.m_dat_o[mast_num]`
342
343			`uint32_t`
344			`OrpsocAccess::getWbArbMastDatO (uint32_t mast_num)`
345			`{`
346			`return (wb_arbiter->get_m_dat_o) (mast_num);`
347
348			`} // getWbArbMastDatO ()`
349
350			`//! Access for the arbiter's master[mast_num] data out`
351
352			`//! @return The value of the wb_conmax_top.m_adr_i[mast_num]`
353
354			`uint32_t`
355			`OrpsocAccess::getWbArbMastAdrI (uint32_t mast_num)`
356			`{`
357			`return (wb_arbiter->get_m_adr_i) (mast_num);`
358
359			`} // getWbArbMastAdrI ()`
360
361			`//! Access for the arbiter's master[mast_num] select signal`
362
363			`//! @return The value of the wb_conmax_top.m_sel_i[mast_num]`
364
365			`uint8_t`
366			`OrpsocAccess::getWbArbMastSelI (uint32_t mast_num)`
367			`{`
368			`return (wb_arbiter->get_m_sel_i) (mast_num);`
369
370			`} // getWbArbMastSelI ()`
371
372			`//! Access for the arbiter's master[mast_num] decoded slave select signal`
373
374			`//! @return The value of the wb_conmax_top.m_ssel_dec[mast_num]`
375
376			`uint8_t`
377			`OrpsocAccess::getWbArbMastSlaveSelDecoded (uint32_t mast_num)`
378			`{`
379			`return (wb_arbiter->get_m_ssel_dec) (mast_num);`
380
381			`} // getWbArbMastSlaveSelDecoded ()`
382
383			`//! Access for the arbiter's master[mast_num] write enable signal`
384
385			`//! @return The value of the wb_conmax_top.m_we_i[mast_num]`
386
387			`bool`
388			`OrpsocAccess::getWbArbMastWeI (uint32_t mast_num)`
389			`{`
390			`return (wb_arbiter->get_m_we_i) (mast_num);`
391
392			`} // getWbArbMastWeI ()`
393
394			`//! Access for the arbiter's master[mast_num] cycle input signal`
395
396			`//! @return The value of the wb_conmax_top.m_cyc_i[mast_num]`
397
398			`bool`
399			`OrpsocAccess::getWbArbMastCycI (uint32_t mast_num)`
400			`{`
401			`return (wb_arbiter->get_m_cyc_i) (mast_num);`
402
403			`} // getWbArbMastCycI ()`
404
405			`//! Access for the arbiter's master[mast_num] strobe input signal`
406
407			`//! @return The value of the wb_conmax_top.m_stb_i[mast_num]`
408
409			`bool`
410			`OrpsocAccess::getWbArbMastStbI (uint32_t mast_num)`
411			`{`
412			`return (wb_arbiter->get_m_stb_i) (mast_num);`
413
414			`} // getWbArbMastStbI ()`
415
416			`//! Access for the arbiter's master[mast_num] ACK output signal`
417
418			`//! @return The value of the wb_conmax_top.m_ack_o[mast_num]`
419
420			`bool`
421			`OrpsocAccess::getWbArbMastAckO (uint32_t mast_num)`
422			`{`
423			`return (wb_arbiter->get_m_ack_o) (mast_num);`
424
425			`} // getWbArbMastAckO ()`
426
427			`//! Access for the arbiter's master[mast_num] error input signal`
428
429			`//! @return The value of the wb_conmax_top.m_err_o[mast_num]`
430
431			`bool`
432			`OrpsocAccess::getWbArbMastErrO (uint32_t mast_num)`
433			`{`
434			`return (wb_arbiter->get_m_err_o) (mast_num);`
435
436			`} // getWbArbMastErrO ()`
437
438	353	julius	`*/`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [OrpsocAccess.cpp] - Blame information for rev 590