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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [OrpsocMain.cpp] - Blame information for rev 435

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1 63 julius
/////////////////////////////////////////////////////////////////////
2 6 julius
////                                                              ////
3
////  ORPSoC SystemC Testbench                                    ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  ORPSoC Testbench file                                       ////
7
////                                                              ////
8
////  To Do:                                                      ////
9
////                                                              ////
10
////                                                              ////
11
////  Author(s):                                                  ////
12
////      - Jeremy Bennett jeremy.bennett@embecosm.com            ////
13
////      - Julius Baxter jb@orsoc.se                             ////
14
////                                                              ////
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////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
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////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
#include "OrpsocMain.h"
44
 
45 363 julius
// TODO - copy orpsoc-defines.h and or1200-defines.h somewhere this can see
46
//        them and include/exclude RSP stuff. For now is defined
47 63 julius
 
48 397 julius
 
49 6 julius
#include "Vorpsoc_top.h"
50
#include "OrpsocAccess.h"
51 51 julius
#include "MemoryLoad.h"
52 49 julius
 
53 70 julius
#include <verilated_vcd_c.h>
54 49 julius
 
55 6 julius
#include "ResetSC.h"
56
#include "Or1200MonitorSC.h"
57 363 julius
 
58 397 julius
 
59
// Include Verilog ORPSoC defines file, converted to C include format to be
60
// able to detect if the debug unit is to be built in or not.
61
#include "orpsoc-defines.h"
62
 
63
 
64 363 julius
#ifdef JTAG_DEBUG
65
# include "GdbServerSC.h"
66
# include "JtagSC_includes.h"
67
#endif
68
 
69 397 julius
#ifdef UART0
70
#  include "UartSC.h"
71
#endif
72 6 julius
 
73 49 julius
int SIM_RUNNING;
74 6 julius
int sc_main (int   argc,
75
             char *argv[] )
76
{
77 49 julius
  sc_set_time_resolution( 1, TIMESCALE_UNIT);
78 6 julius
  // CPU clock (also used as JTAG TCK) and reset (both active high and low)
79
  sc_time  clkPeriod (BENCH_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
80 363 julius
  sc_clock             clk ("clk", clkPeriod);
81 6 julius
 
82
  sc_signal<bool>      rst;
83
  sc_signal<bool>      rstn;
84
 
85 363 julius
#ifdef JTAG_DEBUG
86
  sc_time   jtagPeriod (JTAG_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
87
  sc_clock  jtag_tck ("jtag-clk", jtagPeriod, 0.5, SC_ZERO_TIME, false);
88
 
89 6 julius
  sc_signal<bool>      jtag_tdi;                // JTAG interface
90
  sc_signal<bool>      jtag_tdo;
91
  sc_signal<bool>      jtag_tms;
92
  sc_signal<bool>      jtag_trst;
93 363 julius
#endif
94 6 julius
 
95 397 julius
#ifdef UART0
96 6 julius
  sc_signal<bool>      uart_rx;         // External UART
97
  sc_signal<bool>      uart_tx;
98 397 julius
#endif
99 6 julius
 
100 49 julius
  SIM_RUNNING = 0;
101 6 julius
 
102 397 julius
  // Are we running "quiet"?
103
  bool quiet = false;
104 49 julius
  // Setup the name of the VCD dump file
105 63 julius
  bool VCD_enabled = false;
106 49 julius
  string dumpNameDefault("vlt-dump.vcd");
107
  string testNameString;
108
  string vcdDumpFile;
109
  // VCD dump controling vars
110 63 julius
  bool dump_start_delay_set = false, dump_stop_set = false;
111
  bool dumping_now = false;
112 49 julius
  int dump_depth = 99; // Default dump depth
113
  sc_time dump_start,dump_stop, finish_time;
114 363 julius
  bool finish_time_set = false; // By default we will let the simulation 
115
                                // finish naturally
116 70 julius
  VerilatedVcdC *verilatorVCDFile;
117 49 julius
 
118 63 julius
  /*int*/double time_val;
119
  bool vcd_file_name_given = false;
120 49 julius
 
121 363 julius
#ifdef JTAG_DEBUG
122 63 julius
  bool rsp_server_enabled = false;
123
  int rsp_server_port = DEFAULT_RSP_PORT;
124 363 julius
#endif
125 63 julius
 
126 51 julius
  // Executable app load variables
127 363 julius
  int do_program_file_load = 0; // Default: we don't require a file, we use the
128
                                // VMEM
129 51 julius
  char* program_file; // Old char* style for program name
130
 
131 6 julius
  // Verilator accessor
132
  OrpsocAccess    *accessor;
133
 
134
  // Modules
135
  Vorpsoc_top *orpsoc;          // Verilated ORPSoC
136
 
137 51 julius
  MemoryLoad *memoryload;       // Memory loader
138
 
139 6 julius
  ResetSC          *reset;              // Generate a RESET signal
140 363 julius
 
141 6 julius
  Or1200MonitorSC  *monitor;            // Handle l.nop x instructions
142 363 julius
 
143
#ifdef JTAG_DEBUG
144 63 julius
  JtagSC           *jtag;               // Generate JTAG signals
145
  GdbServerSC      *gdbServer;          // Map RSP requests to debug unit
146 363 julius
#endif
147
 
148 397 julius
#ifdef UART0
149 6 julius
  UartSC          *uart;                // Handle UART signals
150 397 julius
#endif
151 6 julius
 
152
  // Instantiate the Verilator model, VCD trace handler and accessor
153
  orpsoc     = new Vorpsoc_top ("orpsoc");
154 51 julius
 
155 6 julius
  accessor   = new OrpsocAccess (orpsoc);
156
 
157 51 julius
  memoryload = new MemoryLoad (accessor);
158
 
159 397 julius
  monitor    = new Or1200MonitorSC ("monitor", accessor, memoryload,
160 63 julius
                                    argc, argv);
161
 
162 6 julius
  // Instantiate the SystemC modules
163
  reset         = new ResetSC ("reset", BENCH_RESET_TIME);
164 363 julius
 
165
#ifdef JTAG_DEBUG  
166 63 julius
  jtag          = new JtagSC ("jtag");
167 363 julius
#endif
168 63 julius
 
169 397 julius
#ifdef UART0
170
  uart          = new UartSC("uart");
171
#endif
172 6 julius
 
173 49 julius
  // Parse command line options
174 363 julius
  // Default is for VCD generation OFF, only turned on if specified on command 
175
  // line
176 49 julius
 
177 51 julius
  // Search through the command line parameters for options  
178 49 julius
  if (argc > 1)
179
    {
180
      for(int i=1; i<argc; i++)
181
        {
182 63 julius
          if ( (strcmp(argv[i], "-e")==0) ||
183
               (strcmp(argv[i], "--endtime")==0) )
184 49 julius
            {
185 63 julius
              time_val = strtod(argv[i+1], NULL);
186 49 julius
              sc_time opt_end_time(time_val,TIMESCALE_UNIT);
187
              finish_time = opt_end_time;
188 63 julius
              finish_time_set = true;
189 49 julius
            }
190 51 julius
          else if ( (strcmp(argv[i], "-f")==0) ||
191
                    (strcmp(argv[i], "--program")==0) )
192
            {
193 363 julius
              do_program_file_load = 1; // Enable program loading - will be 
194
                                        // done after sim init.
195 51 julius
              program_file = argv[i+1]; // Old char* style for program name
196
            }
197 63 julius
          else if ((strcmp(argv[i], "-d")==0) ||
198
                   (strcmp(argv[i], "--vcdfile")==0) ||
199
                   (strcmp(argv[i], "-v")==0) ||
200
                   (strcmp(argv[i], "--vcdon")==0)
201
                   )
202
            {
203
              VCD_enabled = true;
204
              dumping_now = true;
205
              vcdDumpFile = dumpNameDefault;
206
              if (i+1 < argc)
207
                if(argv[i+1][0] != '-')
208
                  {
209
                    testNameString = argv[i+1];
210
                    vcdDumpFile = testNameString;
211
                    i++;
212
                  }
213
            }
214
          else if ( (strcmp(argv[i], "-s")==0) ||
215 49 julius
                    (strcmp(argv[i], "--vcdstart")==0) )
216
            {
217 63 julius
              VCD_enabled = true;
218
              time_val = strtod(argv[i+1], NULL);
219 49 julius
              sc_time dump_start_time(time_val,TIMESCALE_UNIT);
220
              dump_start = dump_start_time;
221 63 julius
              dump_start_delay_set = true;
222
              dumping_now = false;
223 49 julius
            }
224
          else if ( (strcmp(argv[i], "-t")==0) ||
225
                    (strcmp(argv[i], "--vcdstop")==0) )
226
            {
227 63 julius
              VCD_enabled = true;
228
              time_val = strtod(argv[i+1],NULL);
229 49 julius
              sc_time dump_stop_time(time_val,TIMESCALE_UNIT);
230
              dump_stop = dump_stop_time;
231 63 julius
              dump_stop_set = true;
232 49 julius
            }
233 397 julius
          /*
234
             Depth setting of VCD doesn't appear to work, I think it's only
235
             configurable during at compile time .
236
          */
237
          /*      else if ( (strcmp(argv[i], "-p")==0) ||
238
                  (strcmp(argv[i], "--vcddepth")==0) )
239
                  {
240
                  dump_depth = atoi(argv[i+1]);
241
          }*/
242 363 julius
#ifdef JTAG_DEBUG
243 63 julius
          else if ( (strcmp(argv[i], "-r")==0) ||
244
                    (strcmp(argv[i], "--rsp")==0) )
245
            {
246
              rsp_server_enabled = true;
247
              if (i+1 < argc) if(argv[i+1][0] != '-')
248
                                {
249
                                  rsp_server_port = atoi(argv[i+1]);
250
                                  i++;
251
                                }
252
            }
253 363 julius
#endif
254 397 julius
          else if ((strcmp(argv[i], "-q")==0) ||
255
                   (strcmp(argv[i], "--quiet")==0))
256
            {
257
              quiet = true;
258
            }
259 49 julius
          else if ( (strcmp(argv[i], "-h")==0) ||
260
                    (strcmp(argv[i], "--help")==0) )
261
            {
262 63 julius
              printf("Usage: %s [options]\n",argv[0]);
263
              printf("\n  ORPSoCv2 cycle accurate model\n");
264
              printf("  For details visit http://opencores.org/openrisc,orpsocv2\n");
265
              printf("\n");
266
              printf("Options:\n");
267 49 julius
              printf("  -h, --help\t\tPrint this help message\n");
268 397 julius
              printf("  -q, --quiet\t\tDisable all except UART print out\n");
269 63 julius
              printf("\nSimulation control:\n");
270
              printf("  -f, --program <file> \tLoad program from OR32 ELF <file>\n");
271
              printf("  -e, --endtime <val> \tStop the sim at <val> ns\n");
272
              printf("\nVCD generation:\n");
273 49 julius
              printf("  -v, --vcdon\t\tEnable VCD generation\n");
274 63 julius
              printf("  -d, --vcdfile <file>\tEnable and save VCD to <file>\n");
275 49 julius
 
276 63 julius
              printf("  -s, --vcdstart <val>\tEnable and delay VCD generation until <val> ns\n");
277
              printf("  -t, --vcdstop <val> \tEnable and terminate VCD generation at <val> ns\n");
278 363 julius
#ifdef JTAG_DEBUG
279 63 julius
              printf("\nRemote debugging:\n");
280
              printf("  -r, --rsp [<port>]\tEnable RSP debugging server, opt. specify <port>\n");
281 363 julius
#endif
282 49 julius
              monitor->printUsage();
283
              printf("\n");
284
              return 0;
285
            }
286
 
287
        }
288
    }
289 63 julius
 
290 49 julius
  // Determine if we're going to setup a VCD dump:
291 63 julius
  // Pretty much setting any related option will enable VCD dumping.
292
  if (VCD_enabled)
293 49 julius
    {
294
 
295
      cout << "* Enabling VCD trace";
296
 
297 63 julius
      if (dump_start_delay_set)
298 49 julius
        cout << ", on at time " << dump_start.to_string();
299
      if (dump_stop_set)
300 63 julius
        cout << ", off at time " << dump_stop.to_string();
301 49 julius
      cout << endl;
302
    }
303 363 julius
#ifdef JTAG_DEBUG  
304 63 julius
  if (rsp_server_enabled)
305
    gdbServer     = new GdbServerSC ("gdb-server", FLASH_START, FLASH_END,
306
                                       rsp_server_port, jtag->tapActionQueue);
307
  else
308
      gdbServer = NULL;
309 363 julius
#endif
310 63 julius
 
311 6 julius
  // Connect up ORPSoC
312
  orpsoc->clk_pad_i (clk);
313 362 julius
  orpsoc->rst_n_pad_i (rstn);
314 6 julius
 
315 363 julius
#ifdef JTAG_DEBUG
316 362 julius
  orpsoc->tck_pad_i  (jtag_tck);                // JTAG interface
317
  orpsoc->tdi_pad_i  (jtag_tdi);
318
  orpsoc->tms_pad_i  (jtag_tms);
319
  orpsoc->tdo_pad_o  (jtag_tdo);
320 363 julius
#endif
321 6 julius
 
322 397 julius
#ifdef UART0
323 6 julius
  orpsoc->uart0_srx_pad_i (uart_rx);            // External UART
324
  orpsoc->uart0_stx_pad_o (uart_tx);
325 397 julius
#endif
326 6 julius
 
327
  // Connect up the SystemC  modules
328
  reset->clk (clk);                     // Reset
329
  reset->rst (rst);
330
  reset->rstn (rstn);
331
 
332
  monitor->clk (clk);                   // Monitor
333
 
334 363 julius
#ifdef JTAG_DEBUG
335 63 julius
  jtag->sysReset (rst);                 // JTAG
336
  jtag->tck (jtag_tck);
337
  jtag->tdi (jtag_tdi);
338
  jtag->tdo (jtag_tdo);
339
  jtag->tms (jtag_tms);
340
  jtag->trst (jtag_trst);
341 363 julius
#endif
342 63 julius
 
343 397 julius
#ifdef UART0
344 6 julius
  uart->clk (clk); // Uart
345
  uart->uartrx (uart_rx); // orpsoc's receive line
346
  uart->uarttx (uart_tx); // orpsoc's transmit line
347 397 julius
#endif
348 6 julius
 
349 63 julius
  // Tie off signals
350 363 julius
#ifdef JTAG_DEBUG
351 63 julius
  jtag_tdi      = 1;                    // Tie off the JTAG inputs
352
  jtag_tms      = 1;
353 363 julius
#endif
354 63 julius
 
355 49 julius
  if (VCD_enabled)
356
    {
357
      Verilated::traceEverOn (true);
358
 
359
      printf("* VCD dumpfile: %s\n", vcdDumpFile.c_str());
360
 
361
      // Establish a new trace with its correct time resolution, and trace to
362
      // great depth.
363 70 julius
      verilatorVCDFile = new VerilatedVcdC ();
364 363 julius
 
365 70 julius
      orpsoc->trace (verilatorVCDFile, dump_depth);
366 49 julius
 
367
      if (dumping_now)
368
        {
369 70 julius
          verilatorVCDFile->open (vcdDumpFile.c_str());
370 49 julius
        }
371
    }
372 362 julius
 
373 52 julius
  //printf("* Beginning test\n");
374 6 julius
 
375 397 julius
#ifdef UART0
376 6 julius
  // Init the UART function
377 354 julius
  uart->initUart(50000000, 115200);
378 397 julius
#endif
379 6 julius
 
380 51 julius
  if (do_program_file_load) // Did the user specify a file to load?
381
    {
382
      cout << "* Loading program from " << program_file << endl;
383
      if (memoryload->loadcode(program_file,0,0) < 0)
384
        {
385 363 julius
          cout << "* Error: executable file " << program_file <<
386
            " not loaded" << endl;
387 51 julius
        }
388
    }
389 397 julius
  else // No ELF file specified, default is to load SRAM from VMEM file
390 51 julius
    {
391 397 julius
      if (!quiet)
392
        cout << "* Loading memory with image from default file, sram.vmem"
393
             << endl;
394 51 julius
      accessor->do_ram_readmemh();
395
    }
396 44 julius
 
397 51 julius
  SIM_RUNNING = 1;
398
 
399 49 julius
  // First check how we should run the sim.
400
  if (VCD_enabled || finish_time_set)
401
    { // We'll run sim with step
402
 
403
      if (!VCD_enabled && finish_time_set)
404
        {
405
          // We just run the sim until the set finish time
406
          sc_start((double)(finish_time.to_double()), TIMESCALE_UNIT);
407
          SIM_RUNNING=0;
408
          sc_stop();
409
          // Print performance summary
410 52 julius
          monitor->perfSummary();
411
          // Do memdump if enabled
412
          monitor->memdump();
413 49 julius
        }
414
      else
415
        {
416 63 julius
          if (dump_start_delay_set)
417 49 julius
            {
418
              // Run the sim until we want to dump
419
              sc_start((double)(dump_start.to_double()),TIMESCALE_UNIT);
420
              // Open the trace file
421 70 julius
              verilatorVCDFile->open (vcdDumpFile.c_str());
422 49 julius
              dumping_now = 1;
423
            }
424 6 julius
 
425 49 julius
          if (dumping_now)
426
            {
427
              // Step the sim and generate the trace
428
                  // Execute until we stop
429
              while(!Verilated::gotFinish())
430
                {
431
                  if (SIM_RUNNING) // Changed by Or1200MonitorSC when finish NOP
432
                    sc_start (1,TIMESCALE_UNIT); // Step the sim
433
                  else
434
                    {
435 70 julius
                      verilatorVCDFile->close();
436 49 julius
                      break;
437
                    }
438
 
439 70 julius
                  verilatorVCDFile->dump (sc_time_stamp().to_double());
440 49 julius
 
441
                  if (dump_stop_set)
442
                    {
443
                      if (sc_time_stamp() >=  dump_stop)
444
                        {
445
                          // Close dump file
446 70 julius
                          verilatorVCDFile->close();
447 49 julius
                          // Now continue on again until the end
448
                          if (!finish_time_set)
449
                            sc_start();
450
                          else
451
                            {
452
                              // Determine how long we should run for
453
                              sc_time sim_time_remaining =
454
                                finish_time - sc_time_stamp();
455
                              sc_start((double)(sim_time_remaining.to_double()),
456
                                       TIMESCALE_UNIT);
457
                              // Officially stop the sim
458
                              sc_stop();
459
                              // Print performance summary
460
                              monitor->perfSummary();
461 52 julius
                              // Do memdump if enabled
462
                              monitor->memdump();
463 49 julius
                            }
464
                          break;
465
                        }
466
                    }
467
                  if (finish_time_set)
468
                    {
469
                      if (sc_time_stamp() >=  finish_time)
470
                        {
471
                          // Officially stop the sim
472
                          sc_stop();
473
                          // Close dump file
474 70 julius
                          verilatorVCDFile->close();
475 52 julius
                          // Do memdump if enabled
476
                          monitor->memdump();
477 49 julius
                          // Print performance summary
478
                          monitor->perfSummary();
479
                          break;
480
                        }
481
                    }
482
                }
483
            }
484
        }
485
    }
486
  else
487
    {
488
      // Simple run case
489 363 julius
      // Ideally a "l.nop 1" will terminate the simulation gracefully.
490
      // Need to step at clock period / 4, otherwise model appears to skip the 
491
      // monitor and logging functions sometimes (?!?)
492 64 julius
      while (SIM_RUNNING)
493
        sc_start(BENCH_CLK_HALFPERIOD / 2, TIMESCALE_UNIT);
494
      //sc_start();
495 49 julius
    }
496
 
497
 
498 6 julius
  // Free memory
499 363 julius
#ifdef JTAG_DEBUG
500 63 julius
  if (rsp_server_enabled)
501
    delete gdbServer;
502 363 julius
 
503 63 julius
  delete jtag;
504 363 julius
#endif
505
 
506 6 julius
  delete monitor;
507 363 julius
 
508 6 julius
  delete reset;
509
 
510
  delete accessor;
511
 
512 49 julius
  //delete trace;
513 363 julius
 
514 6 julius
  delete orpsoc;
515
 
516
  return 0;
517
 
518
}       /* sc_main() */

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