URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [OrpsocMain.cpp] - Blame information for rev 535

Go to most recent revision | Details | Compare with Previous | View Log


/////////////////////////////////////////////////////////////////////
////                                                              ////
////  ORPSoC SystemC Testbench                                    ////
////                                                              ////
////  Description                                                 ////
////  ORPSoC Testbench file                                       ////
////                                                              ////
////  To Do:                                                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////      - Jeremy Bennett jeremy.bennett@embecosm.com            ////
////      - Julius Baxter  julius@opencores.org                   ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
#include "OrpsocMain.h"
 
#include "Vorpsoc_top.h"
#include "OrpsocAccess.h"
#include "MemoryLoad.h"
 
#include <verilated_vcd_c.h>
 
#include "ResetSC.h"
#include "Or1200MonitorSC.h"
 
// Include Verilog ORPSoC defines file, converted to C include format to be
// able to detect if the debug unit is to be built in or not.
#include "orpsoc-defines.h"
 
#ifdef JTAG_DEBUG
# include "GdbServerSC.h"
# include "JtagSC_includes.h"
#endif
 
#ifdef UART0
#  include "UartSC.h"
#endif
 
/* Global quiet variable */
bool gQuiet;
 
int gSimRunning;
 
int sc_main(int argc, char *argv[])
{
        sc_set_time_resolution(1, TIMESCALE_UNIT);
        // CPU clock (also used as JTAG TCK) and reset (both active high and low)
        sc_time clkPeriod(BENCH_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
        sc_clock clk("clk", clkPeriod);
 
        sc_signal < bool > rst;
        sc_signal < bool > rstn;
 
#ifdef JTAG_DEBUG
        sc_time jtagPeriod(JTAG_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
        sc_clock jtag_tck("jtag-clk", jtagPeriod, 0.5, SC_ZERO_TIME, false);
 
        sc_signal < bool > jtag_tdi;    // JTAG interface
        sc_signal < bool > jtag_tdo;
        sc_signal < bool > jtag_tms;
        sc_signal < bool > jtag_trst;
#endif
 
#ifdef UART0
        sc_signal < bool > uart_rx;     // External UART
        sc_signal < bool > uart_tx;
#endif
 
        gSimRunning = 0;
 
        // Are we running "quiet"?
        gQuiet = false;
        // Setup the name of the VCD dump file
        bool VCD_enabled = false;
        string dumpNameDefault("vlt-dump.vcd");
        string testNameString;
        string vcdDumpFile;
        // VCD dump controling vars
        bool dump_start_delay_set = false, dump_stop_set = false;
        bool dumping_now = false;
        int dump_depth = 99;    // Default dump depth
        sc_time dump_start, dump_stop, finish_time;
        bool finish_time_set = false;   // By default we will let the simulation 
        // finish naturally
        VerilatedVcdC *verilatorVCDFile;
 
        /*int */ double time_val;
        bool vcd_file_name_given = false;
 
#ifdef JTAG_DEBUG
        bool rsp_server_enabled = false;
        int rsp_server_port = DEFAULT_RSP_PORT;
#endif
 
        // Executable app load variables
        int do_program_file_load = 0;    // Default: we don't require a file, we use the
        // VMEM
        char *program_file;     // Old char* style for program name
 
        // Verilator accessor
        OrpsocAccess *accessor;
 
        // Modules
        Vorpsoc_top *orpsoc;    // Verilated ORPSoC
 
        MemoryLoad *memoryload; // Memory loader
 
        ResetSC *reset;         // Generate a RESET signal
 
        Or1200MonitorSC *monitor;       // Handle l.nop x instructions
 
#ifdef JTAG_DEBUG
        JtagSC *jtag;           // Generate JTAG signals
        GdbServerSC *gdbServer; // Map RSP requests to debug unit
#endif
 
#ifdef UART0
        UartSC *uart;           // Handle UART signals
#endif
 
        // Instantiate the Verilator model, VCD trace handler and accessor
        orpsoc = new Vorpsoc_top("orpsoc");
 
        accessor = new OrpsocAccess(orpsoc);
 
        memoryload = new MemoryLoad(accessor);
 
        monitor = new Or1200MonitorSC("monitor", accessor, memoryload,
                                      argc, argv);
 
        // Instantiate the SystemC modules
        reset = new ResetSC("reset", BENCH_RESET_TIME);
 
#ifdef JTAG_DEBUG
        jtag = new JtagSC("jtag");
#endif
 
#ifdef UART0
        uart = new UartSC("uart");
#endif
 
        // Parse command line options
        // Default is for VCD generation OFF, only turned on if specified on command 
        // line
 
        // Search through the command line parameters for options  
        if (argc > 1) {
                for (int i = 1; i < argc; i++) {
                        if ((strcmp(argv[i], "-e") == 0) ||
                            (strcmp(argv[i], "--endtime") == 0)) {
                                time_val = strtod(argv[i + 1], NULL);
                                sc_time opt_end_time(time_val, TIMESCALE_UNIT);
                                finish_time = opt_end_time;
                                finish_time_set = true;
                        } else if ((strcmp(argv[i], "-q") == 0) ||
                                   (strcmp(argv[i], "--quiet") == 0)) {
                                gQuiet = true;
                        } else if ((strcmp(argv[i], "-f") == 0) ||
                                  (strcmp(argv[i], "--program") == 0)) {
                                do_program_file_load = 1;       // Enable program loading - will be 
                                // done after sim init.
                                program_file = argv[i + 1];     // Old char* style for program name
                        } else if ((strcmp(argv[i], "-d") == 0) ||
                                   (strcmp(argv[i], "--vcdfile") == 0) ||
                                   (strcmp(argv[i], "-v") == 0) ||
                                   (strcmp(argv[i], "--vcdon") == 0)
                            ) {
                                VCD_enabled = true;
                                dumping_now = true;
                                vcdDumpFile = dumpNameDefault;
                                if (i + 1 < argc)
                                        if (argv[i + 1][0] != '-') {
                                                testNameString = argv[i + 1];
                                                vcdDumpFile = testNameString;
                                                i++;
                                        }
                        } else if ((strcmp(argv[i], "-s") == 0) ||
                                   (strcmp(argv[i], "--vcdstart") == 0)) {
                                VCD_enabled = true;
                                time_val = strtod(argv[i + 1], NULL);
                                sc_time dump_start_time(time_val,
                                                        TIMESCALE_UNIT);
                                dump_start = dump_start_time;
                                dump_start_delay_set = true;
                                dumping_now = false;
                        } else if ((strcmp(argv[i], "-t") == 0) ||
                                   (strcmp(argv[i], "--vcdstop") == 0)) {
                                VCD_enabled = true;
                                time_val = strtod(argv[i + 1], NULL);
                                sc_time dump_stop_time(time_val,
                                                       TIMESCALE_UNIT);
                                dump_stop = dump_stop_time;
                                dump_stop_set = true;
                        }
#ifdef JTAG_DEBUG
                        else if ((strcmp(argv[i], "-r") == 0) ||
                                 (strcmp(argv[i], "--rsp") == 0)) {
                                rsp_server_enabled = true;
                                if (i + 1 < argc)
                                        if (argv[i + 1][0] != '-') {
                                                rsp_server_port =
                                                    atoi(argv[i + 1]);
                                                i++;
                                        }
                        }
#endif
                        else if ((strcmp(argv[i], "-h") == 0) ||
                                   (strcmp(argv[i], "--help") == 0)) {
                                printf("Usage: %s [options]\n", argv[0]);
                                printf("\n  ORPSoCv2 cycle accurate model\n");
                                printf
                                    ("  For details visit http://opencores.org/openrisc,orpsocv2\n");
                                printf("\n");
                                printf("Options:\n");
                                printf
                                    ("  -h, --help\t\tPrint this help message\n");
                                printf
                                    ("  -q, --quiet\t\tDisable all except UART print out\n");
                                printf("\nSimulation control:\n");
                                printf
                                    ("  -f, --program <file> \tLoad program from OR32 ELF <file>\n");
                                printf
                                    ("  -e, --endtime <val> \tStop the sim at <val> ns\n");
                                printf("\nVCD generation:\n");
                                printf
                                    ("  -v, --vcdon\t\tEnable VCD generation\n");
                                printf
                                    ("  -d, --vcdfile <file>\tEnable and save VCD to <file>\n");
 
                                printf
                                    ("  -s, --vcdstart <val>\tEnable and delay VCD generation until <val> ns\n");
                                printf
                                    ("  -t, --vcdstop <val> \tEnable and terminate VCD generation at <val> ns\n");
#ifdef JTAG_DEBUG
                                printf("\nRemote debugging:\n");
                                printf
                                    ("  -r, --rsp [<port>]\tEnable RSP debugging server, opt. specify <port>\n");
#endif
                                monitor->printUsage();
                                printf("\n");
                                return 0;
                        }
 
                }
        }
        // Determine if we're going to setup a VCD dump:
        // Pretty much setting any related option will enable VCD dumping.
        if (VCD_enabled) {
 
                cout << "* Enabling VCD trace";
 
                if (dump_start_delay_set)
                        cout << ", on at time " << dump_start.to_string();
                if (dump_stop_set)
                        cout << ", off at time " << dump_stop.to_string();
                cout << endl;
        }
#ifdef JTAG_DEBUG
        if (rsp_server_enabled)
                gdbServer =
                    new GdbServerSC("gdb-server", FLASH_START, FLASH_END,
                                    rsp_server_port, jtag->tapActionQueue);
        else
                gdbServer = NULL;
#endif
 
        // Connect up ORPSoC
        orpsoc->clk_pad_i(clk);
        orpsoc->rst_n_pad_i(rstn);
 
#ifdef JTAG_DEBUG
        orpsoc->tck_pad_i(jtag_tck);    // JTAG interface
        orpsoc->tdi_pad_i(jtag_tdi);
        orpsoc->tms_pad_i(jtag_tms);
        orpsoc->tdo_pad_o(jtag_tdo);
#endif
 
#ifdef UART0
        orpsoc->uart0_srx_pad_i(uart_rx);       // External UART
        orpsoc->uart0_stx_pad_o(uart_tx);
#endif
 
        // Connect up the SystemC  modules
        reset->clk(clk);        // Reset
        reset->rst(rst);
        reset->rstn(rstn);
 
        monitor->clk(clk);      // Monitor
 
#ifdef JTAG_DEBUG
        jtag->sysReset(rst);    // JTAG
        jtag->tck(jtag_tck);
        jtag->tdi(jtag_tdi);
        jtag->tdo(jtag_tdo);
        jtag->tms(jtag_tms);
        jtag->trst(jtag_trst);
#endif
 
#ifdef UART0
        uart->clk(clk);         // Uart
        uart->uartrx(uart_rx);  // orpsoc's receive line
        uart->uarttx(uart_tx);  // orpsoc's transmit line
#endif
 
        // Tie off signals
#ifdef JTAG_DEBUG
        jtag_tdi = 1;           // Tie off the JTAG inputs
        jtag_tms = 1;
#endif
 
        if (VCD_enabled) {
                Verilated::traceEverOn(true);
 
                printf("* VCD dumpfile: %s\n", vcdDumpFile.c_str());
 
                // Establish a new trace with its correct time resolution, and trace to
                // great depth.
                verilatorVCDFile = new VerilatedVcdC();
 
                orpsoc->trace(verilatorVCDFile, dump_depth);
 
                if (dumping_now) {
                        verilatorVCDFile->open(vcdDumpFile.c_str());
                }
        }
        //printf("* Beginning test\n");
 
#ifdef UART0
        // Init the UART function
        uart->initUart(115200);
#endif
 
        if (do_program_file_load)       // Did the user specify a file to load?
        {
                if (!gQuiet)
                        cout << "* Loading program from " << program_file <<
                                endl;
                if (memoryload->loadcode(program_file, 0, 0) < 0) {
                        cout << "* Error: executable file " << program_file <<
                            " not loaded" << endl;
                        goto finish_up;
 
                }
        } else
        {
                /* No ELF file specified, default is to load from  VMEM file */
                if (!gQuiet)
                        cout <<
                            "* Loading memory with image from default file, sram.vmem"
                            << endl;
                accessor->do_ram_readmemh();
        }
 
        gSimRunning = 1;
 
        // First check how we should run the sim.
        if (VCD_enabled || finish_time_set) {   // We'll run sim with step
 
                if (!VCD_enabled && finish_time_set) {
                        // We just run the sim until the set finish time
                        sc_start((double)(finish_time.to_double()),
                                 TIMESCALE_UNIT);
                        gSimRunning = 0;
                        sc_stop();
                        // Print performance summary
                        monitor->perfSummary();
                        // Do memdump if enabled
                        monitor->memdump();
                } else {
                        if (dump_start_delay_set) {
                                // Run the sim until we want to dump
                                sc_start((double)(dump_start.to_double()),
                                         TIMESCALE_UNIT);
                                // Open the trace file
                                verilatorVCDFile->open(vcdDumpFile.c_str());
                                dumping_now = 1;
                        }
 
                        if (dumping_now) {
                                // Step the sim and generate the trace
                                // Execute until we stop
                                while (!Verilated::gotFinish()) {
                                        // gSimRunning value changed by the
                                        // monitor when sim should finish.
                                        if (gSimRunning)
                                                // Step the sim
                                                sc_start(1, TIMESCALE_UNIT);
                                        else {
                                                verilatorVCDFile->close();
                                                break;
                                        }
 
                                        verilatorVCDFile->dump(sc_time_stamp().
                                                               to_double());
 
                                        if (dump_stop_set) {
                                                if (sc_time_stamp() >=
                                                    dump_stop) {
                                                        // Close dump file
                                                        verilatorVCDFile->close
                                                                ();
                                                        // Now continue on again until the end
                                                        if (!finish_time_set)
                                                                sc_start();
                                                        else {
                                                                // Determine how long we should run for
                                                                sc_time
                                                                    sim_time_remaining
                                                                    =
                                                                    finish_time
                                                                    -
                                                                    sc_time_stamp
                                                                    ();
                                                                sc_start((double)(sim_time_remaining.to_double()), TIMESCALE_UNIT);
                                                                // Officially stop the sim
                                                                sc_stop();
                                                                // Print performance summary
                                                                monitor->
                                                                    perfSummary
                                                                    ();
                                                                // Do memdump if enabled
                                                                monitor->memdump
                                                                    ();
                                                        }
                                                        break;
                                                }
                                        }
                                        if (finish_time_set) {
                                                if (sc_time_stamp() >=
                                                    finish_time) {
                                                        // Officially stop the sim
                                                        sc_stop();
                                                        // Close dump file
                                                        verilatorVCDFile->close
                                                            ();
                                                        // Do memdump if enabled
                                                        monitor->memdump();
                                                        // Print performance summary
                                                        monitor->perfSummary();
                                                        break;
                                                }
                                        }
                                }
                        }
                }
        } else {
                // Simple run case
                // Ideally a "l.nop 1" will terminate the simulation gracefully.
                // Need to step at clock period / 4, otherwise model appears to skip the 
                // monitor and logging functions sometimes (?!?)
                while (gSimRunning)
                        sc_start(BENCH_CLK_HALFPERIOD / 2, TIMESCALE_UNIT);
                //sc_start();
        }
 
 
finish_up:
        // Free memory
#ifdef JTAG_DEBUG
        if (rsp_server_enabled)
                delete gdbServer;
 
        delete jtag;
#endif
 
        delete monitor;
 
        delete reset;
 
        delete accessor;
 
        //delete trace;
 
        delete orpsoc;
 
        return 0;
 
}                               /* sc_main() */

Line No.	Rev	Author	Line
1	63	julius	`/////////////////////////////////////////////////////////////////////`
2	6	julius	`//// ////`
3			`//// ORPSoC SystemC Testbench ////`
4			`//// ////`
5			`//// Description ////`
6			`//// ORPSoC Testbench file ////`
7			`//// ////`
8			`//// To Do: ////`
9			`//// ////`
10			`//// ////`
11			`//// Author(s): ////`
12			`//// - Jeremy Bennett jeremy.bennett@embecosm.com ////`
13	462	julius	`//// - Julius Baxter julius@opencores.org ////`
14	6	julius	`//// ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2009 Authors and OPENCORES.ORG ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43			`#include "OrpsocMain.h"`
44
45			`#include "Vorpsoc_top.h"`
46			`#include "OrpsocAccess.h"`
47	51	julius	`#include "MemoryLoad.h"`
48	49	julius
49	70	julius	`#include <verilated_vcd_c.h>`
50	49	julius
51	6	julius	`#include "ResetSC.h"`
52			`#include "Or1200MonitorSC.h"`
53	363	julius
54	397	julius	`// Include Verilog ORPSoC defines file, converted to C include format to be`
55			`// able to detect if the debug unit is to be built in or not.`
56			`#include "orpsoc-defines.h"`
57
58	363	julius	`#ifdef JTAG_DEBUG`
59			`# include "GdbServerSC.h"`
60			`# include "JtagSC_includes.h"`
61			`#endif`
62
63	397	julius	`#ifdef UART0`
64			`# include "UartSC.h"`
65			`#endif`
66	6	julius
67	462	julius	`/* Global quiet variable */`
68			`bool gQuiet;`
69
70			`int gSimRunning;`
71
72			`int sc_main(int argc, char *argv[])`
73	6	julius	`{`
74	462	julius	`sc_set_time_resolution(1, TIMESCALE_UNIT);`
75			`// CPU clock (also used as JTAG TCK) and reset (both active high and low)`
76			`sc_time clkPeriod(BENCH_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);`
77			`sc_clock clk("clk", clkPeriod);`
78	6	julius
79	462	julius	`sc_signal < bool > rst;`
80			`sc_signal < bool > rstn;`
81	6	julius
82	363	julius	`#ifdef JTAG_DEBUG`
83	462	julius	`sc_time jtagPeriod(JTAG_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);`
84			`sc_clock jtag_tck("jtag-clk", jtagPeriod, 0.5, SC_ZERO_TIME, false);`
85	363	julius
86	462	julius	`sc_signal < bool > jtag_tdi; // JTAG interface`
87			`sc_signal < bool > jtag_tdo;`
88			`sc_signal < bool > jtag_tms;`
89			`sc_signal < bool > jtag_trst;`
90	363	julius	`#endif`
91	6	julius
92	397	julius	`#ifdef UART0`
93	462	julius	`sc_signal < bool > uart_rx; // External UART`
94			`sc_signal < bool > uart_tx;`
95	397	julius	`#endif`
96	6	julius
97	462	julius	`gSimRunning = 0;`
98	6	julius
99	462	julius	`// Are we running "quiet"?`
100			`gQuiet = false;`
101			`// Setup the name of the VCD dump file`
102			`bool VCD_enabled = false;`
103			`string dumpNameDefault("vlt-dump.vcd");`
104			`string testNameString;`
105			`string vcdDumpFile;`
106			`// VCD dump controling vars`
107			`bool dump_start_delay_set = false, dump_stop_set = false;`
108			`bool dumping_now = false;`
109			`int dump_depth = 99; // Default dump depth`
110			`sc_time dump_start, dump_stop, finish_time;`
111			`bool finish_time_set = false; // By default we will let the simulation`
112			`// finish naturally`
113			`VerilatedVcdC *verilatorVCDFile;`
114	49	julius
115	462	julius	`/int / double time_val;`
116			`bool vcd_file_name_given = false;`
117
118	363	julius	`#ifdef JTAG_DEBUG`
119	462	julius	`bool rsp_server_enabled = false;`
120			`int rsp_server_port = DEFAULT_RSP_PORT;`
121	363	julius	`#endif`
122	63	julius
123	462	julius	`// Executable app load variables`
124			`int do_program_file_load = 0; // Default: we don't require a file, we use the`
125			`// VMEM`
126			`char program_file; // Old char style for program name`
127	51	julius
128	462	julius	`// Verilator accessor`
129			`OrpsocAccess *accessor;`
130	6	julius
131	462	julius	`// Modules`
132			`Vorpsoc_top *orpsoc; // Verilated ORPSoC`
133	363	julius
134	462	julius	`MemoryLoad *memoryload; // Memory loader`
135	363	julius
136	462	julius	`ResetSC *reset; // Generate a RESET signal`
137
138			`Or1200MonitorSC *monitor; // Handle l.nop x instructions`
139
140	363	julius	`#ifdef JTAG_DEBUG`
141	462	julius	`JtagSC *jtag; // Generate JTAG signals`
142			`GdbServerSC *gdbServer; // Map RSP requests to debug unit`
143	363	julius	`#endif`
144
145	397	julius	`#ifdef UART0`
146	462	julius	`UartSC *uart; // Handle UART signals`
147	397	julius	`#endif`
148	6	julius
149	462	julius	`// Instantiate the Verilator model, VCD trace handler and accessor`
150			`orpsoc = new Vorpsoc_top("orpsoc");`
151	363	julius
152	462	julius	`accessor = new OrpsocAccess(orpsoc);`
153
154			`memoryload = new MemoryLoad(accessor);`
155
156			`monitor = new Or1200MonitorSC("monitor", accessor, memoryload,`
157			`argc, argv);`
158
159			`// Instantiate the SystemC modules`
160			`reset = new ResetSC("reset", BENCH_RESET_TIME);`
161
162			`#ifdef JTAG_DEBUG`
163			`jtag = new JtagSC("jtag");`
164	363	julius	`#endif`
165	63	julius
166	397	julius	`#ifdef UART0`
167	462	julius	`uart = new UartSC("uart");`
168	397	julius	`#endif`
169	6	julius
170	462	julius	`// Parse command line options`
171			`// Default is for VCD generation OFF, only turned on if specified on command`
172			`// line`
173
174			`// Search through the command line parameters for options`
175			`if (argc > 1) {`
176			`for (int i = 1; i < argc; i++) {`
177			`if ((strcmp(argv[i], "-e") == 0) \|\|`
178			`(strcmp(argv[i], "--endtime") == 0)) {`
179			`time_val = strtod(argv[i + 1], NULL);`
180			`sc_time opt_end_time(time_val, TIMESCALE_UNIT);`
181			`finish_time = opt_end_time;`
182			`finish_time_set = true;`
183			`} else if ((strcmp(argv[i], "-q") == 0) \|\|`
184			`(strcmp(argv[i], "--quiet") == 0)) {`
185			`gQuiet = true;`
186			`} else if ((strcmp(argv[i], "-f") == 0) \|\|`
187			`(strcmp(argv[i], "--program") == 0)) {`
188			`do_program_file_load = 1; // Enable program loading - will be`
189			`// done after sim init.`
190			`program_file = argv[i + 1]; // Old char* style for program name`
191			`} else if ((strcmp(argv[i], "-d") == 0) \|\|`
192			`(strcmp(argv[i], "--vcdfile") == 0) \|\|`
193			`(strcmp(argv[i], "-v") == 0) \|\|`
194			`(strcmp(argv[i], "--vcdon") == 0)`
195			`) {`
196			`VCD_enabled = true;`
197			`dumping_now = true;`
198			`vcdDumpFile = dumpNameDefault;`
199			`if (i + 1 < argc)`
200			`if (argv[i + 1][0] != '-') {`
201			`testNameString = argv[i + 1];`
202			`vcdDumpFile = testNameString;`
203			`i++;`
204			`}`
205			`} else if ((strcmp(argv[i], "-s") == 0) \|\|`
206			`(strcmp(argv[i], "--vcdstart") == 0)) {`
207			`VCD_enabled = true;`
208			`time_val = strtod(argv[i + 1], NULL);`
209			`sc_time dump_start_time(time_val,`
210			`TIMESCALE_UNIT);`
211			`dump_start = dump_start_time;`
212			`dump_start_delay_set = true;`
213			`dumping_now = false;`
214			`} else if ((strcmp(argv[i], "-t") == 0) \|\|`
215			`(strcmp(argv[i], "--vcdstop") == 0)) {`
216			`VCD_enabled = true;`
217			`time_val = strtod(argv[i + 1], NULL);`
218			`sc_time dump_stop_time(time_val,`
219			`TIMESCALE_UNIT);`
220			`dump_stop = dump_stop_time;`
221			`dump_stop_set = true;`
222			`}`
223	363	julius	`#ifdef JTAG_DEBUG`
224	462	julius	`else if ((strcmp(argv[i], "-r") == 0) \|\|`
225			`(strcmp(argv[i], "--rsp") == 0)) {`
226			`rsp_server_enabled = true;`
227			`if (i + 1 < argc)`
228			`if (argv[i + 1][0] != '-') {`
229			`rsp_server_port =`
230			`atoi(argv[i + 1]);`
231			`i++;`
232			`}`
233			`}`
234	363	julius	`#endif`
235	462	julius	`else if ((strcmp(argv[i], "-h") == 0) \|\|`
236			`(strcmp(argv[i], "--help") == 0)) {`
237			`printf("Usage: %s [options]\n", argv[0]);`
238			`printf("\n ORPSoCv2 cycle accurate model\n");`
239			`printf`
240			`(" For details visit http://opencores.org/openrisc,orpsocv2\n");`
241			`printf("\n");`
242			`printf("Options:\n");`
243			`printf`
244			`(" -h, --help\t\tPrint this help message\n");`
245			`printf`
246			`(" -q, --quiet\t\tDisable all except UART print out\n");`
247			`printf("\nSimulation control:\n");`
248			`printf`
249			`(" -f, --program <file> \tLoad program from OR32 ELF <file>\n");`
250			`printf`
251			`(" -e, --endtime <val> \tStop the sim at <val> ns\n");`
252			`printf("\nVCD generation:\n");`
253			`printf`
254			`(" -v, --vcdon\t\tEnable VCD generation\n");`
255			`printf`
256			`(" -d, --vcdfile <file>\tEnable and save VCD to <file>\n");`
257	49	julius
258	462	julius	`printf`
259			`(" -s, --vcdstart <val>\tEnable and delay VCD generation until <val> ns\n");`
260			`printf`
261			`(" -t, --vcdstop <val> \tEnable and terminate VCD generation at <val> ns\n");`
262	363	julius	`#ifdef JTAG_DEBUG`
263	462	julius	`printf("\nRemote debugging:\n");`
264			`printf`
265			`(" -r, --rsp [<port>]\tEnable RSP debugging server, opt. specify <port>\n");`
266	363	julius	`#endif`
267	462	julius	`monitor->printUsage();`
268			`printf("\n");`
269			`return 0;`
270			`}`
271
272			`}`
273	49	julius	`}`
274	462	julius	`// Determine if we're going to setup a VCD dump:`
275			`// Pretty much setting any related option will enable VCD dumping.`
276			`if (VCD_enabled) {`
277
278			`cout << "* Enabling VCD trace";`
279
280			`if (dump_start_delay_set)`
281			`cout << ", on at time " << dump_start.to_string();`
282			`if (dump_stop_set)`
283			`cout << ", off at time " << dump_stop.to_string();`
284			`cout << endl;`
285			`}`
286			`#ifdef JTAG_DEBUG`
287			`if (rsp_server_enabled)`
288			`gdbServer =`
289			`new GdbServerSC("gdb-server", FLASH_START, FLASH_END,`
290			`rsp_server_port, jtag->tapActionQueue);`
291			`else`
292			`gdbServer = NULL;`
293	363	julius	`#endif`
294	6	julius
295	462	julius	`// Connect up ORPSoC`
296			`orpsoc->clk_pad_i(clk);`
297			`orpsoc->rst_n_pad_i(rstn);`
298
299	363	julius	`#ifdef JTAG_DEBUG`
300	462	julius	`orpsoc->tck_pad_i(jtag_tck); // JTAG interface`
301			`orpsoc->tdi_pad_i(jtag_tdi);`
302			`orpsoc->tms_pad_i(jtag_tms);`
303			`orpsoc->tdo_pad_o(jtag_tdo);`
304	363	julius	`#endif`
305	6	julius
306	397	julius	`#ifdef UART0`
307	462	julius	`orpsoc->uart0_srx_pad_i(uart_rx); // External UART`
308			`orpsoc->uart0_stx_pad_o(uart_tx);`
309	397	julius	`#endif`
310	6	julius
311	462	julius	`// Connect up the SystemC modules`
312			`reset->clk(clk); // Reset`
313			`reset->rst(rst);`
314			`reset->rstn(rstn);`
315	6	julius
316	462	julius	`monitor->clk(clk); // Monitor`
317	6	julius
318	363	julius	`#ifdef JTAG_DEBUG`
319	462	julius	`jtag->sysReset(rst); // JTAG`
320			`jtag->tck(jtag_tck);`
321			`jtag->tdi(jtag_tdi);`
322			`jtag->tdo(jtag_tdo);`
323			`jtag->tms(jtag_tms);`
324			`jtag->trst(jtag_trst);`
325	363	julius	`#endif`
326	63	julius
327	397	julius	`#ifdef UART0`
328	462	julius	`uart->clk(clk); // Uart`
329			`uart->uartrx(uart_rx); // orpsoc's receive line`
330			`uart->uarttx(uart_tx); // orpsoc's transmit line`
331	397	julius	`#endif`
332	6	julius
333	462	julius	`// Tie off signals`
334	363	julius	`#ifdef JTAG_DEBUG`
335	462	julius	`jtag_tdi = 1; // Tie off the JTAG inputs`
336			`jtag_tms = 1;`
337	363	julius	`#endif`
338
339	462	julius	`if (VCD_enabled) {`
340			`Verilated::traceEverOn(true);`
341
342			`printf("* VCD dumpfile: %s\n", vcdDumpFile.c_str());`
343
344			`// Establish a new trace with its correct time resolution, and trace to`
345			`// great depth.`
346			`verilatorVCDFile = new VerilatedVcdC();`
347
348			`orpsoc->trace(verilatorVCDFile, dump_depth);`
349
350			`if (dumping_now) {`
351			`verilatorVCDFile->open(vcdDumpFile.c_str());`
352			`}`
353	49	julius	`}`
354	462	julius	`//printf("* Beginning test\n");`
355	362	julius
356	397	julius	`#ifdef UART0`
357	462	julius	`// Init the UART function`
358	500	julius	`uart->initUart(115200);`
359	397	julius	`#endif`
360	6	julius
361	462	julius	`if (do_program_file_load) // Did the user specify a file to load?`
362	51	julius	`{`
363	462	julius	`if (!gQuiet)`
364			`cout << "* Loading program from " << program_file <<`
365			`endl;`
366			`if (memoryload->loadcode(program_file, 0, 0) < 0) {`
367			`cout << "* Error: executable file " << program_file <<`
368			`" not loaded" << endl;`
369			`goto finish_up;`
370
371			`}`
372			`} else`
373	49	julius	`{`
374	462	julius	`/* No ELF file specified, default is to load from VMEM file */`
375			`if (!gQuiet)`
376			`cout <<`
377			`"* Loading memory with image from default file, sram.vmem"`
378			`<< endl;`
379			`accessor->do_ram_readmemh();`
380	49	julius	`}`
381	6	julius
382	462	julius	`gSimRunning = 1;`
383
384			`// First check how we should run the sim.`
385			`if (VCD_enabled \|\| finish_time_set) { // We'll run sim with step`
386
387			`if (!VCD_enabled && finish_time_set) {`
388			`// We just run the sim until the set finish time`
389			`sc_start((double)(finish_time.to_double()),`
390			`TIMESCALE_UNIT);`
391			`gSimRunning = 0;`
392			`sc_stop();`
393			`// Print performance summary`
394			`monitor->perfSummary();`
395			`// Do memdump if enabled`
396			`monitor->memdump();`
397			`} else {`
398			`if (dump_start_delay_set) {`
399			`// Run the sim until we want to dump`
400			`sc_start((double)(dump_start.to_double()),`
401			`TIMESCALE_UNIT);`
402			`// Open the trace file`
403			`verilatorVCDFile->open(vcdDumpFile.c_str());`
404			`dumping_now = 1;`
405	49	julius	`}`
406	462	julius
407			`if (dumping_now) {`
408			`// Step the sim and generate the trace`
409			`// Execute until we stop`
410			`while (!Verilated::gotFinish()) {`
411			`// gSimRunning value changed by the`
412			`// monitor when sim should finish.`
413			`if (gSimRunning)`
414			`// Step the sim`
415			`sc_start(1, TIMESCALE_UNIT);`
416			`else {`
417			`verilatorVCDFile->close();`
418			`break;`
419			`}`
420
421			`verilatorVCDFile->dump(sc_time_stamp().`
422			`to_double());`
423
424			`if (dump_stop_set) {`
425			`if (sc_time_stamp() >=`
426			`dump_stop) {`
427			`// Close dump file`
428			`verilatorVCDFile->close`
429			`();`
430			`// Now continue on again until the end`
431			`if (!finish_time_set)`
432			`sc_start();`
433			`else {`
434			`// Determine how long we should run for`
435			`sc_time`
436			`sim_time_remaining`
437			`=`
438			`finish_time`
439			`-`
440			`sc_time_stamp`
441			`();`
442			`sc_start((double)(sim_time_remaining.to_double()), TIMESCALE_UNIT);`
443			`// Officially stop the sim`
444			`sc_stop();`
445			`// Print performance summary`
446			`monitor->`
447			`perfSummary`
448			`();`
449			`// Do memdump if enabled`
450			`monitor->memdump`
451			`();`
452			`}`
453			`break;`
454			`}`
455			`}`
456			`if (finish_time_set) {`
457			`if (sc_time_stamp() >=`
458			`finish_time) {`
459			`// Officially stop the sim`
460			`sc_stop();`
461			`// Close dump file`
462			`verilatorVCDFile->close`
463			`();`
464			`// Do memdump if enabled`
465			`monitor->memdump();`
466			`// Print performance summary`
467			`monitor->perfSummary();`
468			`break;`
469			`}`
470			`}`
471			`}`
472	49	julius	`}`
473			`}`
474	462	julius	`} else {`
475			`// Simple run case`
476			`// Ideally a "l.nop 1" will terminate the simulation gracefully.`
477			`// Need to step at clock period / 4, otherwise model appears to skip the`
478			`// monitor and logging functions sometimes (?!?)`
479			`while (gSimRunning)`
480			`sc_start(BENCH_CLK_HALFPERIOD / 2, TIMESCALE_UNIT);`
481			`//sc_start();`
482	49	julius	`}`
483	462	julius
484
485			`finish_up:`
486			`// Free memory`
487	363	julius	`#ifdef JTAG_DEBUG`
488	462	julius	`if (rsp_server_enabled)`
489			`delete gdbServer;`
490	363	julius
491	462	julius	`delete jtag;`
492	363	julius	`#endif`
493
494	462	julius	`delete monitor;`
495	363	julius
496	462	julius	`delete reset;`
497	6	julius
498	462	julius	`delete accessor;`
499	6	julius
500	462	julius	`//delete trace;`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [OrpsocMain.cpp] - Blame information for rev 535