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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] [OrpsocMain.cpp] - Blame information for rev 70

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1 63 julius
/////////////////////////////////////////////////////////////////////
2 6 julius
////                                                              ////
3
////  ORPSoC SystemC Testbench                                    ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  ORPSoC Testbench file                                       ////
7
////                                                              ////
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////  To Do:                                                      ////
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////                                                              ////
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////                                                              ////
11
////  Author(s):                                                  ////
12
////      - Jeremy Bennett jeremy.bennett@embecosm.com            ////
13
////      - Julius Baxter jb@orsoc.se                             ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
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////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
#include "OrpsocMain.h"
44
 
45 64 julius
#include "JtagSC_includes.h"
46 63 julius
 
47 6 julius
#include "Vorpsoc_top.h"
48
#include "OrpsocAccess.h"
49 51 julius
#include "MemoryLoad.h"
50 49 julius
 
51 70 julius
#include <verilated_vcd_c.h>
52 49 julius
 
53 6 julius
#include "ResetSC.h"
54
#include "Or1200MonitorSC.h"
55 63 julius
#include "GdbServerSC.h"
56 6 julius
#include "UartSC.h"
57
 
58 49 julius
int SIM_RUNNING;
59 6 julius
int sc_main (int   argc,
60
             char *argv[] )
61
{
62 49 julius
  sc_set_time_resolution( 1, TIMESCALE_UNIT);
63 6 julius
  // CPU clock (also used as JTAG TCK) and reset (both active high and low)
64
  sc_time  clkPeriod (BENCH_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
65 63 julius
  sc_time   jtagPeriod (JTAG_CLK_HALFPERIOD * 2.0, TIMESCALE_UNIT);
66 6 julius
 
67
  sc_clock             clk ("clk", clkPeriod);
68 63 julius
  sc_clock  jtag_tck ("jtag-clk", jtagPeriod, 0.5, SC_ZERO_TIME, false);
69
 
70 6 julius
  sc_signal<bool>      rst;
71
  sc_signal<bool>      rstn;
72
  sc_signal<bool>      rst_o;
73
 
74
  sc_signal<bool>      jtag_tdi;                // JTAG interface
75
  sc_signal<bool>      jtag_tdo;
76
  sc_signal<bool>      jtag_tms;
77
  sc_signal<bool>      jtag_trst;
78
 
79
  sc_signal<bool>      uart_rx;         // External UART
80
  sc_signal<bool>      uart_tx;
81
 
82
  sc_signal<bool> spi_sd_sclk; // SD Card Memory SPI
83
  sc_signal<bool> spi_sd_ss;
84
  sc_signal<bool> spi_sd_miso;
85
  sc_signal<bool> spi_sd_mosi;
86
 
87
  sc_signal<uint32_t> gpio_a; // GPIO bus - output only in verilator sims
88
 
89
  sc_signal<bool> spi1_mosi;
90
  sc_signal<bool> spi1_miso;
91
  sc_signal<bool> spi1_ss;
92
  sc_signal<bool> spi1_sclk;
93
 
94 49 julius
  SIM_RUNNING = 0;
95 6 julius
 
96 49 julius
  // Setup the name of the VCD dump file
97 63 julius
  bool VCD_enabled = false;
98 49 julius
  string dumpNameDefault("vlt-dump.vcd");
99
  string testNameString;
100
  string vcdDumpFile;
101
  // VCD dump controling vars
102 63 julius
  bool dump_start_delay_set = false, dump_stop_set = false;
103
  bool dumping_now = false;
104 49 julius
  int dump_depth = 99; // Default dump depth
105
  sc_time dump_start,dump_stop, finish_time;
106 63 julius
  bool finish_time_set = false; // By default we will let the simulation finish naturally
107 70 julius
  VerilatedVcdC *verilatorVCDFile;
108 49 julius
 
109 63 julius
  /*int*/double time_val;
110
  bool vcd_file_name_given = false;
111 49 julius
 
112 63 julius
  bool rsp_server_enabled = false;
113
  int rsp_server_port = DEFAULT_RSP_PORT;
114
 
115 51 julius
  // Executable app load variables
116
  int do_program_file_load = 0; // Default: we don't require a file, we use the VMEM
117
  char* program_file; // Old char* style for program name
118
 
119 6 julius
  // Verilator accessor
120
  OrpsocAccess    *accessor;
121
 
122
  // Modules
123
  Vorpsoc_top *orpsoc;          // Verilated ORPSoC
124
 
125 51 julius
  MemoryLoad *memoryload;       // Memory loader
126
 
127 6 julius
  ResetSC          *reset;              // Generate a RESET signal
128
  Or1200MonitorSC  *monitor;            // Handle l.nop x instructions
129 63 julius
  JtagSC           *jtag;               // Generate JTAG signals
130
  GdbServerSC      *gdbServer;          // Map RSP requests to debug unit
131 6 julius
  UartSC          *uart;                // Handle UART signals
132
 
133
  // Instantiate the Verilator model, VCD trace handler and accessor
134
  orpsoc     = new Vorpsoc_top ("orpsoc");
135 51 julius
 
136 6 julius
  accessor   = new OrpsocAccess (orpsoc);
137
 
138 51 julius
  memoryload = new MemoryLoad (accessor);
139
 
140 63 julius
  monitor    = new Or1200MonitorSC ("monitor", accessor, memoryload,
141
                                    argc, argv);
142
 
143 6 julius
  // Instantiate the SystemC modules
144
  reset         = new ResetSC ("reset", BENCH_RESET_TIME);
145 63 julius
 
146
  jtag          = new JtagSC ("jtag");
147
 
148 6 julius
  uart          = new UartSC("uart"); // TODO: Probalby some sort of param
149
 
150 49 julius
  // Parse command line options
151
  // Default is for VCD generation OFF, only turned on if specified on command line
152
 
153 51 julius
  // Search through the command line parameters for options  
154 49 julius
  if (argc > 1)
155
    {
156
      for(int i=1; i<argc; i++)
157
        {
158 63 julius
          if ( (strcmp(argv[i], "-e")==0) ||
159
               (strcmp(argv[i], "--endtime")==0) )
160 49 julius
            {
161 63 julius
              time_val = strtod(argv[i+1], NULL);
162 49 julius
              sc_time opt_end_time(time_val,TIMESCALE_UNIT);
163
              finish_time = opt_end_time;
164 63 julius
              finish_time_set = true;
165 49 julius
            }
166 51 julius
          else if ( (strcmp(argv[i], "-f")==0) ||
167
                    (strcmp(argv[i], "--program")==0) )
168
            {
169
              do_program_file_load = 1; // Enable program loading - will be done after sim init
170
              program_file = argv[i+1]; // Old char* style for program name
171
            }
172 63 julius
          else if ((strcmp(argv[i], "-d")==0) ||
173
                   (strcmp(argv[i], "--vcdfile")==0) ||
174
                   (strcmp(argv[i], "-v")==0) ||
175
                   (strcmp(argv[i], "--vcdon")==0)
176
                   )
177
            {
178
              VCD_enabled = true;
179
              dumping_now = true;
180
              vcdDumpFile = dumpNameDefault;
181
              if (i+1 < argc)
182
                if(argv[i+1][0] != '-')
183
                  {
184
                    testNameString = argv[i+1];
185
                    vcdDumpFile = testNameString;
186
                    i++;
187
                  }
188
            }
189
          else if ( (strcmp(argv[i], "-s")==0) ||
190 49 julius
                    (strcmp(argv[i], "--vcdstart")==0) )
191
            {
192 63 julius
              VCD_enabled = true;
193
              time_val = strtod(argv[i+1], NULL);
194 49 julius
              sc_time dump_start_time(time_val,TIMESCALE_UNIT);
195
              dump_start = dump_start_time;
196 63 julius
              dump_start_delay_set = true;
197
              dumping_now = false;
198 49 julius
            }
199
          else if ( (strcmp(argv[i], "-t")==0) ||
200
                    (strcmp(argv[i], "--vcdstop")==0) )
201
            {
202 63 julius
              VCD_enabled = true;
203
              time_val = strtod(argv[i+1],NULL);
204 49 julius
              sc_time dump_stop_time(time_val,TIMESCALE_UNIT);
205
              dump_stop = dump_stop_time;
206 63 julius
              dump_stop_set = true;
207 49 julius
            }
208 63 julius
          else if ( (strcmp(argv[i], "-r")==0) ||
209
                    (strcmp(argv[i], "--rsp")==0) )
210
            {
211
              rsp_server_enabled = true;
212
              if (i+1 < argc) if(argv[i+1][0] != '-')
213
                                {
214
                                  rsp_server_port = atoi(argv[i+1]);
215
                                  i++;
216
                                }
217
            }
218
          /*
219
             Depth setting of VCD doesn't appear to work, I think it's only
220
             configurable during at compile time .
221
          */
222 49 julius
          /*      else if ( (strcmp(argv[i], "-p")==0) ||
223 51 julius
                  (strcmp(argv[i], "--vcddepth")==0) )
224
                  {
225
                  dump_depth = atoi(argv[i+1]);
226
                  }*/
227 49 julius
          else if ( (strcmp(argv[i], "-h")==0) ||
228
                    (strcmp(argv[i], "--help")==0) )
229
            {
230 63 julius
              printf("Usage: %s [options]\n",argv[0]);
231
              printf("\n  ORPSoCv2 cycle accurate model\n");
232
              printf("  For details visit http://opencores.org/openrisc,orpsocv2\n");
233
              printf("\n");
234
              printf("Options:\n");
235 49 julius
              printf("  -h, --help\t\tPrint this help message\n");
236 63 julius
              printf("\nSimulation control:\n");
237
              printf("  -f, --program <file> \tLoad program from OR32 ELF <file>\n");
238
              printf("  -e, --endtime <val> \tStop the sim at <val> ns\n");
239
              printf("\nVCD generation:\n");
240 49 julius
              printf("  -v, --vcdon\t\tEnable VCD generation\n");
241 63 julius
              printf("  -d, --vcdfile <file>\tEnable and save VCD to <file>\n");
242 49 julius
 
243 63 julius
              printf("  -s, --vcdstart <val>\tEnable and delay VCD generation until <val> ns\n");
244
              printf("  -t, --vcdstop <val> \tEnable and terminate VCD generation at <val> ns\n");
245
              printf("\nRemote debugging:\n");
246
              printf("  -r, --rsp [<port>]\tEnable RSP debugging server, opt. specify <port>\n");
247 49 julius
              monitor->printUsage();
248
              printf("\n");
249
              return 0;
250
            }
251
 
252
        }
253
    }
254 63 julius
 
255 49 julius
  // Determine if we're going to setup a VCD dump:
256 63 julius
  // Pretty much setting any related option will enable VCD dumping.
257
  if (VCD_enabled)
258 49 julius
    {
259
 
260
      cout << "* Enabling VCD trace";
261
 
262 63 julius
      if (dump_start_delay_set)
263 49 julius
        cout << ", on at time " << dump_start.to_string();
264
      if (dump_stop_set)
265 63 julius
        cout << ", off at time " << dump_stop.to_string();
266 49 julius
      cout << endl;
267
    }
268 63 julius
 
269
  if (rsp_server_enabled)
270
    gdbServer     = new GdbServerSC ("gdb-server", FLASH_START, FLASH_END,
271
                                       rsp_server_port, jtag->tapActionQueue);
272
  else
273
      gdbServer = NULL;
274
 
275 6 julius
  // Connect up ORPSoC
276
  orpsoc->clk_pad_i (clk);
277
  orpsoc->rst_pad_i (rstn);
278
  orpsoc->rst_pad_o (rst_o);
279
 
280 63 julius
  orpsoc->dbg_tck_pad_i  (jtag_tck);            // JTAG interface
281 6 julius
  orpsoc->dbg_tdi_pad_i  (jtag_tdi);
282
  orpsoc->dbg_tms_pad_i  (jtag_tms);
283
  orpsoc->dbg_tdo_pad_o  (jtag_tdo);
284
 
285
  orpsoc->uart0_srx_pad_i (uart_rx);            // External UART
286
  orpsoc->uart0_stx_pad_o (uart_tx);
287
 
288
  orpsoc->spi_sd_sclk_pad_o (spi_sd_sclk); // SD Card Memory SPI
289
  orpsoc->spi_sd_ss_pad_o (spi_sd_ss);
290
  orpsoc->spi_sd_miso_pad_i (spi_sd_miso);
291
  orpsoc->spi_sd_mosi_pad_o (spi_sd_mosi);
292
 
293
  orpsoc->spi1_mosi_pad_o (spi1_mosi);
294
  orpsoc->spi1_miso_pad_i (spi1_miso);
295
  orpsoc->spi1_ss_pad_o  (spi1_ss);
296
  orpsoc->spi1_sclk_pad_o (spi1_sclk);
297
 
298
 
299
  orpsoc->gpio_a_pad_io (gpio_a); // GPIO bus - output only in 
300
                                  // verilator sims
301
 
302
  // Connect up the SystemC  modules
303
  reset->clk (clk);                     // Reset
304
  reset->rst (rst);
305
  reset->rstn (rstn);
306
 
307
  monitor->clk (clk);                   // Monitor
308
 
309 63 julius
  jtag->sysReset (rst);                 // JTAG
310
  jtag->tck (jtag_tck);
311
  jtag->tdi (jtag_tdi);
312
  jtag->tdo (jtag_tdo);
313
  jtag->tms (jtag_tms);
314
  jtag->trst (jtag_trst);
315
 
316 6 julius
  uart->clk (clk); // Uart
317
  uart->uartrx (uart_rx); // orpsoc's receive line
318
  uart->uarttx (uart_tx); // orpsoc's transmit line
319
 
320 63 julius
  // Tie off signals
321
  jtag_tdi      = 1;                    // Tie off the JTAG inputs
322
  jtag_tms      = 1;
323
 
324
  spi_sd_miso = 0; // Tie off master-in/slave-out of SD SPI bus
325 6 julius
 
326
  spi1_miso = 0;
327 49 julius
 
328 63 julius
 
329 49 julius
  if (VCD_enabled)
330
    {
331
      Verilated::traceEverOn (true);
332
 
333
      printf("* VCD dumpfile: %s\n", vcdDumpFile.c_str());
334
 
335
      // Establish a new trace with its correct time resolution, and trace to
336
      // great depth.
337 70 julius
      verilatorVCDFile = new VerilatedVcdC ();
338
      //verilatorVCDFile->verilated()->set_time_resolution (sc_get_time_resolution());
339 49 julius
      //setSpTimeResolution (sc_get_time_resolution ());
340 70 julius
      //traceTarget->trace (verilatorVCDFile, 99);
341
      orpsoc->trace (verilatorVCDFile, dump_depth);
342 49 julius
 
343
      if (dumping_now)
344
        {
345 70 julius
          verilatorVCDFile->open (vcdDumpFile.c_str());
346 49 julius
        }
347
    }
348 6 julius
 
349 52 julius
  //printf("* Beginning test\n");
350 6 julius
 
351
  // Init the UART function
352
  uart->initUart(25000000, 115200);
353
 
354 51 julius
  if (do_program_file_load) // Did the user specify a file to load?
355
    {
356
      cout << "* Loading program from " << program_file << endl;
357
      if (memoryload->loadcode(program_file,0,0) < 0)
358
        {
359
          cout << "* Error: executable file " << program_file << " not loaded" << endl;
360
        }
361
    }
362
  else // Load SRAM from VMEM file
363
    {
364
      accessor->do_ram_readmemh();
365
    }
366 44 julius
 
367 51 julius
  SIM_RUNNING = 1;
368
 
369 49 julius
  // First check how we should run the sim.
370
  if (VCD_enabled || finish_time_set)
371
    { // We'll run sim with step
372
 
373
      if (!VCD_enabled && finish_time_set)
374
        {
375
          // We just run the sim until the set finish time
376
          sc_start((double)(finish_time.to_double()), TIMESCALE_UNIT);
377
          SIM_RUNNING=0;
378
          sc_stop();
379
          // Print performance summary
380 52 julius
          monitor->perfSummary();
381
          // Do memdump if enabled
382
          monitor->memdump();
383 49 julius
        }
384
      else
385
        {
386 63 julius
          if (dump_start_delay_set)
387 49 julius
            {
388
              // Run the sim until we want to dump
389
              sc_start((double)(dump_start.to_double()),TIMESCALE_UNIT);
390
              // Open the trace file
391 70 julius
              verilatorVCDFile->open (vcdDumpFile.c_str());
392 49 julius
              dumping_now = 1;
393
            }
394 6 julius
 
395 49 julius
          if (dumping_now)
396
            {
397
              // Step the sim and generate the trace
398
                  // Execute until we stop
399
              while(!Verilated::gotFinish())
400
                {
401
                  if (SIM_RUNNING) // Changed by Or1200MonitorSC when finish NOP
402
                    sc_start (1,TIMESCALE_UNIT); // Step the sim
403
                  else
404
                    {
405 70 julius
                      verilatorVCDFile->close();
406 49 julius
                      break;
407
                    }
408
 
409 70 julius
                  verilatorVCDFile->dump (sc_time_stamp().to_double());
410 49 julius
 
411
                  if (dump_stop_set)
412
                    {
413
                      if (sc_time_stamp() >=  dump_stop)
414
                        {
415
                          // Close dump file
416 70 julius
                          verilatorVCDFile->close();
417 49 julius
                          // Now continue on again until the end
418
                          if (!finish_time_set)
419
                            sc_start();
420
                          else
421
                            {
422
                              // Determine how long we should run for
423
                              sc_time sim_time_remaining =
424
                                finish_time - sc_time_stamp();
425
                              sc_start((double)(sim_time_remaining.to_double()),
426
                                       TIMESCALE_UNIT);
427
                              // Officially stop the sim
428
                              sc_stop();
429
                              // Print performance summary
430
                              monitor->perfSummary();
431 52 julius
                              // Do memdump if enabled
432
                              monitor->memdump();
433 49 julius
                            }
434
                          break;
435
                        }
436
                    }
437
                  if (finish_time_set)
438
                    {
439
                      if (sc_time_stamp() >=  finish_time)
440
                        {
441
                          // Officially stop the sim
442
                          sc_stop();
443
                          // Close dump file
444 70 julius
                          verilatorVCDFile->close();
445 52 julius
                          // Do memdump if enabled
446
                          monitor->memdump();
447 49 julius
                          // Print performance summary
448
                          monitor->perfSummary();
449
                          break;
450
                        }
451
                    }
452
                }
453
            }
454
        }
455
    }
456
  else
457
    {
458
      // Simple run case
459 52 julius
      // Ideally a "l.nop 1" will terminate the simulation gracefully
460 64 julius
      // Need to step at clock period / 4, otherwise model appears to skip the monitor and logging functions sometimes (?!?)
461
      while (SIM_RUNNING)
462
        sc_start(BENCH_CLK_HALFPERIOD / 2, TIMESCALE_UNIT);
463
      //sc_start();
464 49 julius
    }
465
 
466
 
467 6 julius
  // Free memory
468 63 julius
  if (rsp_server_enabled)
469
    delete gdbServer;
470
  delete jtag;
471 6 julius
  delete monitor;
472
  delete reset;
473
 
474
  delete accessor;
475
 
476 49 julius
  //delete trace;
477 6 julius
  delete orpsoc;
478
 
479
  return 0;
480
 
481
}       /* sc_main() */

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