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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [include/] [cfi_flash_TimingData.h] - Blame information for rev 824

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//          _/             _/_/
//        _/_/           _/_/_/
//      _/_/_/_/         _/_/_/
//      _/_/_/_/_/       _/_/_/              ____________________________________________ 
//      _/_/_/_/_/       _/_/_/             /                                           / 
//      _/_/_/_/_/       _/_/_/            /                                 28F256P30 / 
//      _/_/_/_/_/       _/_/_/           /                                           /  
//      _/_/_/_/_/_/     _/_/_/          /                                   256Mbit / 
//      _/_/_/_/_/_/     _/_/_/         /                                single die / 
//      _/_/_/ _/_/_/    _/_/_/        /                                           / 
//      _/_/_/  _/_/_/   _/_/_/       /                  Verilog Behavioral Model / 
//      _/_/_/   _/_/_/  _/_/_/      /                               Version 1.3 / 
//      _/_/_/    _/_/_/ _/_/_/     /                                           /
//      _/_/_/     _/_/_/_/_/_/    /           Copyright (c) 2010 Numonyx B.V. / 
//      _/_/_/      _/_/_/_/_/    /___________________________________________/ 
//      _/_/_/       _/_/_/_/      
//      _/_/          _/_/_/  
// 
//     
//             NUMONYX              
`include "cfi_flash_data.h"
`include "cfi_flash_UserData.h"
 
`define Reset_time  300000
 
// *********************************************
//
// Table 29 
//      Program/Erase Characteristics
// 
// *********************************************
 
// Vpp = VppL
 
/*
// Too long!
`define ParameterBlockErase_time         800000000//  0.8 sec
`define MainBlockErase_time        800000000
*/
 
/* erase times much reduced for simulation - Julius */
`define ParameterBlockErase_time         8000//  800ns sec
`define MainBlockErase_time        8000
 
/*
`define WordProgram_time                  150000   //      150 us
`define ParameterBlockProgram_time       272000   //   32000 us =  32 ms???????verificare
`define MainBlockProgram_time            700000   //  256000 us = 256 ms???????verificare
*/
 
`define WordProgram_time                  1500   //      150 us
`define ParameterBlockProgram_time       2720   //   32000 us =  32 ms???????verificare
`define MainBlockProgram_time            7000   //  256000 us = 256 ms???????verificare
 
`define ProgramSuspendLatency_time         20000   //      20 us
`define EraseSuspendLatency_time           20000   //      20 us
`define MainBlankCheck_time                     3200000
// Vpp = VppH
 
`define FastParameterBlockErase_time        800000000    //  0.8 sec
`define FastMainBlockErase_time             800000000    //  0.8 sec
`define FastWordProgram_time                 150000    //  8   us
`define FastParameterBlockProgram_time     272000   //  32 ms
`define FastMainBlockProgram_time      700000  //  256000 us = 256 ms 
 
`define BlockProtect_time                     1800
`define BlockUnProtect_time                   5000000
 
`define ProgramBuffer_time                     700000
 
 
`define EnhBuffProgram_time                     512000 //
`define EnhBuffProgramSetupPhase_time             5000
 
 
 
// **********************
//
// Timing Data Module :
//      set timing values
//
// **********************
 
module TimingDataModule;
 
// ************************************
//
//  AC Read Specifications
//
//      Table 27
//
// ************************************
 
integer tAVAV;                   // Address Valid to Next Address Valid
integer tAVQV;                   // Address Valid to Output Valid (Random)
integer tAVQV1;                  // Address Valid to Output Valid (Page)
integer tELTV;                   // Chip Enable Low to Wait Valid
integer tELQV;                   // Chip Enable Low to Output Valid
integer tELQX;                   // Chip Enable Low to Output Transition
integer tEHTZ;                 // Chip Enable High to Wait Hi-Z
integer tEHQX;//tOH                   // Chip Enable High to Output Transition
integer tEHQZ;                   // Chip Enable High to Output Hi-Z
integer tGLQV;                   // Output Enable Low to Output Valid 
integer tGLQX;                   // Output Enable Low to Output Transition
integer tGHQZ;                   // Output Enable High to Output Hi-Z
integer tAVLH;//tAVVH                   // Address Valid to (ADV#) Latch Enable High
integer tELLH;  //tELVH                 // Chip Enable Low to Latch Enable High
integer tLHAX;  //tVHAX                 // Latch Enable High to Address Transition
integer tLLLH;  //tVLVH                 // Latch Enable Low to Latch Enable High
integer tLLQV; //tVLQV                  // Latch Enable Low to Output Valid
 
integer tGLTV; //// Output Enable Low to Wait Valid
integer tGLTX; //// Output Enable Low to Wait Transition
integer tGHTZ; //// Output Enable high to Wait Hi-Z
 
 
 
 
 
integer tAVKH;  //tAVCH/L      // Address Valid to Clock High
integer tELKH;    //tELCH            // Chip Enable Low to Clock High
integer tEHEL;// tEHEL              // Chip Enable High to Chip Enable Low (reading)
integer tKHAX;//tCHAX                // Clock High to Address Transition
integer tKHQV; //tCHQV               // Clock High to Output Enable Valid
integer tKHTV;   //tCHTV             // Clock High to Wait Valid
integer tKHQX;   //tCHQX             // Clock High to Output Enable Transition
integer tKHTX; //tCHTX                // Clock High to Wait Transition
integer tLLKH;  //tVLCH/L              // Latch Enable Low to Clock High
integer tLLKL;  //tVLCH/L              // Latch Enable Low to Clock High
integer tKHLL;  //tCHVL               //Clock valid to ADV# setup  
integer tKHKH;  //tCLK               // Clock Period
integer tKHKL; //tCH/CL               // Clock High to Clock Low
integer tKLKH;                      // Clock Low to Clock High
integer tCK_fall; //R203            // Clock Fall Time
integer tCK_rise;             // Clock Rise Time
 
 
// *************************************************
//
//  AC Write Specifications
//
//      Table 28
//
// *************************************************
 
integer tAVWH;                  // Address Valid to Write Enable High
integer tDVWH;                  // Data Valid to Write Enable High
integer tELWL;                  // Chip Enable Low to Write Enable Low
integer tWHAV;  //W18           // Write Enable High to Address Valid
integer tWHAX;                  // Write Enable High to Address Transition
integer tWHDX;                  // Write Enable High to Data Transition
integer tWHEH;                  // Write Enable High to Chip Enable High
integer tWHGL;                  // Write Enable High to Output Enable High
integer tWHLL; //W28 tWHVL      // Write Enable High to Latch Enable Low
integer tWHWL;                  // Write Enable High to Latch Enable Low
integer tWHQV;                  // Write Enable High to Output Enable Valid
integer tWLWH;                  // Write Enable Low to Write Enable High
integer tQVVPL; //tQVVL         // Output (Status Register) Valid to Vpp Low
integer tQVWPL;   //tQVBL       // Output (Status Register) Valid to Write Protect Low
integer tVPHWH;                  // Vpp High to Write Enable High
integer tWPHWH;   //tBHWH               // Write Protect High to Write Enable High
 
 
integer tELEH;                // Chip Enable Low to Chip Enable High
 
 
//!// *************************************
//!//
//!// Power and Reset
//!//
//!//      Table 20
//!//
//!// **************************************
 
integer tPHWL; //W1                 // Reset High to Write Enable Low
integer tPLPH;//P1                  // Reset High to Reset Low
 
integer tVDHPH;  //tVCCPH               // Supply voltages High to Reset High
 
 
 
initial begin
 
       setTiming(`t_access);
 
end
 
// **********************
//
// FUNCTION getTime :
//      return time value
//
// **********************
 
function getTime;
 
input [8*31 : 0] time_str;
 
begin
 
 
 
end
endfunction
 
// **********************
//
// Task setTiming :
//      set timing values
//
// **********************
 
task setTiming;
 
input time_access;
 
integer time_access;
 
begin
 
        // ***********************************************
        //
        // AC Read Specifications
        //
        //      Table 27
        //
        // ***********************************************
 
        tELQX    =  0;
        tEHQX    =  0;
        tGLQX    =  0;
        tGHQZ    = 15;
        tELLH    = 10;
 
        tAVAV  =  time_access;
        tAVQV  =  time_access;
        tELQV  =  time_access;
        tLLQV  =  time_access;
 
        tEHTZ    =  20;
        tAVQV1   =  25;
        tELTV    =  17;
 
        tEHEL  = 17;
        tCK_fall =  3;
        tCK_rise =  3;
         tEHQZ    =  20;
                                tGLQV    =  25;
                                tAVLH    =  10;
                                tLHAX    =   9;
                                tLLLH    =  10;
 
                                tAVKH    =   9;
                                tELKH    =   9;
                                tKHAX    =   10;
                                tKHQV    =  17;
                                tKHTV    =  17;
                                tKHQX    =   3;
                                tKHTX    =   3;
                                tLLKH    =   9;
                                tLLKL    =   9;
                                tKHLL    =   3;
                                tKHKH    =  19.2;
                                tKHKL    =   5;
                                tKLKH    =   5;
                                tGLTV    =   17;
                                tGLTX    =   0;
                                tGHTZ    =   20;
 
// *************************************************
//
//  AC Write Specifications
//
//      Table 28
//
// *************************************************
 
        tELWL    =    0;
        tWHAV    =    0;
        tWHAX    =    0;
        tWHDX    =    0;
        tWHEH    =    0;
        tWHGL    =    0;
        tWHLL    =    7;
        tQVVPL   =    0;
        tQVWPL   =    0;
        tVPHWH   =  200;
        tWPHWH   =  200;
        tAVWH    =  50;
 
                                tDVWH    =  50;
                                tWHWL    =  20;
                                tWHQV    =  tAVQV + 35;  //tAVQV+35 
                                tWLWH    =  50;
                                tELEH    =  50;
 
// *************************************
//
// Power and Reset
//
//      Table 20
//
// **************************************
 
        tPHWL           = 150;
        tPLPH           =  100;
        tVDHPH          =  300;
 
 
end
endtask
 
endmodule
 

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [include/] [cfi_flash_TimingData.h] - Blame information for rev 824

Line No.	Rev	Author	Line
1	655	julius	`// _/ _/_/`
2			`// _/_/ _/_/_/`
3			`// _/_/_/_/ _/_/_/`
4			`// _/_/_/_/_/ _/_/_/ ____________________________________________`
5			`// _/_/_/_/_/ _/_/_/ / /`
6			`// _/_/_/_/_/ _/_/_/ / 28F256P30 /`
7			`// _/_/_/_/_/ _/_/_/ / /`
8			`// _/_/_/_/_/_/ _/_/_/ / 256Mbit /`
9			`// _/_/_/_/_/_/ _/_/_/ / single die /`
10			`// _/_/_/ _/_/_/ _/_/_/ / /`
11			`// _/_/_/ _/_/_/ _/_/_/ / Verilog Behavioral Model /`
12			`// _/_/_/ _/_/_/ _/_/_/ / Version 1.3 /`
13			`// _/_/_/ _/_/_/ _/_/_/ / /`
14			`// _/_/_/ _/_/_/_/_/_/ / Copyright (c) 2010 Numonyx B.V. /`
15			`// _/_/_/ _/_/_/_/_/ /___________________________________________/`
16			`// _/_/_/ _/_/_/_/`
17			`// _/_/ _/_/_/`
18			`//`
19			`//`
20			`// NUMONYX`
21			`include "cfi_flash_data.h"
22			`include "cfi_flash_UserData.h"
23
24			`define Reset_time 300000
25
26			`// *********************************************`
27			`//`
28			`// Table 29`
29			`// Program/Erase Characteristics`
30			`//`
31			`// *********************************************`
32
33			`// Vpp = VppL`
34
35			`/*`
36			`// Too long!`
37			`define ParameterBlockErase_time 800000000// 0.8 sec
38			`define MainBlockErase_time 800000000
39			`*/`
40
41			`/* erase times much reduced for simulation - Julius */`
42			`define ParameterBlockErase_time 8000// 800ns sec
43			`define MainBlockErase_time 8000
44
45			`/*`
46			`define WordProgram_time 150000 // 150 us
47			`define ParameterBlockProgram_time 272000 // 32000 us = 32 ms???????verificare
48			`define MainBlockProgram_time 700000 // 256000 us = 256 ms???????verificare
49			`*/`
50
51			`define WordProgram_time 1500 // 150 us
52			`define ParameterBlockProgram_time 2720 // 32000 us = 32 ms???????verificare
53			`define MainBlockProgram_time 7000 // 256000 us = 256 ms???????verificare
54
55			`define ProgramSuspendLatency_time 20000 // 20 us
56			`define EraseSuspendLatency_time 20000 // 20 us
57			`define MainBlankCheck_time 3200000
58			`// Vpp = VppH`
59
60			`define FastParameterBlockErase_time 800000000 // 0.8 sec
61			`define FastMainBlockErase_time 800000000 // 0.8 sec
62			`define FastWordProgram_time 150000 // 8 us
63			`define FastParameterBlockProgram_time 272000 // 32 ms
64			`define FastMainBlockProgram_time 700000 // 256000 us = 256 ms
65
66			`define BlockProtect_time 1800
67			`define BlockUnProtect_time 5000000
68
69			`define ProgramBuffer_time 700000
70
71
72			`define EnhBuffProgram_time 512000 //
73			`define EnhBuffProgramSetupPhase_time 5000
74
75
76
77			`// **********************`
78			`//`
79			`// Timing Data Module :`
80			`// set timing values`
81			`//`
82			`// **********************`
83
84			`module TimingDataModule;`
85
86			`// ************************************`
87			`//`
88			`// AC Read Specifications`
89			`//`
90			`// Table 27`
91			`//`
92			`// ************************************`
93
94			`integer tAVAV; // Address Valid to Next Address Valid`
95			`integer tAVQV; // Address Valid to Output Valid (Random)`
96			`integer tAVQV1; // Address Valid to Output Valid (Page)`
97			`integer tELTV; // Chip Enable Low to Wait Valid`
98			`integer tELQV; // Chip Enable Low to Output Valid`
99			`integer tELQX; // Chip Enable Low to Output Transition`
100			`integer tEHTZ; // Chip Enable High to Wait Hi-Z`
101			`integer tEHQX;//tOH // Chip Enable High to Output Transition`
102			`integer tEHQZ; // Chip Enable High to Output Hi-Z`
103			`integer tGLQV; // Output Enable Low to Output Valid`
104			`integer tGLQX; // Output Enable Low to Output Transition`
105			`integer tGHQZ; // Output Enable High to Output Hi-Z`
106			`integer tAVLH;//tAVVH // Address Valid to (ADV#) Latch Enable High`
107			`integer tELLH; //tELVH // Chip Enable Low to Latch Enable High`
108			`integer tLHAX; //tVHAX // Latch Enable High to Address Transition`
109			`integer tLLLH; //tVLVH // Latch Enable Low to Latch Enable High`
110			`integer tLLQV; //tVLQV // Latch Enable Low to Output Valid`
111
112			`integer tGLTV; //// Output Enable Low to Wait Valid`
113			`integer tGLTX; //// Output Enable Low to Wait Transition`
114			`integer tGHTZ; //// Output Enable high to Wait Hi-Z`
115
116
117
118
119
120			`integer tAVKH; //tAVCH/L // Address Valid to Clock High`
121			`integer tELKH; //tELCH // Chip Enable Low to Clock High`
122			`integer tEHEL;// tEHEL // Chip Enable High to Chip Enable Low (reading)`
123			`integer tKHAX;//tCHAX // Clock High to Address Transition`
124			`integer tKHQV; //tCHQV // Clock High to Output Enable Valid`
125			`integer tKHTV; //tCHTV // Clock High to Wait Valid`
126			`integer tKHQX; //tCHQX // Clock High to Output Enable Transition`
127			`integer tKHTX; //tCHTX // Clock High to Wait Transition`
128			`integer tLLKH; //tVLCH/L // Latch Enable Low to Clock High`
129			`integer tLLKL; //tVLCH/L // Latch Enable Low to Clock High`
130			`integer tKHLL; //tCHVL //Clock valid to ADV# setup`
131			`integer tKHKH; //tCLK // Clock Period`
132			`integer tKHKL; //tCH/CL // Clock High to Clock Low`
133			`integer tKLKH; // Clock Low to Clock High`
134			`integer tCK_fall; //R203 // Clock Fall Time`
135			`integer tCK_rise; // Clock Rise Time`
136
137
138			`// *************************************************`
139			`//`
140			`// AC Write Specifications`
141			`//`
142			`// Table 28`
143			`//`
144			`// *************************************************`
145
146			`integer tAVWH; // Address Valid to Write Enable High`
147			`integer tDVWH; // Data Valid to Write Enable High`
148			`integer tELWL; // Chip Enable Low to Write Enable Low`
149			`integer tWHAV; //W18 // Write Enable High to Address Valid`
150			`integer tWHAX; // Write Enable High to Address Transition`
151			`integer tWHDX; // Write Enable High to Data Transition`
152			`integer tWHEH; // Write Enable High to Chip Enable High`
153			`integer tWHGL; // Write Enable High to Output Enable High`
154			`integer tWHLL; //W28 tWHVL // Write Enable High to Latch Enable Low`
155			`integer tWHWL; // Write Enable High to Latch Enable Low`
156			`integer tWHQV; // Write Enable High to Output Enable Valid`
157			`integer tWLWH; // Write Enable Low to Write Enable High`
158			`integer tQVVPL; //tQVVL // Output (Status Register) Valid to Vpp Low`
159			`integer tQVWPL; //tQVBL // Output (Status Register) Valid to Write Protect Low`
160			`integer tVPHWH; // Vpp High to Write Enable High`
161			`integer tWPHWH; //tBHWH // Write Protect High to Write Enable High`
162
163
164			`integer tELEH; // Chip Enable Low to Chip Enable High`
165
166
167			`//!// *************************************`
168			`//!//`
169			`//!// Power and Reset`
170			`//!//`
171			`//!// Table 20`
172			`//!//`
173			`//!// **************************************`
174
175			`integer tPHWL; //W1 // Reset High to Write Enable Low`
176			`integer tPLPH;//P1 // Reset High to Reset Low`
177
178			`integer tVDHPH; //tVCCPH // Supply voltages High to Reset High`
179
180
181
182			`initial begin`
183
184			setTiming(`t_access);
185
186			`end`
187
188			`// **********************`
189			`//`
190			`// FUNCTION getTime :`
191			`// return time value`
192			`//`
193			`// **********************`
194
195			`function getTime;`
196
197			`input [8*31 : 0] time_str;`
198
199			`begin`
200
201
202
203			`end`
204			`endfunction`
205
206			`// **********************`
207			`//`
208			`// Task setTiming :`
209			`// set timing values`
210			`//`
211			`// **********************`
212
213			`task setTiming;`
214
215			`input time_access;`
216
217			`integer time_access;`
218
219			`begin`
220
221			`// ***********************************************`
222			`//`
223			`// AC Read Specifications`
224			`//`
225			`// Table 27`
226			`//`
227			`// ***********************************************`
228
229			`tELQX = 0;`
230			`tEHQX = 0;`
231			`tGLQX = 0;`
232			`tGHQZ = 15;`
233			`tELLH = 10;`
234
235			`tAVAV = time_access;`
236			`tAVQV = time_access;`
237			`tELQV = time_access;`
238			`tLLQV = time_access;`
239
240			`tEHTZ = 20;`
241			`tAVQV1 = 25;`
242			`tELTV = 17;`
243
244			`tEHEL = 17;`
245			`tCK_fall = 3;`
246			`tCK_rise = 3;`
247			`tEHQZ = 20;`
248			`tGLQV = 25;`
249			`tAVLH = 10;`
250			`tLHAX = 9;`
251			`tLLLH = 10;`
252
253			`tAVKH = 9;`
254			`tELKH = 9;`
255			`tKHAX = 10;`
256			`tKHQV = 17;`
257			`tKHTV = 17;`
258			`tKHQX = 3;`
259			`tKHTX = 3;`
260			`tLLKH = 9;`
261			`tLLKL = 9;`
262			`tKHLL = 3;`
263			`tKHKH = 19.2;`
264			`tKHKL = 5;`
265			`tKLKH = 5;`
266			`tGLTV = 17;`
267			`tGLTX = 0;`
268			`tGHTZ = 20;`
269
270			`// *************************************************`
271			`//`
272			`// AC Write Specifications`
273			`//`
274			`// Table 28`
275			`//`
276			`// *************************************************`
277
278			`tELWL = 0;`
279			`tWHAV = 0;`
280			`tWHAX = 0;`
281			`tWHDX = 0;`
282			`tWHEH = 0;`
283			`tWHGL = 0;`
284			`tWHLL = 7;`
285			`tQVVPL = 0;`
286			`tQVWPL = 0;`
287			`tVPHWH = 200;`
288			`tWPHWH = 200;`
289			`tAVWH = 50;`
290
291			`tDVWH = 50;`
292			`tWHWL = 20;`
293			`tWHQV = tAVQV + 35; //tAVQV+35`
294			`tWLWH = 50;`
295			`tELEH = 50;`
296
297			`// *************************************`
298			`//`
299			`// Power and Reset`
300			`//`
301			`// Table 20`
302			`//`
303			`// **************************************`
304
305			`tPHWL = 150;`
306			`tPLPH = 100;`
307			`tVDHPH = 300;`
308
309
310			`end`
311			`endtask`
312
313			`endmodule`
314