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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [include/] [or1200_monitor_defines.v] - Blame information for rev 856

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//
// Top of TB
//
`define TB_TOP orpsoc_testbench
 
//
// Top of DUT
//
`define DUT_TOP `TB_TOP.dut
 
//
// Top of OR1200 inside test bench
//
`define OR1200_TOP `DUT_TOP.or1200_top0
 
//
// Define to enable lookup file generation
//
//`define OR1200_MONITOR_LOOKUP
 
//
// Define to enable SPR access log file generation
//
//`define OR1200_MONITOR_SPRS
 
//
// Enable logging of state during execution
//
//`define OR1200_MONITOR_EXEC_STATE
 
//
// Enable disassembly of instructions in execution state log
//
//`define OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
 
//
// Enable verbose report l.nops (to both general log file and stdout)
//
`define OR1200_MONITOR_VERBOSE_NOPS
 
//
// Enable monitoring of control and execution flow (experimental)
//
//`define OR1200_SYSTEM_CHECKER
 
// Can either individually enable things above, or usually have the scripts
// running the simulation pass the PROCESSOR_MONITOR_ENABLE_LOGS define to
// enable them all.
 
`ifdef PROCESSOR_MONITOR_ENABLE_LOGS
 `define OR1200_MONITOR_EXEC_STATE
 `define OR1200_MONITOR_SPRS
 `define OR1200_MONITOR_LOOKUP
`endif
 
//
// Memory coherence checking (double check instruction in fetch stage against
// what is in memory.) Useful for cache controller development.
//
//`define MEM_COHERENCE_CHECK
 
//
// Top of OR1200 inside test bench
//
`define CPU or1200
`define CPU_cpu or1200_cpu
`define CPU_rf or1200_rf
`define CPU_except or1200_except
`define CPU_ctrl or1200_ctrl
`define CPU_sprs or1200_sprs
`define CPU_immu_top or1200_immu_top
`define CPU_immu_tlb or1200_immu_tlb
`define CPU_CORE_CLK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk
 
 
`define OR1K_OPCODE_POS 31:26
`define OR1K_J_BR_IMM_POS 25:0
`define OR1K_RD_POS 25:21
`define OR1K_RA_POS 20:16
`define OR1K_RB_POS 15:11
`define OR1K_ALU_OP_POS 3:0
 
`define OR1K_SHROT_OP_POS 7:6
`define OR1K_SHROTI_IMM_POS 5:0
`define OR1K_SF_OP 25:21
 
`define OR1K_XSYNC_OP_POS 25:21

Line No.	Rev	Author	Line
1	485	julius
2			`//`
3			`// Top of TB`
4			`//`
5			`define TB_TOP orpsoc_testbench
6
7			`//`
8			`// Top of DUT`
9			`//`
10			`define DUT_TOP `TB_TOP.dut
11
12			`//`
13			`// Top of OR1200 inside test bench`
14			`//`
15			`define OR1200_TOP `DUT_TOP.or1200_top0
16
17			`//`
18			`// Define to enable lookup file generation`
19			`//`
20			//`define OR1200_MONITOR_LOOKUP
21
22			`//`
23			`// Define to enable SPR access log file generation`
24			`//`
25			//`define OR1200_MONITOR_SPRS
26
27			`//`
28			`// Enable logging of state during execution`
29			`//`
30			//`define OR1200_MONITOR_EXEC_STATE
31
32			`//`
33			`// Enable disassembly of instructions in execution state log`
34			`//`
35			//`define OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
36
37			`//`
38			`// Enable verbose report l.nops (to both general log file and stdout)`
39			`//`
40			`define OR1200_MONITOR_VERBOSE_NOPS
41
42			`//`
43			`// Enable monitoring of control and execution flow (experimental)`
44			`//`
45			//`define OR1200_SYSTEM_CHECKER
46
47			`// Can either individually enable things above, or usually have the scripts`
48			`// running the simulation pass the PROCESSOR_MONITOR_ENABLE_LOGS define to`
49			`// enable them all.`
50
51			`ifdef PROCESSOR_MONITOR_ENABLE_LOGS
52			`define OR1200_MONITOR_EXEC_STATE
53			`define OR1200_MONITOR_SPRS
54			`define OR1200_MONITOR_LOOKUP
55			`endif
56
57			`//`
58			`// Memory coherence checking (double check instruction in fetch stage against`
59			`// what is in memory.) Useful for cache controller development.`
60			`//`
61			//`define MEM_COHERENCE_CHECK
62
63			`//`
64			`// Top of OR1200 inside test bench`
65			`//`
66			`define CPU or1200
67			`define CPU_cpu or1200_cpu
68			`define CPU_rf or1200_rf
69			`define CPU_except or1200_except
70			`define CPU_ctrl or1200_ctrl
71			`define CPU_sprs or1200_sprs
72			`define CPU_immu_top or1200_immu_top
73			`define CPU_immu_tlb or1200_immu_tlb
74			`define CPU_CORE_CLK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk
75
76
77			`define OR1K_OPCODE_POS 31:26
78			`define OR1K_J_BR_IMM_POS 25:0
79			`define OR1K_RD_POS 25:21
80			`define OR1K_RA_POS 20:16
81			`define OR1K_RB_POS 15:11
82			`define OR1K_ALU_OP_POS 3:0
83
84			`define OR1K_SHROT_OP_POS 7:6
85			`define OR1K_SHROTI_IMM_POS 5:0
86			`define OR1K_SF_OP 25:21
87
88			`define OR1K_XSYNC_OP_POS 25:21

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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [include/] [or1200_monitor_defines.v] - Blame information for rev 856