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1 6 julius 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 449 julius 
////  or1200_monitor.v                                            ////
4 360 julius 
////                                                              ////
5 
////  OR1200 processor monitor module                             ////
6 
////                                                              ////
7 449 julius 
////  Author(s):                                                  ////
8 
////      - Damjan Lampret, lampret@opencores.org                 ////
9 
////      - Julius Baxter, julius@opencores.org                   ////
10 
////                                                              ////
11 360 julius 
//////////////////////////////////////////////////////////////////////
12 
////                                                              ////
13 348 julius 
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
14 6 julius 
////                                                              ////
15 
//// This source file may be used and distributed without         ////
16 
//// restriction provided that this copyright statement is not    ////
17 
//// removed from the file and that any derivative work contains  ////
18 
//// the original copyright notice and the associated disclaimer. ////
19 
////                                                              ////
20 
//// This source file is free software; you can redistribute it   ////
21 
//// and/or modify it under the terms of the GNU Lesser General   ////
22 
//// Public License as published by the Free Software Foundation; ////
23 
//// either version 2.1 of the License, or (at your option) any   ////
24 
//// later version.                                               ////
25 
////                                                              ////
26 
//// This source is distributed in the hope that it will be       ////
27 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
28 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
29 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
30 
//// details.                                                     ////
31 
////                                                              ////
32 
//// You should have received a copy of the GNU Lesser General    ////
33 
//// Public License along with this source; if not, download it   ////
34 
//// from http://www.opencores.org/lgpl.shtml                     ////
35 
////                                                              ////
36 
//////////////////////////////////////////////////////////////////////
37 67 julius 
 
38 55 julius 
`include "timescale.v"
39 6 julius 
`include "or1200_defines.v"
40 360 julius 
`include "orpsoc-testbench-defines.v"
41 
`include "test-defines.v"
42 415 julius 
 
43 6 julius 
//
44 415 julius 
// Top of TB
45 
//
46 
`define TB_TOP orpsoc_testbench
47 449 julius 
 
48 415 julius 
//
49 
// Top of DUT
50 
//
51 
`define DUT_TOP `TB_TOP.dut
52 449 julius 
 
53 415 julius 
//
54 6 julius 
// Top of OR1200 inside test bench
55 
//
56 415 julius 
`define OR1200_TOP `DUT_TOP.or1200_top0
57 360 julius 
 
58 397 julius 
//
59 
// Define to enable lookup file generation
60 
//
61 
//`define OR1200_MONITOR_LOOKUP
62 360 julius 
 
63 6 julius 
//
64 397 julius 
// Define to enable SPR access log file generation
65 6 julius 
//
66 397 julius 
//`define OR1200_MONITOR_SPRS
67 6 julius 
 
68 348 julius 
//
69 397 julius 
// Enable logging of state during execution
70 351 julius 
//
71 397 julius 
//`define OR1200_MONITOR_EXEC_STATE
72 
 
73 
//
74 
// Enable disassembly of instructions in execution state log
75 
//
76 449 julius 
//`define OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
77 351 julius 
 
78 449 julius 
//
79 
// Enable monitoring of control and execution flow (experimental)
80 
//
81 
//`define OR1200_SYSTEM_CHECKER
82 
 
83 397 julius 
// Can either individually enable things above, or usually have the scripts
84 
// running the simulation pass the PROCESSOR_MONITOR_ENABLE_LOGS define to
85 
// enable them all.
86 351 julius 
 
87 397 julius 
`ifdef PROCESSOR_MONITOR_ENABLE_LOGS
88 
 `define OR1200_MONITOR_EXEC_STATE
89 
 `define OR1200_MONITOR_SPRS
90 
 `define OR1200_MONITOR_LOOKUP
91 
`endif
92 
 
93 351 julius 
//
94 415 julius 
// Memory coherence checking (double check instruction in fetch stage against
95 
// what is in memory.)
96 
//
97 
//`define MEM_COHERENCE_CHECK
98 
 
99 
//
100 348 julius 
// Top of OR1200 inside test bench
101 
//
102 
`define CPU or1200
103 
`define CPU_cpu or1200_cpu
104 
`define CPU_rf or1200_rf
105 
`define CPU_except or1200_except
106 
`define CPU_ctrl or1200_ctrl
107 
`define CPU_sprs or1200_sprs
108 449 julius 
`define CPU_immu_top or1200_immu_top
109 
`define CPU_immu_tlb or1200_immu_tlb
110 
`define CPU_CORE_CLK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk
111 348 julius 
 
112 449 julius 
 
113 
`define OR1K_OPCODE_POS 31:26
114 
`define OR1K_J_BR_IMM_POS 25:0
115 
`define OR1K_RD_POS 25:21
116 
`define OR1K_RA_POS 20:16
117 
`define OR1K_RB_POS 15:11
118 
`define OR1K_ALU_OP_POS 3:0
119 
 
120 
`define OR1K_SHROT_OP_POS 7:6
121 
`define OR1K_SHROTI_IMM_POS 5:0
122 
`define OR1K_SF_OP 25:21
123 
 
124 
`define OR1K_XSYNC_OP_POS 25:21
125 
 
126 
 
127 6 julius 
module or1200_monitor;
128 
 
129 
   integer fexe;
130 449 julius 
   integer finsn;
131 
 
132 6 julius 
   reg [23:0] ref;
133 397 julius 
`ifdef OR1200_MONITOR_SPRS
134 6 julius 
   integer    fspr;
135 397 julius 
`endif
136 6 julius 
   integer    fgeneral;
137 397 julius 
`ifdef OR1200_MONITOR_LOOKUP
138 6 julius 
   integer    flookup;
139 397 julius 
`endif
140 6 julius 
   integer    r3;
141 
   integer    insns;
142 
 
143 348 julius 
 
144 6 julius 
   //
145 
   // Initialization
146 
   //
147 
   initial begin
148 
      ref = 0;
149 397 julius 
`ifdef OR1200_MONITOR_EXEC_STATE
150 360 julius 
      fexe = $fopen({"../out/",`TEST_NAME_STRING,"-executed.log"});
151 449 julius 
`endif
152 
`ifdef OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
153 
      finsn = fexe;
154 397 julius 
`endif
155 6 julius 
      $timeformat (-9, 2, " ns", 12);
156 397 julius 
`ifdef OR1200_MONITOR_SPRS
157 360 julius 
      fspr = $fopen({"../out/",`TEST_NAME_STRING,"-sprs.log"});
158 397 julius 
`endif
159 360 julius 
      fgeneral = $fopen({"../out/",`TEST_NAME_STRING,"-general.log"});
160 397 julius 
`ifdef OR1200_MONITOR_LOOKUP
161 360 julius 
      flookup = $fopen({"../out/",`TEST_NAME_STRING,"-lookup.log"});
162 397 julius 
`endif
163 6 julius 
      insns = 0;
164 
 
165 
   end
166 
 
167 
   //
168 
   // Get GPR
169 
   //
170 
   task get_gpr;
171 
      input     [4:0]    gpr_no;
172 
      output [31:0]      gpr;
173 
      integer           j;
174 
      begin
175 348 julius 
 
176 449 julius 
`ifdef OR1200_RFRAM_GENERIC
177 6 julius 
         for(j = 0; j < 32; j = j + 1) begin
178 348 julius 
            gpr[j] = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no*32+j];
179 6 julius 
         end
180 348 julius 
 
181 449 julius 
`else
182 348 julius 
         //gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no];
183 
         gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.get_gpr(gpr_no);
184 
 
185 449 julius 
`endif
186 6 julius 
 
187 348 julius 
 
188 
      end
189 
   endtask
190 
 
191 6 julius 
   //
192 
   // Write state of the OR1200 registers into a file
193 
   //
194 
   // Limitation: only a small subset of register file RAMs
195 
   // are supported
196 
   //
197 
   task display_arch_state;
198 
      reg [5:0] i;
199 
      reg [31:0] r;
200 
      integer    j;
201 
      begin
202 397 julius 
`ifdef OR1200_MONITOR_EXEC_STATE
203 6 julius 
         ref = ref + 1;
204 397 julius 
 `ifdef OR1200_MONITOR_LOOKUP
205 6 julius 
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
206 397 julius 
 `endif
207 351 julius 
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h", insns,
208 
                 `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
209 
                 `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
210 449 julius 
 `ifdef OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
211 351 julius 
         $fwrite(fexe,"\t");
212 
         // Decode the instruction, print it out
213 
         or1200_print_op(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
214 
 `endif
215 6 julius 
         for(i = 0; i < 32; i = i + 1) begin
216 
            if (i % 4 == 0)
217 
              $fdisplay(fexe);
218 
            get_gpr(i, r);
219 
            $fwrite(fexe, "GPR%d: %h  ", i, r);
220 
         end
221 
         $fdisplay(fexe);
222 348 julius 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
223 6 julius 
         $fwrite(fexe, "SR   : %h  ", r);
224 348 julius 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
225 6 julius 
         $fwrite(fexe, "EPCR0: %h  ", r);
226 348 julius 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
227 6 julius 
         $fwrite(fexe, "EEAR0: %h  ", r);
228 348 julius 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
229 6 julius 
         $fdisplay(fexe, "ESR0 : %h", r);
230 397 julius 
`endif //  `ifdef OR1200_MONITOR_EXEC_STATE
231 348 julius 
`ifdef OR1200_DISPLAY_EXECUTED
232 
         ref = ref + 1;
233 397 julius 
 `ifdef OR1200_MONITOR_LOOKUP
234 348 julius 
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
235 397 julius 
 `endif
236 348 julius 
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
237 6 julius 
`endif
238 348 julius 
         insns = insns + 1;
239 449 julius 
      end
240 6 julius 
   endtask // display_arch_state
241 
 
242 
   /* Keep a trace buffer of the last lot of instructions and addresses
243 
    * "executed",as read from the writeback stage, and cause a $finish if we hit
244 
    * an instruction that is invalid, such as all zeros.
245 
    * Currently, only breaks on an all zero instruction, but should probably be
246 
    * made to break for anything with an X in it too. And of course ideally this
247 
    * shouldn't be needed - but is handy if someone changes something and stops
248 
    * the test continuing forever.
249 
    */
250 49 julius 
   integer num_nul_inst;
251 
   initial num_nul_inst = 0;
252 449 julius 
 
253 6 julius 
   task monitor_for_crash;
254 348 julius 
`define OR1200_MONITOR_CRASH_TRACE_SIZE 32
255 
      //Trace buffer of 32 instructions
256 
      reg [31:0] insn_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
257 
      //Trace buffer of the addresses of those instructions
258 
      reg [31:0] addr_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
259 449 julius 
      integer    i;
260 6 julius 
 
261 449 julius 
      begin
262 
         if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h00000000)
263 
           num_nul_inst = num_nul_inst + 1;
264 
         else
265 
           num_nul_inst = 0; // Reset it
266 49 julius 
 
267 449 julius 
         if (num_nul_inst == 1000) // Sat a loop a bit too long...
268 
           begin
269 
              $fdisplay(fgeneral, "ERROR - no instruction at PC %h",
270 
                        `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc);
271 
              $fdisplay(fgeneral, "Crash trace: Last %d instructions: ",
272 
                        `OR1200_MONITOR_CRASH_TRACE_SIZE);
273 6 julius 
 
274 449 julius 
              $fdisplay(fgeneral, "PC\t\tINSTR");
275 
              for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
276 
                 $fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);
277 
              end
278 
              #100 $finish;
279 
           end
280 
         else
281 
           begin
282 
              for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
283 
                 insn_trace[i] = insn_trace[i-1];
284 
                 addr_trace[i] = addr_trace[i-1];
285 
              end
286 
              insn_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn;
287 
              addr_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc;
288 
           end
289 
 
290 
      end
291 6 julius 
   endtask // monitor_for_crash
292 348 julius 
 
293 6 julius 
 
294 348 julius 
   //
295 
   // Write state of the OR1200 registers into a file; version for exception
296 
   //
297 
   task display_arch_state_except;
298 
      reg [5:0] i;
299 
      reg [31:0] r;
300 
      integer    j;
301 
      begin
302 397 julius 
`ifdef OR1200_MONITOR_EXEC_STATE
303 348 julius 
         ref = ref + 1;
304 397 julius 
 `ifdef OR1200_MONITOR_LOOKUP
305 348 julius 
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
306 397 julius 
 `endif
307 348 julius 
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h  (exception)", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
308 
         for(i = 0; i < 32; i = i + 1) begin
309 
            if (i % 4 == 0)
310 
              $fdisplay(fexe);
311 
            get_gpr(i, r);
312 
            $fwrite(fexe, "GPR%d: %h  ", i, r);
313 
         end
314 
         $fdisplay(fexe);
315 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
316 
         $fwrite(fexe, "SR   : %h  ", r);
317 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
318 
         $fwrite(fexe, "EPCR0: %h  ", r);
319 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
320 
         $fwrite(fexe, "EEAR0: %h  ", r);
321 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
322 
         $fdisplay(fexe, "ESR0 : %h", r);
323 
         insns = insns + 1;
324 397 julius 
`endif //  `ifdef OR1200_MONITOR_EXEC_STATE
325 348 julius 
`ifdef OR1200_DISPLAY_EXECUTED
326 
         ref = ref + 1;
327 397 julius 
 `ifdef OR1200_MONITOR_LOOKUP
328 348 julius 
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
329 397 julius 
 `endif
330 348 julius 
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h  (exception)", insns,
331 
                 `OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc,
332 
                 `OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
333 
         insns = insns + 1;
334 
`endif
335 
 
336 449 julius 
      end
337 348 julius 
   endtask
338 
 
339 6 julius 
   integer iwb_progress;
340 
   reg [31:0] iwb_progress_addr;
341 
   //
342 
   // WISHBONE bus checker
343 
   //
344 
   always @(posedge `OR1200_TOP.iwb_clk_i)
345 
     if (`OR1200_TOP.iwb_rst_i) begin
346 
        iwb_progress = 0;
347 
        iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
348 
     end
349 
     else begin
350 
        if (`OR1200_TOP.iwb_cyc_o && (iwb_progress != 2)) begin
351 
           iwb_progress = 1;
352 
        end
353 
        if (`OR1200_TOP.iwb_stb_o) begin
354 
           if (iwb_progress >= 1) begin
355 
              if (iwb_progress == 1)
356 
                iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
357 
              iwb_progress = 2;
358 
           end
359 
           else begin
360 
              $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o raised without `OR1200_TOP.iwb_cyc_o, at %t\n", $time);
361 
              #100 $finish;
362 
           end
363 
        end
364 
        if (`OR1200_TOP.iwb_ack_i & `OR1200_TOP.iwb_err_i) begin
365 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i and `OR1200_TOP.iwb_err_i raised at the same time, at %t\n", $time);
366 
        end
367 
        if ((iwb_progress == 2) && (iwb_progress_addr != `OR1200_TOP.iwb_adr_o)) begin
368 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_adr_o changed while waiting for `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
369 
           #100 $finish;
370 
        end
371 
        if (`OR1200_TOP.iwb_ack_i | `OR1200_TOP.iwb_err_i)
372 
          if (iwb_progress == 2) begin
373 
             iwb_progress = 0;
374 
             iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
375 
          end
376 
          else begin
377 
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
378 
             #100 $finish;
379 
          end
380 
        if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
381 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
382 348 julius 
           #100 $finish;
383 6 julius 
        end
384 
     end
385 
 
386 
   integer dwb_progress;
387 449 julius 
   reg [31:0] dwb_progress_addr;
388 
   //
389 
   // WISHBONE bus checker
390 
   //
391 
   always @(posedge `OR1200_TOP.dwb_clk_i)
392 
     if (`OR1200_TOP.dwb_rst_i)
393 
       dwb_progress = 0;
394 
     else begin
395 
        if (`OR1200_TOP.dwb_cyc_o && (dwb_progress != 2))
396 
          dwb_progress = 1;
397 
        if (`OR1200_TOP.dwb_stb_o)
398 
          if (dwb_progress >= 1) begin
399 
             if (dwb_progress == 1)
400 
               dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
401 
             dwb_progress = 2;
402 
          end
403 
          else begin
404 
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o raised without `OR1200_TOP.dwb_cyc_o, at %t\n", $time);
405 
             #100 $finish;
406 
          end
407 
        if (`OR1200_TOP.dwb_ack_i & `OR1200_TOP.dwb_err_i) begin
408 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i and `OR1200_TOP.dwb_err_i raised at the same time, at %t\n", $time);
409 
        end
410 
        if ((dwb_progress == 2) && (dwb_progress_addr != `OR1200_TOP.dwb_adr_o)) begin
411 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_adr_o changed while waiting for `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
412 
           #100 $finish;
413 
        end
414 
        if (`OR1200_TOP.dwb_ack_i | `OR1200_TOP.dwb_err_i)
415 
          if (dwb_progress == 2) begin
416 
             dwb_progress = 0;
417 
             dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
418 
          end
419 
          else begin
420 
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i/`OR1200_TOP.dwb_err_i raised without `OR1200_TOP.dwb_cyc_i/`OR1200_TOP.dwb_stb_i, at %t\n", $time);
421 
             #100 $finish;
422 
          end
423 
        if ((dwb_progress == 2) && !`OR1200_TOP.dwb_stb_o) begin
424 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o lowered without `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
425 
           #100 $finish;
426 
        end
427 6 julius 
     end
428 
 
429 449 julius 
   //
430 
   // Hooks for:
431 
   // - displaying registers
432 
   // - end of simulation
433 
   // - access to SPRs
434 
   //
435 
   always @(posedge `CPU_CORE_CLK)
436 348 julius 
     if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze) begin
437 449 julius 
        //      #2;
438 348 julius 
        if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP)
439 
             | !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
440 
            & !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &
441 
                `OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot))
442 6 julius 
          begin
443 
             display_arch_state;
444 
             monitor_for_crash;
445 
          end
446 
        else
447 348 julius 
          if (`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe)
448 6 julius 
            display_arch_state_except;
449 348 julius 
        // small hack to stop simulation (l.nop 1):
450 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
451 6 julius 
           get_gpr(3, r3);
452 
           $fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
453 
           $finish;
454 
        end
455 348 julius 
        // debug if test (l.nop 10)
456 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
457 6 julius 
           $fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
458 
        end
459 348 julius 
        // simulation reports (l.nop 2)
460 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
461 6 julius 
           get_gpr(3, r3);
462 348 julius 
           $fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
463 
        end
464 
        // simulation printfs (l.nop 3)
465 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0003) begin
466 
           get_gpr(3, r3);
467 6 julius 
           $fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);
468 
        end
469 348 julius 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0004) begin
470 
           // simulation putc (l.nop 4)
471 
           get_gpr(3, r3);
472 
           $write("%c", r3);
473 
           $fdisplay(fgeneral, "%t: l.nop putc (%c)", $time, r3);
474 
        end
475 397 julius 
`ifdef OR1200_MONITOR_SPRS
476 
        if (`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
477 6 julius 
          $fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
478 397 julius 
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
479 348 julius 
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_dat_o);
480 397 julius 
        if ((|`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_cs) &
481 
            !`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
482 6 julius 
          $fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
483 348 julius 
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
484 
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.to_wbmux);
485 397 julius 
`endif
486 6 julius 
     end
487 
 
488 348 julius 
 
489 415 julius 
`ifdef RAM_WB
490 439 julius 
 `define RAM_WB_TOP `DUT_TOP.ram_wb0.ram_wb_b3_0
491 415 julius 
   task get_insn_from_wb_ram;
492 
      input [31:0] addr;
493 
      output [31:0] insn;
494 
      begin
495 439 julius 
         insn = `RAM_WB_TOP.get_mem(addr);
496 415 julius 
      end
497 
   endtask // get_insn_from_wb_ram
498 
`endif
499 
 
500 348 julius 
`ifdef VERSATILE_SDRAM
501 415 julius 
 `define SDRAM_TOP `TB_TOP.sdram0
502 348 julius 
   // Bit selects to define the bank
503 
   // 32 MB part with 4 banks
504 
 `define SDRAM_BANK_SEL_BITS 24:23
505 
 `define SDRAM_WORD_SEL_TOP_BIT 22
506 
   // Gets instruction word from correct bank
507 
   task get_insn_from_sdram;
508 
      input [31:0] addr;
509 
      output [31:0] insn;
510 
      reg [`SDRAM_WORD_SEL_TOP_BIT-1:0] word_addr;
511 449 julius 
 
512 348 julius 
      begin
513 
         word_addr = addr[`SDRAM_WORD_SEL_TOP_BIT:2];
514 
         if (addr[`SDRAM_BANK_SEL_BITS] == 2'b00)
515 
           begin
516 
 
517 
              //$display("%t: get_insn_from_sdram bank0, word 0x%h, (%h and %h in SDRAM)", $time, word_addr, `SDRAM_TOP.Bank0[{word_addr,1'b0}], `SDRAM_TOP.Bank0[{word_addr,1'b1}]);
518 
              insn[15:0] = `SDRAM_TOP.Bank0[{word_addr,1'b1}];
519 
              insn[31:16] = `SDRAM_TOP.Bank0[{word_addr,1'b0}];
520 
           end
521 
      end
522 
 
523 
   endtask // get_insn_from_sdram
524 
`endif //  `ifdef VERSATILE_SDRAM
525 
 
526 
`ifdef XILINX_DDR2
527 415 julius 
 `define DDR2_TOP `TB_TOP.gen_cs[0]
528 348 julius 
   // Gets instruction word from correct bank
529 
   task get_insn_from_xilinx_ddr2;
530 
      input [31:0] addr;
531 
      output [31:0] insn;
532 415 julius 
      reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2,
533 
                     ddr2_array_line3;
534 348 julius 
      integer        word_in_line_num;
535 
      begin
536 449 julius 
         // Get our 4 128-bit chunks (8 half-words in each!! Confused yet?),
537 
         // 16 words total
538 348 julius 
         `DDR2_TOP.gen[0].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line0);
539 
         `DDR2_TOP.gen[1].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line1);
540 
         `DDR2_TOP.gen[2].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line2);
541 
         `DDR2_TOP.gen[3].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line3);
542 
         case (addr[5:2])
543 
           4'h0:
544 
             begin
545 
                insn[15:0] = ddr2_array_line0[15:0];
546 
                insn[31:16] = ddr2_array_line1[15:0];
547 
             end
548 
           4'h1:
549 
             begin
550 
                insn[15:0] = ddr2_array_line2[15:0];
551 
                insn[31:16] = ddr2_array_line3[15:0];
552 
             end
553 
           4'h2:
554 
             begin
555 
                insn[15:0] = ddr2_array_line0[31:16];
556 
                insn[31:16] = ddr2_array_line1[31:16];
557 
             end
558 
           4'h3:
559 
             begin
560 
                insn[15:0] = ddr2_array_line2[31:16];
561 
                insn[31:16] = ddr2_array_line3[31:16];
562 
             end
563 
           4'h4:
564 
             begin
565 
                insn[15:0] = ddr2_array_line0[47:32];
566 
                insn[31:16] = ddr2_array_line1[47:32];
567 
             end
568 
           4'h5:
569 
             begin
570 
                insn[15:0] = ddr2_array_line2[47:32];
571 
                insn[31:16] = ddr2_array_line3[47:32];
572 
             end
573 
           4'h6:
574 
             begin
575 
                insn[15:0] = ddr2_array_line0[63:48];
576 
                insn[31:16] = ddr2_array_line1[63:48];
577 
             end
578 
           4'h7:
579 
             begin
580 
                insn[15:0] = ddr2_array_line2[63:48];
581 
                insn[31:16] = ddr2_array_line3[63:48];
582 
             end
583 
           4'h8:
584 
             begin
585 
                insn[15:0] = ddr2_array_line0[79:64];
586 
                insn[31:16] = ddr2_array_line1[79:64];
587 
             end
588 
           4'h9:
589 
             begin
590 
                insn[15:0] = ddr2_array_line2[79:64];
591 
                insn[31:16] = ddr2_array_line3[79:64];
592 
             end
593 
           4'ha:
594 
             begin
595 
                insn[15:0] = ddr2_array_line0[95:80];
596 
                insn[31:16] = ddr2_array_line1[95:80];
597 
             end
598 
           4'hb:
599 
             begin
600 
                insn[15:0] = ddr2_array_line2[95:80];
601 
                insn[31:16] = ddr2_array_line3[95:80];
602 
             end
603 
           4'hc:
604 
             begin
605 
                insn[15:0] = ddr2_array_line0[111:96];
606 
                insn[31:16] = ddr2_array_line1[111:96];
607 
             end
608 
           4'hd:
609 
             begin
610 
                insn[15:0] = ddr2_array_line2[111:96];
611 
                insn[31:16] = ddr2_array_line3[111:96];
612 
             end
613 
           4'he:
614 
             begin
615 
                insn[15:0] = ddr2_array_line0[127:112];
616 
                insn[31:16] = ddr2_array_line1[127:112];
617 
             end
618 
           4'hf:
619 
             begin
620 
                insn[15:0] = ddr2_array_line2[127:112];
621 
                insn[31:16] = ddr2_array_line3[127:112];
622 
             end
623 
         endcase // case (addr[5:2])
624 
      end
625 
   endtask // get_insn_from_xilinx_ddr2
626 
`endif
627 
 
628 
 
629 
   task get_insn_from_memory;
630 
      input [31:0] id_pc;
631 
      output [31:0] insn;
632 
      begin
633 
         // do a decode of which server we should look in
634 
         case (id_pc[31:28])
635 
`ifdef VERSATILE_SDRAM
636 
           4'h0:
637 
             get_insn_from_sdram(id_pc, insn);
638 
`endif
639 
`ifdef XILINX_DDR2
640 
           4'h0:
641 
             get_insn_from_xilinx_ddr2(id_pc, insn);
642 415 julius 
`endif
643 
`ifdef RAM_WB
644 
           4'h0:
645 
             get_insn_from_wb_ram(id_pc, insn);
646 
`endif
647 348 julius 
           4'hf:
648 
             // Flash isn't stored in a memory, it's an FSM so just skip/ignore
649 
             insn = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn;
650 
           default:
651 
             begin
652 
                $fdisplay(fgeneral, "%t: Unknown memory server for address 0x%h", $time,id_pc);
653 
                insn = 32'hxxxxxxxx; // Unknown server
654 
             end
655 
         endcase // case (id_pc[31:28])
656 
      end
657 
   endtask // get_insn_from_memory
658 
 
659 
 
660 449 julius 
   //
661 
   // Look in the iMMU TLB MR for this address' page, if MMUs are on and enabled
662 
   //
663 
   task check_for_immu_entry;
664 
      input [31:0] pc;
665 
      output [31:0] physical_pc;
666 
      output        mmu_tlb_miss;
667 
      integer       w,x;
668 
 
669 
      reg [31:`OR1200_IMMU_PS] pc_vpn;
670 
 
671 
      reg [`OR1200_ITLBTRW-1:0] itlb_tr;
672 
      reg [`OR1200_ITLBMRW-1:0] itlb_mr;
673 
 
674 
      integer                   tlb_index;
675 
      reg                       mmu_en;
676 
 
677 
 
678 
      begin
679 
         mmu_tlb_miss = 0;
680 
 
681 
`ifdef OR1200_NO_IMMU
682 
         physical_pc = pc;
683 
`else
684 
         mmu_en = `OR1200_TOP.`CPU_immu_top.immu_en;
685 
         // If MMU is enabled
686 
         if (mmu_en)
687 
           begin
688 
 
689 
              // Look in the iTLB for mapping - get virtual page number
690 
              pc_vpn = pc[31:`OR1200_IMMU_PS];
691 
 
692 
              tlb_index = pc[`OR1200_ITLB_INDX];
693 
 
694 
              // Look at the ITLB match register
695 
              itlb_mr = `OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_mr_ram.mem[tlb_index];
696 
 
697 
              // Get the translate register here too, in case there's an error, we print it
698 
              itlb_tr = `OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_tr_ram.mem[tlb_index];
699 
 
700 
              if ((itlb_mr[`OR1200_ITLBMR_V_BITS] === 1'b1) & (itlb_mr[`OR1200_ITLBMRW-1:1] === pc[`OR1200_ITLB_TAG]))
701 
                begin
702 
                   // Page number in match register matches page number of virtual PC, so get the physical
703 
                   // address from the translate memory
704 
                   // Now pull the physical page number out of the tranlsate register (it's after bottom 3 bits)
705 
                   physical_pc = {itlb_tr[`OR1200_ITLBTRW-1:`OR1200_ITLBTRW-(32-`OR1200_IMMU_PS)],pc[`OR1200_IMMU_PS-1:0]};
706 
                   //$display("check_for_immu_entry: found match for virtual PC 0x%h in entry %d of iMMU, mr = 0x%x tr = 0x%x, phys. PC = 0x%h", pc, pc[`OR1200_ITLB_INDX], itlb_mr, itlb_tr, physical_pc);
707 
                end // if ((itlb_mr[`OR1200_ITLBMR_V_BITS]) & (itlb_mr[`OR1200_ITLBMRW-1:1] == pc[`OR1200_ITLB_TAG]))
708 
              else
709 
                begin
710 
 
711 
                   // Wait a couple of clocks, see if we're doing a miss
712 
                   @(posedge `CPU_CORE_CLK);
713 
                   @(posedge `CPU_CORE_CLK);
714 
                   if (!(`OR1200_TOP.`CPU_immu_top.miss)) // MMU should indicate miss
715 
                     begin
716 
                        $display("%t: check_for_immu_entry - ERROR - no match found for virtual PC 0x%h in entry %d of iMMU, mr = 0x%x tr = 0x%x, and no miss generated",
717 
                                 $time, pc, pc[`OR1200_ITLB_INDX], itlb_mr, itlb_tr);
718 
                        #100;
719 
                        $finish;
720 
                     end
721 
                   else
722 
                     begin
723 
                        mmu_tlb_miss = 1; // Started a miss, so ignore this instruction
724 
                     end
725 
                end // else: !if((itlb_mr[`OR1200_ITLBMR_V_BITS]) & (itlb_mr[`OR1200_ITLBMRW-1:1] == pc[`OR1200_ITLB_TAG]))
726 
 
727 
           end // if (`OR1200_TOP.`CPU_immu_top.immu_en === 1'b1)
728 
         else
729 
           physical_pc = pc;
730 
`endif // !`ifdef OR1200_NO_IMMU
731 
      end
732 
   endtask // check_for_immu_entry
733 
 
734 
 
735 
   /*
736 
    Instruction memory coherence checking.
737 
 
738 
    For new instruction executed in the pipeline - ensure it matches
739 
    what is in the main program memory. Perform MMU translations if
740 
    it is enabled.
741 
    */
742 
 
743 
   reg [31:0] mem_word;
744 348 julius 
   reg [31:0] last_addr = 0;
745 
   reg [31:0] last_mem_word;
746 449 julius 
   reg [31:0] physical_pc;
747 
   reg        tlb_miss;
748 
 
749 348 julius 
 
750 415 julius 
`ifdef MEM_COHERENCE_CHECK
751 
 `define MEM_COHERENCE_TRIGGER (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_void === 1'b0)
752 
 
753 449 julius 
 `define INSN_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn
754 
 `define PC_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_except.id_pc
755 348 julius 
 
756 
   // Check instruction in decode stage is what is in the RAM
757 449 julius 
   always @(posedge `CPU_CORE_CLK)
758 348 julius 
     begin
759 415 julius 
        if (`MEM_COHERENCE_TRIGGER)
760 348 julius 
          begin
761 449 julius 
 
762 
             check_for_immu_entry(`PC_TO_CHECK, physical_pc, tlb_miss);
763 
 
764 348 julius 
             // Check if it's a new PC - will also get triggered if the
765 
             // instruction has changed since we last checked it
766 449 julius 
             if (((physical_pc !== last_addr) || (last_mem_word != `INSN_TO_CHECK))
767 
                 & !tlb_miss)
768 348 julius 
               begin
769 
                  // Decode stage not void, check instruction
770 
                  // get PC
771 449 julius 
                  get_insn_from_memory(physical_pc, mem_word);
772 348 julius 
 
773 
                  if (mem_word !== `INSN_TO_CHECK)
774 
                    begin
775 449 julius 
                       $fdisplay(fgeneral, "%t: Instruction mismatch for PC 0x%h (phys. 0x%h) - memory had 0x%h, CPU had 0x%h", $time, `PC_TO_CHECK, physical_pc, mem_word, `INSN_TO_CHECK);
776 
                       $display("%t: Instruction mismatch for PC 0x%h (phys. 0x%h) - memory had 0x%h, CPU had 0x%h", $time, `PC_TO_CHECK, physical_pc, mem_word, `INSN_TO_CHECK);
777 
                       #200
778 348 julius 
                         $finish;
779 
                    end
780 449 julius 
                  last_addr = physical_pc;
781 
                  last_mem_word = mem_word;
782 
 
783 
               end // if (((physical_pc !== last_addr) || (last_mem_word != `INSN_TO_CHECK))...
784 
          end // if (`MEM_COHERENCE_TRIGGER)
785 
     end // always @ (posedge `CPU_CORE_CLK)
786 
 
787 
`endif //  `ifdef MEM_COHERENCE_CHECK
788 
 
789 
   // Trigger on each instruction that gets into writeback stage properly
790 
   reg exception_coming1, exception_coming2, exception_here;
791 
   reg will_jump, jumping, jump_dslot, jumped;
792 
   reg rfe, except_during_rfe;
793 
   reg dslot_expt;
794 
 
795 
 
796 
   // Maintain a copy of GPRS for previous instruction
797 
   reg [31:0] current_gprs [0:31];
798 
   reg [31:0] current_epcr, current_eear, current_esr, current_sr;
799 
   reg [31:0] previous_gprs [0:31];
800 
   reg [31:0] previous_epcr;
801 
   reg [31:0] previous_eear;
802 
   reg [31:0] previous_esr;
803 
   reg [31:0] previous_sr;
804 
 
805 
   task update_current_gprs;
806 
      integer j;
807 
      begin
808 
         for(j=0;j<32;j=j+1)
809 
           begin
810 
              get_gpr(j,current_gprs[j]);
811 
           end
812 
         current_sr = `OR1200_TOP.`CPU_cpu.or1200_sprs.sr ;
813 
         current_esr = `OR1200_TOP.`CPU_cpu.or1200_sprs.epcr ;
814 
         current_epcr = `OR1200_TOP.`CPU_cpu.or1200_sprs.epcr ;
815 
         current_eear = `OR1200_TOP.`CPU_cpu.or1200_sprs.eear ;
816 
      end
817 
   endtask
818 
 
819 
   task update_previous_gprs;
820 
      integer j;
821 
      begin
822 
         for(j=0;j<32;j=j+1)
823 
           begin
824 
              previous_gprs[j] = current_gprs[j];
825 
           end
826 
         previous_sr = current_sr;
827 
         previous_esr = current_esr;
828 
         previous_epcr = current_epcr;
829 
         previous_eear = current_eear;
830 
      end
831 
   endtask // update_previous_gprs
832 
 
833 
   // Maintain a list of addresses we expect the processor to execute
834 
   // Whenever we hit a branch or jump or rfe we add to this list - when we
835 
   // execute it then we remove it from the list.
836 
   reg [31:0] expected_addresses [0:31];
837 
   reg        expected_addresses_waiting [0:31]; // List indicating if address is waiting
838 
   reg        duplicate_expected_addresses_waiting [0:31]; // List indicating if a waiting address will be cleared by the single return
839 
   integer    expected_address_num;
840 
   // Initialise things on reset
841 
   always @(`OR1200_TOP.iwb_rst_i)
842 
     begin
843 
        for (expected_address_num=0;expected_address_num<32;expected_address_num=expected_address_num+1)
844 
          begin
845 
             expected_addresses_waiting[expected_address_num] = 0;
846 
             duplicate_expected_addresses_waiting[expected_address_num] = 0;
847 348 julius 
          end
848 449 julius 
        expected_address_num = 0;
849 
     end
850 
 
851 
   task add_expected_address;
852 
      input [31:0] expected_pc;
853 
      begin
854 
         if (expected_address_num == 31)
855 
           begin
856 
              $display("%t: Too many branches not reached",$time);
857 
              #100;
858 
              $finish;
859 
           end
860 
         if (expected_addresses_waiting[expected_address_num])
861 
           begin
862 
              $display("%t: expected_addresses tracker bugged out. expected_address_num = %0d",$time,expected_address_num);
863 
              #100;
864 
              $finish;
865 
           end
866 
         else
867 
           begin
868 
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
869 
              // Debugging output...
870 
              $display("%t: Adding address 0x%h to expected list index %0d",$time, expected_pc,expected_address_num);
871 
`endif
872 
              // Put the expected PC in the list, increase the index
873 
              expected_addresses[expected_address_num] = expected_pc;
874 
              expected_addresses_waiting[expected_address_num] = 1;
875 
              expected_address_num = expected_address_num + 1;
876 
           end // else: !if(expected_addresses_waiting[expected_address_num])
877 
      end
878 
   endtask // add_address_to_expect
879 
 
880 
   // Use this in the case that there's an execption after a jump, in which
881 
   // case we'll have two entries when we finally jump back (the one the
882 
   // original jump put in, and the one put in by the l.rfe or l.jr/ when
883 
   // returning outside of exception handler), so mark this one as OK for
884 
   // removing the duplicate of
885 
   task mark_duplicate_expected_address;
886 
      begin
887 
         // This will always be done on the first instruction of an exception
888 
         // that has occured after a delay slot instruction, so
889 
         // expected_address_num will be one past the entry for the one we will
890 
         // get a duplicate return call for
891 
         duplicate_expected_addresses_waiting[expected_address_num-1] = 1;
892 
      end
893 
   endtask // mark_duplicate_expected_address
894 
 
895 
 
896 
   task check_expected_address;
897 
      input [31:0] pc;
898 
      input        expecting_hit;
899 
      integer      i,j;
900 
      reg          hit;
901 
      reg          duplicates;
902 348 julius 
 
903 449 julius 
      begin
904 
         hit = 0;
905 
         //$display("%t: check_expected_addr 0x%h, index %0d",
906 
         // $time,pc, expected_address_num);
907 
         if (expected_address_num > 0)
908 
           begin
909 
              // First check the last jump we did
910 
              if (expected_addresses[expected_address_num-1] == pc)
911 
                begin
912 
                   // Jump address hit
913 
                   // Debugging printout:
914 
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
915 
                   $display("%t: PC address 0x%h was in expected list, index %0d",$time, pc,expected_address_num-1);
916 
`endif
917 
                   expected_address_num = expected_address_num-1;
918 
                   expected_addresses_waiting[expected_address_num] = 0;
919 
                   hit = 1;
920 
                end
921 
              else
922 
                begin
923 
                   // Check through the list
924 
                   for(i=0;i<expected_address_num;i=i+1)
925 
                     begin
926 
                        if (expected_addresses[i] == pc)
927 
                          begin
928 
                             // Jump address hit
929 
                             // Debugging printout:
930 
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
931 
                             $display("%t: PC address 0x%h was in expected list, index %0d",$time, pc,i);
932 
`endif
933 
                             for(j=i;j<expected_address_num;j=j+1)
934 
                               begin
935 
                                  // Pull all of the ones above us down one
936 
                                  expected_addresses_waiting[j]
937 
                                    = expected_addresses_waiting[j+1];
938 
                                  expected_addresses[j]
939 
                                    = expected_addresses[j+1];
940 
                                  duplicate_expected_addresses_waiting[j]
941 
                                    = duplicate_expected_addresses_waiting[j+1];
942 
                               end
943 
                             expected_address_num = expected_address_num-1;
944 
                             hit = 1;
945 
                             // quit out. only allow 1 hit
946 
                             i = expected_address_num;
947 
                          end
948 
                     end
949 
                end // else: !if(expected_addresses[expected_ad...
950 
           end // if (expected_address_num > 0)
951 348 julius 
 
952 449 julius 
         // Check for duplicates this way because of the way we've declared
953 
         // the array...
954 
         duplicates=0;
955 
         for(i=0;i<32;i=i+1)
956 
           duplicates = duplicates | duplicate_expected_addresses_waiting[i];
957 
 
958 
         if (hit & duplicates)
959 
           begin
960 
              // If we got a hit, check for duplicates we're also meant to clear
961 
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
962 
              $display;
963 
`endif
964 
              for(i=0;i<expected_address_num;i=i+1)
965 
                begin
966 
                   if(duplicate_expected_addresses_waiting[i] &
967 
                      expected_addresses_waiting[i] &
968 
                      expected_addresses[i] == pc)
969 
                     begin
970 
                        // Found a duplicate call address, clear it
971 
                        duplicate_expected_addresses_waiting[i] = 0;
972 
                        expected_addresses_waiting[i] = 0;
973 
 
974 
                        // Now reorder the list - pull all the ones above us
975 
                        // down by one
976 
                        for(j=i;j<expected_address_num;j=j+1)
977 
                          begin
978 
                             expected_addresses_waiting[j] = expected_addresses_waiting[j+1];
979 
                             expected_addresses[j] = expected_addresses[j+1];
980 
                             duplicate_expected_addresses_waiting[j] = duplicate_expected_addresses_waiting[j+1];
981 
                          end
982 
                        expected_address_num = expected_address_num - 1;
983 
                     end
984 
                end // for (i=0;i<expected_address_num;i=i+1)
985 
           end // if (hit & duplicates)
986 
 
987 
         if (expecting_hit & !hit)
988 
           begin
989 
              // Expected this address to be one we're supposed to jump to, but it wasn't!
990 
              $display("%t: Failed to find current PC, 0x%h, in expected PCs for branches/jumps",$time,pc);
991 
              #100;
992 
              $finish;
993 
           end
994 
 
995 
      end
996 
   endtask // check_expected_address
997 
 
998 
   // Task to assert value of GPR
999 
   task assert_gpr_val;
1000 
      input [5:0] regnum;
1001 
      input [31:0] assert_value;
1002 
      input [31:0] pc;
1003 
      reg [31:0]   reg_val;
1004 
 
1005 
      begin
1006 
         get_gpr(regnum, reg_val);
1007 
         if (reg_val !== assert_value)
1008 
           begin
1009 
              $display("%t: Assert r%0d value (0x%h) = 0x%h failed. pc=0x%h",
1010 
                       $time, regnum, reg_val, assert_value,pc);
1011 
              #100;
1012 
              $finish;
1013 
           end
1014 
      end
1015 
   endtask // assert_gpr_val
1016 
 
1017 
   // Task to assert something is true
1018 
   task assert_this;
1019 
      input assert_result;
1020 
      input [31:0] pc;
1021 
      begin
1022 
         if (!assert_result)
1023 
           begin
1024 
              $display("%t: Assert failed for instruction at pc=0x%h",
1025 
                       $time , pc);
1026 
              #100;
1027 
              $finish;
1028 
           end
1029 
      end
1030 
   endtask // assert_gpr_val
1031 
 
1032 
   // The jumping variable doesn't get updated until we do the proper check of
1033 
   // the current instruction reaching the writeback stage. We need to know
1034 
   // earlier, eg. in the exception checking part, if this instruction will
1035 
   // jump. We do that with this task.
1036 
   task check_for_jump;
1037 
      input [31:0] insn;
1038 
      reg [5:0]    opcode;
1039 
      reg          flag;
1040 
      begin
1041 
         opcode = insn[`OR1K_OPCODE_POS];
1042 
         // Use the flag from the previous instruction, as the decision
1043 
         // is made in the execute stage not in te writeback stage,
1044 
         // which is where we're getting our instructions.
1045 
         flag = previous_sr[`OR1200_SR_F];
1046 
 
1047 
         case (opcode)
1048 
           `OR1200_OR32_J,
1049 
             `OR1200_OR32_JR,
1050 
             `OR1200_OR32_JAL,
1051 
             `OR1200_OR32_JALR:
1052 
               will_jump = 1;
1053 
           `OR1200_OR32_BNF:
1054 
             will_jump = !flag;
1055 
           `OR1200_OR32_BF:
1056 
             will_jump = flag;
1057 
           default:
1058 
             will_jump = 0;
1059 
         endcase // case (opcode)
1060 
      end
1061 
   endtask // check_for_jump
1062 
 
1063 
 
1064 
 
1065 
   // Detect exceptions from the processor here
1066 
   reg [13:0] except_trig_r;
1067 
   reg        exception_coming;
1068 
 
1069 
   always @(posedge `CPU_CORE_CLK)
1070 
     if (`OR1200_TOP.iwb_rst_i)
1071 
       begin
1072 
          except_trig_r = 0;
1073 
          exception_coming = 0;
1074 
          except_during_rfe = 0;
1075 
       end
1076 
     else if ((|`OR1200_TOP.`CPU_cpu.`CPU_except.except_trig) && !exception_coming)
1077 
       begin
1078 
          exception_coming  = 1;
1079 
          except_trig_r = `OR1200_TOP.`CPU_cpu.`CPU_except.except_trig;
1080 
          except_during_rfe = rfe;
1081 
       end
1082 
 
1083 
   task check_incoming_exceptions;
1084 
      begin
1085 
 
1086 
         // Exception timing  - depends on the trigger.
1087 
         // Appears to be:
1088 
         // tick timer - dslot - 1 instruction delay, else 2
1089 
         // tlb lookasides - 1 instruction for both
1090 
 
1091 
         casex (except_trig_r)
1092 
           13'b1_xxxx_xxxx_xxxx: begin
1093 
              //except_type <= #1 `OR1200_EXCEPT_TICK;
1094 
              exception_here = exception_coming2;
1095 
              exception_coming2 = jump_dslot ? exception_coming: exception_coming1 ;
1096 
              exception_coming1 = jump_dslot ? 0 : exception_coming;
1097 
           end
1098 
           13'b0_1xxx_xxxx_xxxx: begin
1099 
              //except_type <= #1 `OR1200_EXCEPT_INT;
1100 
              #1;
1101 
           end
1102 
           13'b0_01xx_xxxx_xxxx: begin
1103 
              //except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
1104 
              exception_here = exception_coming2;
1105 
              exception_coming2 = jump_dslot ? exception_coming : exception_coming1 ;
1106 
              exception_coming1 = jump_dslot ? 0 : exception_coming;
1107 
           end
1108 
           13'b0_001x_xxxx_xxxx: begin
1109 
              //except_type <= #1 `OR1200_EXCEPT_IPF;
1110 
              exception_here = exception_coming2;
1111 
              exception_coming2 = jump_dslot ? exception_coming : exception_coming1 ;
1112 
              exception_coming1 = jump_dslot ? 0 : exception_coming;
1113 
           end
1114 
           13'b0_0001_xxxx_xxxx: begin
1115 
              //except_type <= #1 `OR1200_EXCEPT_BUSERR;
1116 
              exception_here = exception_coming;
1117 
              exception_coming2 = 0;
1118 
              exception_coming1 = 0;
1119 
           end
1120 
           13'b0_0000_1xxx_xxxx: begin
1121 
              //except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
1122 
              if (will_jump)
1123 
                begin
1124 
                   // Writeback stage instruction will jump, and we have an
1125 
                   // illegal instruction in the decode/execute stage, which is
1126 
                   // the delay slot, so indicate the exception is coming...
1127 
                   exception_here = exception_coming2;
1128 
                   exception_coming2 = exception_coming;
1129 
                   exception_coming1 = 0;
1130 
                end
1131 
              else
1132 
                begin
1133 
                   exception_here = jump_dslot ?
1134 
                                    exception_coming2 : exception_coming;
1135 
                   exception_coming2 = jump_dslot ? exception_coming : 0;
1136 
                   exception_coming1 = 0;
1137 
                end
1138 
           end
1139 
           13'b0_0000_01xx_xxxx: begin
1140 
              //except_type <= #1 `OR1200_EXCEPT_ALIGN;
1141 
              if(will_jump)
1142 
                begin
1143 
                   exception_here = exception_coming2;
1144 
                   exception_coming2 = exception_coming;
1145 
                   exception_coming1 = 0;
1146 
                end
1147 
              else
1148 
                begin
1149 
                   exception_here =  (rfe) ? exception_coming : exception_coming2;
1150 
                   exception_coming2 = (rfe) ? 0 : exception_coming;
1151 
                   exception_coming1 = 0;
1152 
                end
1153 
           end
1154 
           13'b0_0000_001x_xxxx: begin
1155 
              //except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
1156 
              // Looks like except_trig goes high here after we check the
1157 
              // instruction before the itlb miss after a delay slot, so we
1158 
              // miss the dslot variable (it gets propegated before we call
1159 
              // this task) so we use the jumped variable here to see if we
1160 
              // are an exception after a delay slot
1161 
              //exception_here = (jumped | rfe) ? exception_coming : exception_coming2 ;
1162 
              //exception_coming2 = (jumped | rfe) ? 0 : exception_coming;
1163 
 
1164 
              exception_here = (jumped | rfe) ? exception_coming : exception_coming2 ;
1165 
              exception_coming2 = (jumped | rfe) ? 0 : exception_coming;
1166 
 
1167 
              exception_coming1 = 0;
1168 
           end
1169 
           13'b0_0000_0001_xxxx: begin
1170 
              //except_type <= #1 `OR1200_EXCEPT_DPF;
1171 
              if (jumped) begin // Jumped onto illegal instruction
1172 
                 exception_here = exception_coming ;
1173 
                 exception_coming2 = 0;
1174 
                 exception_coming1 = 0;
1175 
              end
1176 
              else begin
1177 
                 exception_here =  exception_coming2;
1178 
                 exception_coming2 = exception_coming;
1179 
                 exception_coming1 = 0;
1180 
              end
1181 
           end
1182 
           13'b0_0000_0000_1xxx: begin  // Data Bus Error
1183 
              //except_type <= #1 `OR1200_EXCEPT_BUSERR;
1184 
              exception_here = exception_coming2 ;
1185 
              exception_coming2 = exception_coming;
1186 
              exception_coming1 = 0;
1187 
           end
1188 
           13'b0_0000_0000_01xx: begin
1189 
              //except_type <= #1 `OR1200_EXCEPT_RANGE;
1190 
              #1;
1191 
           end
1192 
           13'b0_0000_0000_001x: begin
1193 
              // trap
1194 
              #1;
1195 
           end
1196 
           13'b0_0000_0000_0001: begin
1197 
              //except_type <= #1 `OR1200_EXCEPT_SYSCALL;
1198 
              exception_here = exception_coming2;
1199 
              exception_coming2 = jumped ? exception_coming: exception_coming1 ;
1200 
              exception_coming1 = jumped ? 0 : exception_coming;
1201 
           end
1202 
         endcase // casex (except_trig_r)
1203 
 
1204 
         exception_coming = 0;
1205 
         except_during_rfe = 0;
1206 
 
1207 
      end
1208 
   endtask // check_incoming_exceptions
1209 
 
1210 
 
1211 
 
1212 
 
1213 351 julius 
   /////////////////////////////////////////////////////////////////////////
1214 449 julius 
   // Execution tracking task
1215 351 julius 
   /////////////////////////////////////////////////////////////////////////
1216 348 julius 
 
1217 449 julius 
 
1218 
`ifdef OR1200_SYSTEM_CHECKER
1219 
   always @(posedge `CPU_CORE_CLK)
1220 
     begin
1221 
        if (`OR1200_TOP.iwb_rst_i)
1222 
          begin
1223 
             exception_coming1 = 0;exception_coming2 = 0;exception_here= 0;
1224 
             jumping = 0; jump_dslot = 0; jumped = 0;
1225 
             rfe = 0;
1226 
          end
1227 
        if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze) begin
1228 
           //#2 ;
1229 
           // If instruction isn't a l.nop with bit 16 set (implementation's
1230 
           // filler instruction in pipeline), and do not have an exception
1231 
           // signaled with a dslot instruction in the execute stage
1232 
           if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[`OR1K_OPCODE_POS] !=
1233 
                 `OR1200_OR32_NOP) || !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
1234 
               && !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &&
1235 
                    `OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot)) // and not except start
1236 
             begin
1237 351 julius 
 
1238 449 julius 
                // Propegate jump-tracking variables
1239 
                // If was exception in delay slot, we didn't actually jump
1240 
                // so don't set jumped in this case.
1241 
                jumped = exception_here ? 0 : jump_dslot;
1242 
                jump_dslot = jumping;
1243 
                jumping = 0;
1244 
                rfe = 0;
1245 
 
1246 
                // Now, check if current instruction will jump/branch, this is
1247 
                // needed by the exception checking code, sets will_jump=1
1248 
                check_for_jump(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
1249 
 
1250 
                // Now check if it's an exception this instruction
1251 
                check_incoming_exceptions;
1252 
 
1253 
                // Case where we just went to an exception after a jump, so we
1254 
                // mark the address we were meant to jump to as a place which will
1255 
                // have duplicate return entries in the expected address list
1256 
                if (exception_here & (jumped | jump_dslot))
1257 
                  begin
1258 
                     $display("%t: marked as jump address with exception (dup)"
1259 
                              ,$time);
1260 
                     mark_duplicate_expected_address;
1261 
                  end
1262 
 
1263 
                or1200_check_execution(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn,
1264 
                                       `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
1265 
                                       exception_here);
1266 
                //$write("%t: pc:0x%h\t",$time,
1267 
                //       `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc);
1268 
                // Decode the instruction, print it out
1269 
                //or1200_print_op(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
1270 
                //$write("\t exc:%0h dsl:%0h\n",exception_here,jump_dslot);
1271 
 
1272 
 
1273 
 
1274 
             end
1275 
        end // if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze)
1276 
     end // always @ (posedge `CPU_CORE_CLK)
1277 
`endif
1278 
 
1279 
 
1280 
   task or1200_check_execution;
1281 
      input [31:0] insn;
1282 
      input [31:0] pc;
1283 
      input        exception;
1284 
 
1285 
      reg [5:0]    opcode;
1286 
 
1287 
      reg [25:0]   j_imm;
1288 
      reg [25:0]   br_imm;
1289 
 
1290 
      reg [4:0]    rD_num, rA_num, rB_num;
1291 
      reg [31:0]   rD_val, rA_val, rB_val;
1292 
      reg [15:0]   imm_16bit;
1293 
 
1294 
      reg [15:0]   mtspr_imm;
1295 
 
1296 
      reg [3:0]    alu_op;
1297 
      reg [1:0]    shrot_op;
1298 
 
1299 
      reg [5:0]    shroti_imm;
1300 
 
1301 
      reg [5:0]    sf_op;
1302 
 
1303 
      reg [5:0]    xsync_op;
1304 
 
1305 
      reg          flag;
1306 
 
1307 
      reg [31:0]   br_j_ea; // Branch/jump effective address
1308 
 
1309 
 
1310 
      begin
1311 
 
1312 
         // Instruction opcode
1313 
         opcode = insn[`OR1K_OPCODE_POS];
1314 
         // Immediates for jump or branch instructions
1315 
         j_imm = insn[`OR1K_J_BR_IMM_POS];
1316 
         br_imm = insn[`OR1K_J_BR_IMM_POS];
1317 
         // Register numbers (D, A and B)
1318 
         rD_num = insn[`OR1K_RD_POS];
1319 
         rA_num = insn[`OR1K_RA_POS];
1320 
         rB_num = insn[`OR1K_RB_POS];
1321 
         // Bottom 16 bits when used as immediates in various instructions
1322 
         imm_16bit = insn[15:0];
1323 
         // 16-bit immediate for mtspr instructions
1324 
         mtspr_imm = {insn[25:21],insn[10:0]};
1325 
         // ALU op for ALU instructions
1326 
         alu_op = insn[`OR1K_ALU_OP_POS];
1327 
         // Shift-rotate op for SHROT ALU instructions
1328 
         shrot_op = insn[`OR1K_SHROT_OP_POS];
1329 
         shroti_imm = insn[`OR1K_SHROTI_IMM_POS];
1330 
 
1331 
         // Set flag op
1332 
         sf_op = insn[`OR1K_SF_OP];
1333 
 
1334 
         // Xsync/syscall/trap opcode
1335 
         xsync_op = insn[`OR1K_XSYNC_OP_POS];
1336 
 
1337 
         // Use the flag from the previous instruction, as the decision
1338 
         // is made in the execute stage not in te writeback stage,
1339 
         // which is where we're getting our instructions.
1340 
         flag = previous_sr[`OR1200_SR_F];
1341 
 
1342 
         update_current_gprs;
1343 
 
1344 
         // Check MSbit of the immediate, sign extend if set
1345 
         br_j_ea = j_imm[25] ? pc + {4'hf,j_imm,2'b00} :
1346 
                   pc + {4'h0,j_imm,2'b00};
1347 
 
1348 
         if (exception)
1349 
           begin
1350 
              $display("%t: exception - at 0x%x",$time, pc);
1351 
              // get epcr, put it in the addresses we expect to jump
1352 
              // back to
1353 
              // Maybe DON'T do this. Because maybe in linux things we
1354 
              // interrupt out of, we don't want to execute them again?
1355 
              //add_expected_address(current_epcr);
1356 
           end
1357 
 
1358 
 
1359 
         check_expected_address(pc, (jumped & !exception));
1360 
 
1361 
         rfe = 0;
1362 
 
1363 
         case (opcode)
1364 
           `OR1200_OR32_J:
1365 
             begin
1366 
                //
1367 
                // PC < - exts(Immediate < < 2) + JumpInsnAddr
1368 
                //
1369 
                //The immediate value is shifted left two bits, sign-extended
1370 
                // to program counter width, and then added to the address of
1371 
                // the jump instruction. The result is the effective address
1372 
                // of the jump. The program unconditionally jumps to EA with
1373 
                // a delay of one instruction.
1374 
 
1375 
                add_expected_address(br_j_ea);
1376 
 
1377 
                jumping = 1;
1378 
             end
1379 
           `OR1200_OR32_JAL:
1380 
             begin
1381 
                //
1382 
                //PC < - exts(Immediate < < 2) + JumpInsnAddr
1383 
                //LR < - DelayInsnAddr + 4
1384 
                //
1385 
                // Link reg is r9, check it is PC+8
1386 
                //
1387 
                add_expected_address(br_j_ea);
1388 
                assert_gpr_val(9, pc+8, pc);
1389 
                jumping = 1;    //
1390 
             end
1391 
           `OR1200_OR32_BNF:
1392 
             begin
1393 
                //EA < - exts(Immediate < < 2) + BranchInsnAddr
1394 
                //PC < - EA if SR[F] cleared
1395 
                if (!flag)
1396 
                  begin
1397 
                     add_expected_address(br_j_ea);
1398 
                     jumping = 1;
1399 
                  end
1400 
             end
1401 
           `OR1200_OR32_BF:
1402 
             begin
1403 
                //EA < - exts(Immediate < < 2) + BranchInsnAddr
1404 
                //PC < - EA if SR[F] set
1405 
                if (flag)
1406 
                  begin
1407 
                     add_expected_address(br_j_ea);
1408 
                     jumping = 1;
1409 
                  end
1410 
             end
1411 
           `OR1200_OR32_RFE:
1412 
             begin
1413 
                add_expected_address(current_epcr);
1414 
                // jumping variable keeps track of jumps/branches with delay
1415 
                // slot - there is none for l.rfe
1416 
                rfe = 1;
1417 
             end
1418 
           `OR1200_OR32_JR:
1419 
             begin
1420 
                //PC < - rB
1421 
                get_gpr(rB_num, rB_val);
1422 
                add_expected_address(rB_val);
1423 
                jumping = 1;
1424 
             end
1425 
           `OR1200_OR32_JALR:
1426 
             begin
1427 
                //PC < - rB
1428 
                //LR < - DelayInsnAddr + 4
1429 
                get_gpr(rB_num, rB_val);
1430 
                add_expected_address(rB_val);
1431 
                assert_gpr_val(9, pc+8, pc);
1432 
                jumping = 1;
1433 
             end
1434 
           /*
1435 
            `OR1200_OR32_LWZ,
1436 
            `OR1200_OR32_LBZ,
1437 
            `OR1200_OR32_LBS,
1438 
            `OR1200_OR32_LHZ,
1439 
            `OR1200_OR32_LHS,
1440 
            `OR1200_OR32_SW,
1441 
            `OR1200_OR32_SB,
1442 
            `OR1200_OR32_SH:
1443 
            begin
1444 
            // Should result in databus access if data cache disabled
1445 
            $display("%t: lsu instruction",$time);
1446 
end
1447 
 
1448 
            `OR1200_OR32_MFSPR,
1449 
            `OR1200_OR32_MTSPR:
1450 
            begin
1451 
            // Confirm RF values end up in the correct SPR
1452 
            $display("%t: mxspr",$time);
1453 
end
1454 
 
1455 
            `OR1200_OR32_MOVHI,
1456 
            `OR1200_OR32_ADDI,
1457 
            `OR1200_OR32_ADDIC,
1458 
            `OR1200_OR32_ANDI,
1459 
            `OR1200_OR32_ORI,
1460 
            `OR1200_OR32_XORI,
1461 
            `OR1200_OR32_MULI,
1462 
            `OR1200_OR32_ALU:
1463 
            begin
1464 
            // Double check operations done on RF and immediate values
1465 
            $display("%t: ALU op",$time);
1466 
end
1467 
 
1468 
            `OR1200_OR32_SH_ROTI:
1469 
            begin
1470 
            // Rotate according to immediate - maybe should be in ALU ops
1471 
            $display("%t: rotate op",$time);
1472 
end
1473 
 
1474 
            `OR1200_OR32_SFXXI,
1475 
            `OR1200_OR32_SFXX:
1476 
            begin
1477 
            // Set flag - do the check oursevles, check flag
1478 
            $display("%t: set flag op",$time);
1479 
end
1480 
 
1481 
            `OR1200_OR32_MACI,
1482 
            `OR1200_OR32_MACMSB:
1483 
            begin
1484 
            // Either, multiply signed and accumulate, l.mac
1485 
            // or multiply signed and subtract, l.msb
1486 
            $display("%t: MAC op",$time);
1487 
end
1488 
            */
1489 
 
1490 
           /*default:
1491 
            begin
1492 
            $display("%t: Unknown opcode 0x%h at pc 0x%x\n",
1493 
            $time,opcode, pc);
1494 
end
1495 
            */
1496 
         endcase // case (opcode)
1497 
 
1498 
         update_previous_gprs;
1499 
 
1500 
      end
1501 
   endtask // or1200_check_execution
1502 348 julius 
 
1503 351 julius 
 
1504 449 julius 
   /////////////////////////////////////////////////////////////////////////
1505 
   // Instruction decode task
1506 
   /////////////////////////////////////////////////////////////////////////
1507 351 julius 
 
1508 
   task or1200_print_op;
1509 
      input [31:0] insn;
1510 
 
1511 
      reg [5:0]    opcode;
1512 
 
1513 
      reg [25:0]   j_imm;
1514 
      reg [25:0]   br_imm;
1515 
 
1516 
      reg [4:0]    rD_num, rA_num, rB_num;
1517 
      reg [31:0]   rA_val, rB_val;
1518 
      reg [15:0]   imm_16bit;
1519 
      reg [10:0]   imm_split16bit;
1520 
 
1521 
      reg [3:0]    alu_op;
1522 
      reg [1:0]    shrot_op;
1523 
 
1524 
      reg [5:0]    shroti_imm;
1525 
 
1526 449 julius 
      reg [5:0]    sf_op;
1527 351 julius 
 
1528 449 julius 
      reg [5:0]    xsync_op;
1529 
 
1530 351 julius 
      begin
1531 
         // Instruction opcode
1532 449 julius 
         opcode = insn[`OR1K_OPCODE_POS];
1533 351 julius 
         // Immediates for jump or branch instructions
1534 449 julius 
         j_imm = insn[`OR1K_J_BR_IMM_POS];
1535 
         br_imm = insn[`OR1K_J_BR_IMM_POS];
1536 351 julius 
         // Register numbers (D, A and B)
1537 449 julius 
         rD_num = insn[`OR1K_RD_POS];
1538 
         rA_num = insn[`OR1K_RA_POS];
1539 
         rB_num = insn[`OR1K_RB_POS];
1540 351 julius 
         // Bottom 16 bits when used as immediates in various instructions
1541 
         imm_16bit = insn[15:0];
1542 
         // Bottom 11 bits used as immediates for l.sX instructions
1543 
 
1544 
         // Split 16-bit immediate for l.mtspr/l.sX instructions
1545 
         imm_split16bit = {insn[25:21],insn[10:0]};
1546 
         // ALU op for ALU instructions
1547 449 julius 
         alu_op = insn[`OR1K_ALU_OP_POS];
1548 351 julius 
         // Shift-rotate op for SHROT ALU instructions
1549 449 julius 
         shrot_op = insn[`OR1K_SHROT_OP_POS];
1550 
         shroti_imm = insn[`OR1K_SHROTI_IMM_POS];
1551 351 julius 
 
1552 
         // Set flag op
1553 449 julius 
         sf_op = insn[`OR1K_SF_OP];
1554 351 julius 
 
1555 449 julius 
         // Xsync/syscall/trap opcode
1556 
         xsync_op = insn[`OR1K_XSYNC_OP_POS];
1557 
 
1558 351 julius 
         case (opcode)
1559 
           `OR1200_OR32_J:
1560 
             begin
1561 449 julius 
                $fwrite(finsn,"l.j 0x%h", {j_imm,2'b00});
1562 351 julius 
             end
1563 
 
1564 
           `OR1200_OR32_JAL:
1565 
             begin
1566 449 julius 
                $fwrite(finsn,"l.jal 0x%h", {j_imm,2'b00});
1567 351 julius 
             end
1568 
 
1569 
           `OR1200_OR32_BNF:
1570 
             begin
1571 449 julius 
                $fwrite(finsn,"l.bnf 0x%h", {br_imm,2'b00});
1572 351 julius 
             end
1573 
 
1574 
           `OR1200_OR32_BF:
1575 
             begin
1576 449 julius 
                $fwrite(finsn,"l.bf 0x%h", {br_imm,2'b00});
1577 351 julius 
             end
1578 
 
1579 
           `OR1200_OR32_RFE:
1580 
             begin
1581 449 julius 
                $fwrite(finsn,"l.rfe");
1582 351 julius 
             end
1583 
 
1584 
           `OR1200_OR32_JR:
1585 
             begin
1586 449 julius 
                $fwrite(finsn,"l.jr r%0d",rB_num);
1587 351 julius 
             end
1588 
 
1589 
           `OR1200_OR32_JALR:
1590 
             begin
1591 449 julius 
                $fwrite(finsn,"l.jalr r%0d",rB_num);
1592 351 julius 
             end
1593 
 
1594 
           `OR1200_OR32_LWZ:
1595 
             begin
1596 449 julius 
                $fwrite(finsn,"l.lwz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1597 351 julius 
             end
1598 
 
1599 
           `OR1200_OR32_LBZ:
1600 
             begin
1601 449 julius 
                $fwrite(finsn,"l.lbz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1602 351 julius 
             end
1603 
 
1604 
           `OR1200_OR32_LBS:
1605 
             begin
1606 449 julius 
                $fwrite(finsn,"l.lbs r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1607 351 julius 
             end
1608 
 
1609 
           `OR1200_OR32_LHZ:
1610 
             begin
1611 449 julius 
                $fwrite(finsn,"l.lhz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1612 351 julius 
             end
1613 
 
1614 
           `OR1200_OR32_LHS:
1615 
             begin
1616 449 julius 
                $fwrite(finsn,"l.lhs r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1617 351 julius 
             end
1618 
 
1619 
           `OR1200_OR32_SW:
1620 
             begin
1621 449 julius 
                $fwrite(finsn,"l.sw 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
1622 351 julius 
             end
1623 
 
1624 
           `OR1200_OR32_SB:
1625 
             begin
1626 449 julius 
                $fwrite(finsn,"l.sb 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
1627 351 julius 
             end
1628 
 
1629 
           `OR1200_OR32_SH:
1630 
             begin
1631 449 julius 
                $fwrite(finsn,"l.sh 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
1632 351 julius 
             end
1633 
 
1634 
           `OR1200_OR32_MFSPR:
1635 
             begin
1636 449 julius 
                $fwrite(finsn,"l.mfspr r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit,);
1637 351 julius 
             end
1638 
 
1639 
           `OR1200_OR32_MTSPR:
1640 
             begin
1641 449 julius 
                $fwrite(finsn,"l.mtspr r%0d,r%0d,0x%h",rA_num,rB_num,imm_split16bit);
1642 351 julius 
             end
1643 
 
1644 
           `OR1200_OR32_MOVHI:
1645 
             begin
1646 
                if (!insn[16])
1647 449 julius 
                  $fwrite(finsn,"l.movhi r%0d,0x%h",rD_num,imm_16bit);
1648 351 julius 
                else
1649 449 julius 
                  $fwrite(finsn,"l.macrc r%0d",rD_num);
1650 351 julius 
             end
1651 
 
1652 
           `OR1200_OR32_ADDI:
1653 
             begin
1654 449 julius 
                $fwrite(finsn,"l.addi r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1655 351 julius 
             end
1656 
 
1657 
           `OR1200_OR32_ADDIC:
1658 
             begin
1659 449 julius 
                $fwrite(finsn,"l.addic r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1660 351 julius 
             end
1661 
 
1662 
           `OR1200_OR32_ANDI:
1663 
             begin
1664 449 julius 
                $fwrite(finsn,"l.andi r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1665 351 julius 
             end
1666 
 
1667 
           `OR1200_OR32_ORI:
1668 
             begin
1669 449 julius 
                $fwrite(finsn,"l.ori r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1670 351 julius 
             end
1671 
 
1672 
           `OR1200_OR32_XORI:
1673 
             begin
1674 449 julius 
                $fwrite(finsn,"l.xori r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1675 351 julius 
             end
1676 
 
1677 
           `OR1200_OR32_MULI:
1678 
             begin
1679 449 julius 
                $fwrite(finsn,"l.muli r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1680 351 julius 
             end
1681 
 
1682 
           `OR1200_OR32_ALU:
1683 
             begin
1684 
                case(alu_op)
1685 
                  `OR1200_ALUOP_ADD:
1686 449 julius 
                    $fwrite(finsn,"l.add ");
1687 351 julius 
                  `OR1200_ALUOP_ADDC:
1688 449 julius 
                    $fwrite(finsn,"l.addc ");
1689 351 julius 
                  `OR1200_ALUOP_SUB:
1690 449 julius 
                    $fwrite(finsn,"l.sub ");
1691 351 julius 
                  `OR1200_ALUOP_AND:
1692 449 julius 
                    $fwrite(finsn,"l.and ");
1693 351 julius 
                  `OR1200_ALUOP_OR:
1694 449 julius 
                    $fwrite(finsn,"l.or ");
1695 351 julius 
                  `OR1200_ALUOP_XOR:
1696 449 julius 
                    $fwrite(finsn,"l.xor ");
1697 351 julius 
                  `OR1200_ALUOP_MUL:
1698 449 julius 
                    $fwrite(finsn,"l.mul ");
1699 351 julius 
                  `OR1200_ALUOP_SHROT:
1700 
                    begin
1701 
                       case(shrot_op)
1702 
                         `OR1200_SHROTOP_SLL:
1703 449 julius 
                           $fwrite(finsn,"l.sll ");
1704 351 julius 
                         `OR1200_SHROTOP_SRL:
1705 449 julius 
                           $fwrite(finsn,"l.srl ");
1706 351 julius 
                         `OR1200_SHROTOP_SRA:
1707 449 julius 
                           $fwrite(finsn,"l.sra ");
1708 351 julius 
                         `OR1200_SHROTOP_ROR:
1709 449 julius 
                           $fwrite(finsn,"l.ror ");
1710 351 julius 
                       endcase // case (shrot_op)
1711 
                    end
1712 
                  `OR1200_ALUOP_DIV:
1713 449 julius 
                    $fwrite(finsn,"l.div ");
1714 351 julius 
                  `OR1200_ALUOP_DIVU:
1715 449 julius 
                    $fwrite(finsn,"l.divu ");
1716 351 julius 
                  `OR1200_ALUOP_CMOV:
1717 449 julius 
                    $fwrite(finsn,"l.cmov ");
1718 351 julius 
                endcase // case (alu_op)
1719 449 julius 
                $fwrite(finsn,"r%0d,r%0d,r%0d",rD_num,rA_num,rB_num);
1720 351 julius 
             end
1721 
 
1722 
           `OR1200_OR32_SH_ROTI:
1723 
             begin
1724 
                case(shrot_op)
1725 
                  `OR1200_SHROTOP_SLL:
1726 449 julius 
                    $fwrite(finsn,"l.slli ");
1727 351 julius 
                  `OR1200_SHROTOP_SRL:
1728 449 julius 
                    $fwrite(finsn,"l.srli ");
1729 351 julius 
                  `OR1200_SHROTOP_SRA:
1730 449 julius 
                    $fwrite(finsn,"l.srai ");
1731 351 julius 
                  `OR1200_SHROTOP_ROR:
1732 449 julius 
                    $fwrite(finsn,"l.rori ");
1733 351 julius 
                endcase // case (shrot_op)
1734 449 julius 
                $fwrite(finsn,"r%0d,r%0d,0x%h",rD_num,rA_num,shroti_imm);
1735 351 julius 
             end
1736 
 
1737 
           `OR1200_OR32_SFXXI:
1738 
             begin
1739 
                case(sf_op[2:0])
1740 
                  `OR1200_COP_SFEQ:
1741 449 julius 
                    $fwrite(finsn,"l.sfeqi ");
1742 351 julius 
                  `OR1200_COP_SFNE:
1743 449 julius 
                    $fwrite(finsn,"l.sfnei ");
1744 351 julius 
                  `OR1200_COP_SFGT:
1745 
                    begin
1746 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1747 449 julius 
                         $fwrite(finsn,"l.sfgtsi ");
1748 351 julius 
                       else
1749 449 julius 
                         $fwrite(finsn,"l.sfgtui ");
1750 351 julius 
                    end
1751 
                  `OR1200_COP_SFGE:
1752 
                    begin
1753 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1754 449 julius 
                         $fwrite(finsn,"l.sfgesi ");
1755 351 julius 
                       else
1756 449 julius 
                         $fwrite(finsn,"l.sfgeui ");
1757 351 julius 
                    end
1758 
                  `OR1200_COP_SFLT:
1759 
                    begin
1760 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1761 449 julius 
                         $fwrite(finsn,"l.sfltsi ");
1762 351 julius 
                       else
1763 449 julius 
                         $fwrite(finsn,"l.sfltui ");
1764 351 julius 
                    end
1765 
                  `OR1200_COP_SFLE:
1766 
                    begin
1767 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1768 449 julius 
                         $fwrite(finsn,"l.sflesi ");
1769 351 julius 
                       else
1770 449 julius 
                         $fwrite(finsn,"l.sfleui ");
1771 351 julius 
                    end
1772 
                endcase // case (sf_op[2:0])
1773 
 
1774 449 julius 
                $fwrite(finsn,"r%0d,0x%h",rA_num, imm_16bit);
1775 351 julius 
 
1776 
             end // case: `OR1200_OR32_SFXXI
1777 
 
1778 
           `OR1200_OR32_SFXX:
1779 
             begin
1780 
                case(sf_op[2:0])
1781 
                  `OR1200_COP_SFEQ:
1782 449 julius 
                    $fwrite(finsn,"l.sfeq ");
1783 351 julius 
                  `OR1200_COP_SFNE:
1784 449 julius 
                    $fwrite(finsn,"l.sfne ");
1785 351 julius 
                  `OR1200_COP_SFGT:
1786 
                    begin
1787 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1788 449 julius 
                         $fwrite(finsn,"l.sfgts ");
1789 351 julius 
                       else
1790 449 julius 
                         $fwrite(finsn,"l.sfgtu ");
1791 351 julius 
                    end
1792 
                  `OR1200_COP_SFGE:
1793 
                    begin
1794 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1795 449 julius 
                         $fwrite(finsn,"l.sfges ");
1796 351 julius 
                       else
1797 449 julius 
                         $fwrite(finsn,"l.sfgeu ");
1798 351 julius 
                    end
1799 
                  `OR1200_COP_SFLT:
1800 
                    begin
1801 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1802 449 julius 
                         $fwrite(finsn,"l.sflts ");
1803 351 julius 
                       else
1804 449 julius 
                         $fwrite(finsn,"l.sfltu ");
1805 351 julius 
                    end
1806 
                  `OR1200_COP_SFLE:
1807 
                    begin
1808 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1809 449 julius 
                         $fwrite(finsn,"l.sfles ");
1810 351 julius 
                       else
1811 449 julius 
                         $fwrite(finsn,"l.sfleu ");
1812 351 julius 
                    end
1813 
 
1814 
                endcase // case (sf_op[2:0])
1815 
 
1816 449 julius 
                $fwrite(finsn,"r%0d,r%0d",rA_num, rB_num);
1817 351 julius 
 
1818 
             end
1819 
 
1820 
           `OR1200_OR32_MACI:
1821 
             begin
1822 449 julius 
                $fwrite(finsn,"l.maci r%0d,0x%h",rA_num,imm_16bit);
1823 351 julius 
             end
1824 
 
1825 
           `OR1200_OR32_MACMSB:
1826 
             begin
1827 
                if(insn[3:0] == 4'h1)
1828 449 julius 
                  $fwrite(finsn,"l.mac ");
1829 351 julius 
                else if(insn[3:0] == 4'h2)
1830 449 julius 
                  $fwrite(finsn,"l.msb ");
1831 351 julius 
 
1832 449 julius 
                $fwrite(finsn,"r%0d,r%0d",rA_num,rB_num);
1833 351 julius 
             end
1834 
 
1835 
           `OR1200_OR32_NOP:
1836 
             begin
1837 449 julius 
                $fwrite(finsn,"l.nop 0x%0h",imm_16bit);
1838 351 julius 
             end
1839 
 
1840 
           `OR1200_OR32_XSYNC:
1841 
             begin
1842 
                case (xsync_op)
1843 
                  5'd0:
1844 449 julius 
                    $fwrite(finsn,"l.sys 0x%h",imm_16bit);
1845 351 julius 
                  5'd8:
1846 449 julius 
                    $fwrite(finsn,"l.trap 0x%h",imm_16bit);
1847 351 julius 
                  5'd16:
1848 449 julius 
                    $fwrite(finsn,"l.msync");
1849 351 julius 
                  5'd20:
1850 449 julius 
                    $fwrite(finsn,"l.psync");
1851 351 julius 
                  5'd24:
1852 449 julius 
                    $fwrite(finsn,"l.csync");
1853 351 julius 
                  default:
1854 
                    begin
1855 
                       $display("%t: Instruction with opcode 0x%h has bad specific type information: 0x%h",$time,opcode,insn);
1856 449 julius 
                       $fwrite(finsn,"%t: Instruction with opcode 0x%h has has bad specific type information: 0x%h",$time,opcode,insn);
1857 351 julius 
                    end
1858 
                endcase // case (xsync_op)
1859 
             end
1860 
 
1861 
           default:
1862 
             begin
1863 
                $display("%t: Unknown opcode 0x%h",$time,opcode);
1864 449 julius 
                $fwrite(finsn,"%t: Unknown opcode 0x%h",$time,opcode);
1865 351 julius 
             end
1866 
 
1867 
         endcase // case (opcode)
1868 
 
1869 
      end
1870 
   endtask // or1200_print_op
1871 
 
1872 
 
1873 
 
1874 6 julius 
endmodule

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