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1 6 julius 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 449 julius 
////  or1200_monitor.v                                            ////
4 360 julius 
////                                                              ////
5 
////  OR1200 processor monitor module                             ////
6 
////                                                              ////
7 449 julius 
////  Author(s):                                                  ////
8 
////      - Damjan Lampret, lampret@opencores.org                 ////
9 
////      - Julius Baxter, julius@opencores.org                   ////
10 
////                                                              ////
11 360 julius 
//////////////////////////////////////////////////////////////////////
12 
////                                                              ////
13 348 julius 
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
14 6 julius 
////                                                              ////
15 
//// This source file may be used and distributed without         ////
16 
//// restriction provided that this copyright statement is not    ////
17 
//// removed from the file and that any derivative work contains  ////
18 
//// the original copyright notice and the associated disclaimer. ////
19 
////                                                              ////
20 
//// This source file is free software; you can redistribute it   ////
21 
//// and/or modify it under the terms of the GNU Lesser General   ////
22 
//// Public License as published by the Free Software Foundation; ////
23 
//// either version 2.1 of the License, or (at your option) any   ////
24 
//// later version.                                               ////
25 
////                                                              ////
26 
//// This source is distributed in the hope that it will be       ////
27 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
28 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
29 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
30 
//// details.                                                     ////
31 
////                                                              ////
32 
//// You should have received a copy of the GNU Lesser General    ////
33 
//// Public License along with this source; if not, download it   ////
34 
//// from http://www.opencores.org/lgpl.shtml                     ////
35 
////                                                              ////
36 
//////////////////////////////////////////////////////////////////////
37 67 julius 
 
38 55 julius 
`include "timescale.v"
39 6 julius 
`include "or1200_defines.v"
40 360 julius 
`include "orpsoc-testbench-defines.v"
41 
`include "test-defines.v"
42 415 julius 
 
43 6 julius 
//
44 415 julius 
// Top of TB
45 
//
46 
`define TB_TOP orpsoc_testbench
47 449 julius 
 
48 415 julius 
//
49 
// Top of DUT
50 
//
51 
`define DUT_TOP `TB_TOP.dut
52 449 julius 
 
53 415 julius 
//
54 6 julius 
// Top of OR1200 inside test bench
55 
//
56 415 julius 
`define OR1200_TOP `DUT_TOP.or1200_top0
57 360 julius 
 
58 397 julius 
//
59 
// Define to enable lookup file generation
60 
//
61 
//`define OR1200_MONITOR_LOOKUP
62 360 julius 
 
63 6 julius 
//
64 397 julius 
// Define to enable SPR access log file generation
65 6 julius 
//
66 397 julius 
//`define OR1200_MONITOR_SPRS
67 6 julius 
 
68 348 julius 
//
69 397 julius 
// Enable logging of state during execution
70 351 julius 
//
71 397 julius 
//`define OR1200_MONITOR_EXEC_STATE
72 
 
73 
//
74 
// Enable disassembly of instructions in execution state log
75 
//
76 449 julius 
//`define OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
77 351 julius 
 
78 449 julius 
//
79 456 julius 
// Enable verbose report l.nops (to both general log file and stdout)
80 
//
81 
`define OR1200_MONITOR_VERBOSE_NOPS
82 
 
83 
//
84 449 julius 
// Enable monitoring of control and execution flow (experimental)
85 
//
86 
//`define OR1200_SYSTEM_CHECKER
87 
 
88 397 julius 
// Can either individually enable things above, or usually have the scripts
89 
// running the simulation pass the PROCESSOR_MONITOR_ENABLE_LOGS define to
90 
// enable them all.
91 351 julius 
 
92 397 julius 
`ifdef PROCESSOR_MONITOR_ENABLE_LOGS
93 
 `define OR1200_MONITOR_EXEC_STATE
94 
 `define OR1200_MONITOR_SPRS
95 
 `define OR1200_MONITOR_LOOKUP
96 
`endif
97 
 
98 351 julius 
//
99 415 julius 
// Memory coherence checking (double check instruction in fetch stage against
100 
// what is in memory.)
101 
//
102 
//`define MEM_COHERENCE_CHECK
103 
 
104 
//
105 348 julius 
// Top of OR1200 inside test bench
106 
//
107 
`define CPU or1200
108 
`define CPU_cpu or1200_cpu
109 
`define CPU_rf or1200_rf
110 
`define CPU_except or1200_except
111 
`define CPU_ctrl or1200_ctrl
112 
`define CPU_sprs or1200_sprs
113 449 julius 
`define CPU_immu_top or1200_immu_top
114 
`define CPU_immu_tlb or1200_immu_tlb
115 
`define CPU_CORE_CLK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk
116 348 julius 
 
117 449 julius 
 
118 
`define OR1K_OPCODE_POS 31:26
119 
`define OR1K_J_BR_IMM_POS 25:0
120 
`define OR1K_RD_POS 25:21
121 
`define OR1K_RA_POS 20:16
122 
`define OR1K_RB_POS 15:11
123 
`define OR1K_ALU_OP_POS 3:0
124 
 
125 
`define OR1K_SHROT_OP_POS 7:6
126 
`define OR1K_SHROTI_IMM_POS 5:0
127 
`define OR1K_SF_OP 25:21
128 
 
129 
`define OR1K_XSYNC_OP_POS 25:21
130 
 
131 
 
132 6 julius 
module or1200_monitor;
133 
 
134 
   integer fexe;
135 449 julius 
   integer finsn;
136 
 
137 6 julius 
   reg [23:0] ref;
138 397 julius 
`ifdef OR1200_MONITOR_SPRS
139 6 julius 
   integer    fspr;
140 397 julius 
`endif
141 6 julius 
   integer    fgeneral;
142 397 julius 
`ifdef OR1200_MONITOR_LOOKUP
143 6 julius 
   integer    flookup;
144 397 julius 
`endif
145 6 julius 
   integer    r3;
146 
   integer    insns;
147 
 
148 348 julius 
 
149 6 julius 
   //
150 
   // Initialization
151 
   //
152 
   initial begin
153 
      ref = 0;
154 397 julius 
`ifdef OR1200_MONITOR_EXEC_STATE
155 360 julius 
      fexe = $fopen({"../out/",`TEST_NAME_STRING,"-executed.log"});
156 449 julius 
`endif
157 
`ifdef OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
158 
      finsn = fexe;
159 397 julius 
`endif
160 6 julius 
      $timeformat (-9, 2, " ns", 12);
161 397 julius 
`ifdef OR1200_MONITOR_SPRS
162 360 julius 
      fspr = $fopen({"../out/",`TEST_NAME_STRING,"-sprs.log"});
163 397 julius 
`endif
164 360 julius 
      fgeneral = $fopen({"../out/",`TEST_NAME_STRING,"-general.log"});
165 397 julius 
`ifdef OR1200_MONITOR_LOOKUP
166 360 julius 
      flookup = $fopen({"../out/",`TEST_NAME_STRING,"-lookup.log"});
167 397 julius 
`endif
168 6 julius 
      insns = 0;
169 
 
170 
   end
171 
 
172 
   //
173 
   // Get GPR
174 
   //
175 
   task get_gpr;
176 
      input     [4:0]    gpr_no;
177 
      output [31:0]      gpr;
178 
      integer           j;
179 
      begin
180 348 julius 
 
181 449 julius 
`ifdef OR1200_RFRAM_GENERIC
182 6 julius 
         for(j = 0; j < 32; j = j + 1) begin
183 348 julius 
            gpr[j] = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no*32+j];
184 6 julius 
         end
185 348 julius 
 
186 449 julius 
`else
187 348 julius 
         //gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no];
188 
         gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.get_gpr(gpr_no);
189 
 
190 449 julius 
`endif
191 6 julius 
 
192 348 julius 
 
193 
      end
194 
   endtask
195 
 
196 6 julius 
   //
197 
   // Write state of the OR1200 registers into a file
198 
   //
199 
   // Limitation: only a small subset of register file RAMs
200 
   // are supported
201 
   //
202 
   task display_arch_state;
203 
      reg [5:0] i;
204 
      reg [31:0] r;
205 
      integer    j;
206 
      begin
207 397 julius 
`ifdef OR1200_MONITOR_EXEC_STATE
208 6 julius 
         ref = ref + 1;
209 397 julius 
 `ifdef OR1200_MONITOR_LOOKUP
210 6 julius 
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
211 397 julius 
 `endif
212 351 julius 
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h", insns,
213 
                 `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
214 
                 `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
215 449 julius 
 `ifdef OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
216 351 julius 
         $fwrite(fexe,"\t");
217 
         // Decode the instruction, print it out
218 
         or1200_print_op(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
219 
 `endif
220 6 julius 
         for(i = 0; i < 32; i = i + 1) begin
221 
            if (i % 4 == 0)
222 
              $fdisplay(fexe);
223 
            get_gpr(i, r);
224 
            $fwrite(fexe, "GPR%d: %h  ", i, r);
225 
         end
226 
         $fdisplay(fexe);
227 348 julius 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
228 6 julius 
         $fwrite(fexe, "SR   : %h  ", r);
229 348 julius 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
230 6 julius 
         $fwrite(fexe, "EPCR0: %h  ", r);
231 348 julius 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
232 6 julius 
         $fwrite(fexe, "EEAR0: %h  ", r);
233 348 julius 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
234 6 julius 
         $fdisplay(fexe, "ESR0 : %h", r);
235 397 julius 
`endif //  `ifdef OR1200_MONITOR_EXEC_STATE
236 348 julius 
`ifdef OR1200_DISPLAY_EXECUTED
237 
         ref = ref + 1;
238 397 julius 
 `ifdef OR1200_MONITOR_LOOKUP
239 348 julius 
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
240 397 julius 
 `endif
241 348 julius 
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
242 6 julius 
`endif
243 348 julius 
         insns = insns + 1;
244 449 julius 
      end
245 6 julius 
   endtask // display_arch_state
246 
 
247 
   /* Keep a trace buffer of the last lot of instructions and addresses
248 
    * "executed",as read from the writeback stage, and cause a $finish if we hit
249 
    * an instruction that is invalid, such as all zeros.
250 
    * Currently, only breaks on an all zero instruction, but should probably be
251 
    * made to break for anything with an X in it too. And of course ideally this
252 
    * shouldn't be needed - but is handy if someone changes something and stops
253 
    * the test continuing forever.
254 
    */
255 49 julius 
   integer num_nul_inst;
256 
   initial num_nul_inst = 0;
257 449 julius 
 
258 6 julius 
   task monitor_for_crash;
259 348 julius 
`define OR1200_MONITOR_CRASH_TRACE_SIZE 32
260 
      //Trace buffer of 32 instructions
261 
      reg [31:0] insn_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
262 
      //Trace buffer of the addresses of those instructions
263 
      reg [31:0] addr_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
264 449 julius 
      integer    i;
265 6 julius 
 
266 449 julius 
      begin
267 
         if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h00000000)
268 
           num_nul_inst = num_nul_inst + 1;
269 
         else
270 
           num_nul_inst = 0; // Reset it
271 49 julius 
 
272 449 julius 
         if (num_nul_inst == 1000) // Sat a loop a bit too long...
273 
           begin
274 
              $fdisplay(fgeneral, "ERROR - no instruction at PC %h",
275 
                        `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc);
276 
              $fdisplay(fgeneral, "Crash trace: Last %d instructions: ",
277 
                        `OR1200_MONITOR_CRASH_TRACE_SIZE);
278 6 julius 
 
279 449 julius 
              $fdisplay(fgeneral, "PC\t\tINSTR");
280 
              for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
281 
                 $fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);
282 
              end
283 
              #100 $finish;
284 
           end
285 
         else
286 
           begin
287 
              for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
288 
                 insn_trace[i] = insn_trace[i-1];
289 
                 addr_trace[i] = addr_trace[i-1];
290 
              end
291 
              insn_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn;
292 
              addr_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc;
293 
           end
294 
 
295 
      end
296 6 julius 
   endtask // monitor_for_crash
297 348 julius 
 
298 6 julius 
 
299 348 julius 
   //
300 
   // Write state of the OR1200 registers into a file; version for exception
301 
   //
302 
   task display_arch_state_except;
303 
      reg [5:0] i;
304 
      reg [31:0] r;
305 
      integer    j;
306 
      begin
307 397 julius 
`ifdef OR1200_MONITOR_EXEC_STATE
308 348 julius 
         ref = ref + 1;
309 397 julius 
 `ifdef OR1200_MONITOR_LOOKUP
310 348 julius 
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
311 397 julius 
 `endif
312 348 julius 
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h  (exception)", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
313 
         for(i = 0; i < 32; i = i + 1) begin
314 
            if (i % 4 == 0)
315 
              $fdisplay(fexe);
316 
            get_gpr(i, r);
317 
            $fwrite(fexe, "GPR%d: %h  ", i, r);
318 
         end
319 
         $fdisplay(fexe);
320 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
321 
         $fwrite(fexe, "SR   : %h  ", r);
322 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
323 
         $fwrite(fexe, "EPCR0: %h  ", r);
324 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
325 
         $fwrite(fexe, "EEAR0: %h  ", r);
326 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
327 
         $fdisplay(fexe, "ESR0 : %h", r);
328 
         insns = insns + 1;
329 397 julius 
`endif //  `ifdef OR1200_MONITOR_EXEC_STATE
330 348 julius 
`ifdef OR1200_DISPLAY_EXECUTED
331 
         ref = ref + 1;
332 397 julius 
 `ifdef OR1200_MONITOR_LOOKUP
333 348 julius 
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
334 397 julius 
 `endif
335 348 julius 
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h  (exception)", insns,
336 
                 `OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc,
337 
                 `OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
338 
         insns = insns + 1;
339 
`endif
340 
 
341 449 julius 
      end
342 348 julius 
   endtask
343 
 
344 6 julius 
   integer iwb_progress;
345 
   reg [31:0] iwb_progress_addr;
346 
   //
347 
   // WISHBONE bus checker
348 
   //
349 
   always @(posedge `OR1200_TOP.iwb_clk_i)
350 
     if (`OR1200_TOP.iwb_rst_i) begin
351 
        iwb_progress = 0;
352 
        iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
353 
     end
354 
     else begin
355 
        if (`OR1200_TOP.iwb_cyc_o && (iwb_progress != 2)) begin
356 
           iwb_progress = 1;
357 
        end
358 
        if (`OR1200_TOP.iwb_stb_o) begin
359 
           if (iwb_progress >= 1) begin
360 
              if (iwb_progress == 1)
361 
                iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
362 
              iwb_progress = 2;
363 
           end
364 
           else begin
365 
              $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o raised without `OR1200_TOP.iwb_cyc_o, at %t\n", $time);
366 
              #100 $finish;
367 
           end
368 
        end
369 
        if (`OR1200_TOP.iwb_ack_i & `OR1200_TOP.iwb_err_i) begin
370 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i and `OR1200_TOP.iwb_err_i raised at the same time, at %t\n", $time);
371 
        end
372 
        if ((iwb_progress == 2) && (iwb_progress_addr != `OR1200_TOP.iwb_adr_o)) begin
373 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_adr_o changed while waiting for `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
374 
           #100 $finish;
375 
        end
376 
        if (`OR1200_TOP.iwb_ack_i | `OR1200_TOP.iwb_err_i)
377 
          if (iwb_progress == 2) begin
378 
             iwb_progress = 0;
379 
             iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
380 
          end
381 
          else begin
382 
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
383 
             #100 $finish;
384 
          end
385 
        if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
386 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
387 348 julius 
           #100 $finish;
388 6 julius 
        end
389 
     end
390 
 
391 
   integer dwb_progress;
392 449 julius 
   reg [31:0] dwb_progress_addr;
393 
   //
394 
   // WISHBONE bus checker
395 
   //
396 
   always @(posedge `OR1200_TOP.dwb_clk_i)
397 
     if (`OR1200_TOP.dwb_rst_i)
398 
       dwb_progress = 0;
399 
     else begin
400 
        if (`OR1200_TOP.dwb_cyc_o && (dwb_progress != 2))
401 
          dwb_progress = 1;
402 
        if (`OR1200_TOP.dwb_stb_o)
403 
          if (dwb_progress >= 1) begin
404 
             if (dwb_progress == 1)
405 
               dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
406 
             dwb_progress = 2;
407 
          end
408 
          else begin
409 
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o raised without `OR1200_TOP.dwb_cyc_o, at %t\n", $time);
410 
             #100 $finish;
411 
          end
412 
        if (`OR1200_TOP.dwb_ack_i & `OR1200_TOP.dwb_err_i) begin
413 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i and `OR1200_TOP.dwb_err_i raised at the same time, at %t\n", $time);
414 
        end
415 
        if ((dwb_progress == 2) && (dwb_progress_addr != `OR1200_TOP.dwb_adr_o)) begin
416 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_adr_o changed while waiting for `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
417 
           #100 $finish;
418 
        end
419 
        if (`OR1200_TOP.dwb_ack_i | `OR1200_TOP.dwb_err_i)
420 
          if (dwb_progress == 2) begin
421 
             dwb_progress = 0;
422 
             dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
423 
          end
424 
          else begin
425 
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i/`OR1200_TOP.dwb_err_i raised without `OR1200_TOP.dwb_cyc_i/`OR1200_TOP.dwb_stb_i, at %t\n", $time);
426 
             #100 $finish;
427 
          end
428 
        if ((dwb_progress == 2) && !`OR1200_TOP.dwb_stb_o) begin
429 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o lowered without `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
430 
           #100 $finish;
431 
        end
432 6 julius 
     end
433 
 
434 449 julius 
   //
435 
   // Hooks for:
436 
   // - displaying registers
437 
   // - end of simulation
438 
   // - access to SPRs
439 
   //
440 
   always @(posedge `CPU_CORE_CLK)
441 348 julius 
     if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze) begin
442 449 julius 
        //      #2;
443 348 julius 
        if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP)
444 
             | !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
445 
            & !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &
446 
                `OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot))
447 6 julius 
          begin
448 
             display_arch_state;
449 
             monitor_for_crash;
450 
          end
451 
        else
452 348 julius 
          if (`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe)
453 6 julius 
            display_arch_state_except;
454 348 julius 
        // small hack to stop simulation (l.nop 1):
455 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
456 6 julius 
           get_gpr(3, r3);
457 
           $fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
458 456 julius 
`ifdef OR1200_MONITOR_VERBOSE_NOPS
459 
           $display("%t: l.nop exit (%h)", $time, r3);
460 
`endif
461 6 julius 
           $finish;
462 
        end
463 348 julius 
        // debug if test (l.nop 10)
464 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
465 6 julius 
           $fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
466 
        end
467 348 julius 
        // simulation reports (l.nop 2)
468 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
469 6 julius 
           get_gpr(3, r3);
470 348 julius 
           $fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
471 456 julius 
`ifdef OR1200_MONITOR_VERBOSE_NOPS
472 
           $display("%t: l.nop report (%h)", $time, r3);
473 
`endif
474 348 julius 
        end
475 
        // simulation printfs (l.nop 3)
476 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0003) begin
477 
           get_gpr(3, r3);
478 6 julius 
           $fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);
479 
        end
480 348 julius 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0004) begin
481 
           // simulation putc (l.nop 4)
482 
           get_gpr(3, r3);
483 
           $write("%c", r3);
484 
           $fdisplay(fgeneral, "%t: l.nop putc (%c)", $time, r3);
485 
        end
486 397 julius 
`ifdef OR1200_MONITOR_SPRS
487 
        if (`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
488 6 julius 
          $fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
489 397 julius 
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
490 348 julius 
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_dat_o);
491 397 julius 
        if ((|`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_cs) &
492 
            !`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
493 6 julius 
          $fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
494 348 julius 
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
495 
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.to_wbmux);
496 397 julius 
`endif
497 6 julius 
     end
498 
 
499 348 julius 
 
500 415 julius 
`ifdef RAM_WB
501 439 julius 
 `define RAM_WB_TOP `DUT_TOP.ram_wb0.ram_wb_b3_0
502 415 julius 
   task get_insn_from_wb_ram;
503 
      input [31:0] addr;
504 
      output [31:0] insn;
505 
      begin
506 439 julius 
         insn = `RAM_WB_TOP.get_mem(addr);
507 415 julius 
      end
508 
   endtask // get_insn_from_wb_ram
509 
`endif
510 
 
511 348 julius 
`ifdef VERSATILE_SDRAM
512 415 julius 
 `define SDRAM_TOP `TB_TOP.sdram0
513 348 julius 
   // Bit selects to define the bank
514 
   // 32 MB part with 4 banks
515 
 `define SDRAM_BANK_SEL_BITS 24:23
516 
 `define SDRAM_WORD_SEL_TOP_BIT 22
517 
   // Gets instruction word from correct bank
518 
   task get_insn_from_sdram;
519 
      input [31:0] addr;
520 
      output [31:0] insn;
521 
      reg [`SDRAM_WORD_SEL_TOP_BIT-1:0] word_addr;
522 449 julius 
 
523 348 julius 
      begin
524 
         word_addr = addr[`SDRAM_WORD_SEL_TOP_BIT:2];
525 
         if (addr[`SDRAM_BANK_SEL_BITS] == 2'b00)
526 
           begin
527 
 
528 
              //$display("%t: get_insn_from_sdram bank0, word 0x%h, (%h and %h in SDRAM)", $time, word_addr, `SDRAM_TOP.Bank0[{word_addr,1'b0}], `SDRAM_TOP.Bank0[{word_addr,1'b1}]);
529 
              insn[15:0] = `SDRAM_TOP.Bank0[{word_addr,1'b1}];
530 
              insn[31:16] = `SDRAM_TOP.Bank0[{word_addr,1'b0}];
531 
           end
532 
      end
533 
 
534 
   endtask // get_insn_from_sdram
535 
`endif //  `ifdef VERSATILE_SDRAM
536 
 
537 
`ifdef XILINX_DDR2
538 415 julius 
 `define DDR2_TOP `TB_TOP.gen_cs[0]
539 348 julius 
   // Gets instruction word from correct bank
540 
   task get_insn_from_xilinx_ddr2;
541 
      input [31:0] addr;
542 
      output [31:0] insn;
543 415 julius 
      reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2,
544 
                     ddr2_array_line3;
545 348 julius 
      integer        word_in_line_num;
546 
      begin
547 449 julius 
         // Get our 4 128-bit chunks (8 half-words in each!! Confused yet?),
548 
         // 16 words total
549 348 julius 
         `DDR2_TOP.gen[0].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line0);
550 
         `DDR2_TOP.gen[1].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line1);
551 
         `DDR2_TOP.gen[2].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line2);
552 
         `DDR2_TOP.gen[3].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line3);
553 
         case (addr[5:2])
554 
           4'h0:
555 
             begin
556 
                insn[15:0] = ddr2_array_line0[15:0];
557 
                insn[31:16] = ddr2_array_line1[15:0];
558 
             end
559 
           4'h1:
560 
             begin
561 
                insn[15:0] = ddr2_array_line2[15:0];
562 
                insn[31:16] = ddr2_array_line3[15:0];
563 
             end
564 
           4'h2:
565 
             begin
566 
                insn[15:0] = ddr2_array_line0[31:16];
567 
                insn[31:16] = ddr2_array_line1[31:16];
568 
             end
569 
           4'h3:
570 
             begin
571 
                insn[15:0] = ddr2_array_line2[31:16];
572 
                insn[31:16] = ddr2_array_line3[31:16];
573 
             end
574 
           4'h4:
575 
             begin
576 
                insn[15:0] = ddr2_array_line0[47:32];
577 
                insn[31:16] = ddr2_array_line1[47:32];
578 
             end
579 
           4'h5:
580 
             begin
581 
                insn[15:0] = ddr2_array_line2[47:32];
582 
                insn[31:16] = ddr2_array_line3[47:32];
583 
             end
584 
           4'h6:
585 
             begin
586 
                insn[15:0] = ddr2_array_line0[63:48];
587 
                insn[31:16] = ddr2_array_line1[63:48];
588 
             end
589 
           4'h7:
590 
             begin
591 
                insn[15:0] = ddr2_array_line2[63:48];
592 
                insn[31:16] = ddr2_array_line3[63:48];
593 
             end
594 
           4'h8:
595 
             begin
596 
                insn[15:0] = ddr2_array_line0[79:64];
597 
                insn[31:16] = ddr2_array_line1[79:64];
598 
             end
599 
           4'h9:
600 
             begin
601 
                insn[15:0] = ddr2_array_line2[79:64];
602 
                insn[31:16] = ddr2_array_line3[79:64];
603 
             end
604 
           4'ha:
605 
             begin
606 
                insn[15:0] = ddr2_array_line0[95:80];
607 
                insn[31:16] = ddr2_array_line1[95:80];
608 
             end
609 
           4'hb:
610 
             begin
611 
                insn[15:0] = ddr2_array_line2[95:80];
612 
                insn[31:16] = ddr2_array_line3[95:80];
613 
             end
614 
           4'hc:
615 
             begin
616 
                insn[15:0] = ddr2_array_line0[111:96];
617 
                insn[31:16] = ddr2_array_line1[111:96];
618 
             end
619 
           4'hd:
620 
             begin
621 
                insn[15:0] = ddr2_array_line2[111:96];
622 
                insn[31:16] = ddr2_array_line3[111:96];
623 
             end
624 
           4'he:
625 
             begin
626 
                insn[15:0] = ddr2_array_line0[127:112];
627 
                insn[31:16] = ddr2_array_line1[127:112];
628 
             end
629 
           4'hf:
630 
             begin
631 
                insn[15:0] = ddr2_array_line2[127:112];
632 
                insn[31:16] = ddr2_array_line3[127:112];
633 
             end
634 
         endcase // case (addr[5:2])
635 
      end
636 
   endtask // get_insn_from_xilinx_ddr2
637 
`endif
638 
 
639 
 
640 
   task get_insn_from_memory;
641 
      input [31:0] id_pc;
642 
      output [31:0] insn;
643 
      begin
644 
         // do a decode of which server we should look in
645 
         case (id_pc[31:28])
646 
`ifdef VERSATILE_SDRAM
647 
           4'h0:
648 
             get_insn_from_sdram(id_pc, insn);
649 
`endif
650 
`ifdef XILINX_DDR2
651 
           4'h0:
652 
             get_insn_from_xilinx_ddr2(id_pc, insn);
653 415 julius 
`endif
654 
`ifdef RAM_WB
655 
           4'h0:
656 
             get_insn_from_wb_ram(id_pc, insn);
657 
`endif
658 348 julius 
           4'hf:
659 
             // Flash isn't stored in a memory, it's an FSM so just skip/ignore
660 
             insn = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn;
661 
           default:
662 
             begin
663 
                $fdisplay(fgeneral, "%t: Unknown memory server for address 0x%h", $time,id_pc);
664 
                insn = 32'hxxxxxxxx; // Unknown server
665 
             end
666 
         endcase // case (id_pc[31:28])
667 
      end
668 
   endtask // get_insn_from_memory
669 
 
670 
 
671 449 julius 
   //
672 
   // Look in the iMMU TLB MR for this address' page, if MMUs are on and enabled
673 
   //
674 
   task check_for_immu_entry;
675 
      input [31:0] pc;
676 
      output [31:0] physical_pc;
677 
      output        mmu_tlb_miss;
678 
      integer       w,x;
679 
 
680 
      reg [31:`OR1200_IMMU_PS] pc_vpn;
681 
 
682 
      reg [`OR1200_ITLBTRW-1:0] itlb_tr;
683 
      reg [`OR1200_ITLBMRW-1:0] itlb_mr;
684 
 
685 
      integer                   tlb_index;
686 
      reg                       mmu_en;
687 
 
688 
 
689 
      begin
690 
         mmu_tlb_miss = 0;
691 
 
692 
`ifdef OR1200_NO_IMMU
693 
         physical_pc = pc;
694 
`else
695 
         mmu_en = `OR1200_TOP.`CPU_immu_top.immu_en;
696 
         // If MMU is enabled
697 
         if (mmu_en)
698 
           begin
699 
 
700 
              // Look in the iTLB for mapping - get virtual page number
701 
              pc_vpn = pc[31:`OR1200_IMMU_PS];
702 
 
703 
              tlb_index = pc[`OR1200_ITLB_INDX];
704 
 
705 
              // Look at the ITLB match register
706 
              itlb_mr = `OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_mr_ram.mem[tlb_index];
707 
 
708 
              // Get the translate register here too, in case there's an error, we print it
709 
              itlb_tr = `OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_tr_ram.mem[tlb_index];
710 
 
711 
              if ((itlb_mr[`OR1200_ITLBMR_V_BITS] === 1'b1) & (itlb_mr[`OR1200_ITLBMRW-1:1] === pc[`OR1200_ITLB_TAG]))
712 
                begin
713 
                   // Page number in match register matches page number of virtual PC, so get the physical
714 
                   // address from the translate memory
715 
                   // Now pull the physical page number out of the tranlsate register (it's after bottom 3 bits)
716 
                   physical_pc = {itlb_tr[`OR1200_ITLBTRW-1:`OR1200_ITLBTRW-(32-`OR1200_IMMU_PS)],pc[`OR1200_IMMU_PS-1:0]};
717 
                   //$display("check_for_immu_entry: found match for virtual PC 0x%h in entry %d of iMMU, mr = 0x%x tr = 0x%x, phys. PC = 0x%h", pc, pc[`OR1200_ITLB_INDX], itlb_mr, itlb_tr, physical_pc);
718 
                end // if ((itlb_mr[`OR1200_ITLBMR_V_BITS]) & (itlb_mr[`OR1200_ITLBMRW-1:1] == pc[`OR1200_ITLB_TAG]))
719 
              else
720 
                begin
721 
 
722 
                   // Wait a couple of clocks, see if we're doing a miss
723 
                   @(posedge `CPU_CORE_CLK);
724 
                   @(posedge `CPU_CORE_CLK);
725 
                   if (!(`OR1200_TOP.`CPU_immu_top.miss)) // MMU should indicate miss
726 
                     begin
727 
                        $display("%t: check_for_immu_entry - ERROR - no match found for virtual PC 0x%h in entry %d of iMMU, mr = 0x%x tr = 0x%x, and no miss generated",
728 
                                 $time, pc, pc[`OR1200_ITLB_INDX], itlb_mr, itlb_tr);
729 
                        #100;
730 
                        $finish;
731 
                     end
732 
                   else
733 
                     begin
734 
                        mmu_tlb_miss = 1; // Started a miss, so ignore this instruction
735 
                     end
736 
                end // else: !if((itlb_mr[`OR1200_ITLBMR_V_BITS]) & (itlb_mr[`OR1200_ITLBMRW-1:1] == pc[`OR1200_ITLB_TAG]))
737 
 
738 
           end // if (`OR1200_TOP.`CPU_immu_top.immu_en === 1'b1)
739 
         else
740 
           physical_pc = pc;
741 
`endif // !`ifdef OR1200_NO_IMMU
742 
      end
743 
   endtask // check_for_immu_entry
744 
 
745 
 
746 
   /*
747 
    Instruction memory coherence checking.
748 
 
749 
    For new instruction executed in the pipeline - ensure it matches
750 
    what is in the main program memory. Perform MMU translations if
751 
    it is enabled.
752 
    */
753 
 
754 
   reg [31:0] mem_word;
755 348 julius 
   reg [31:0] last_addr = 0;
756 
   reg [31:0] last_mem_word;
757 449 julius 
   reg [31:0] physical_pc;
758 
   reg        tlb_miss;
759 
 
760 348 julius 
 
761 415 julius 
`ifdef MEM_COHERENCE_CHECK
762 
 `define MEM_COHERENCE_TRIGGER (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_void === 1'b0)
763 
 
764 449 julius 
 `define INSN_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn
765 
 `define PC_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_except.id_pc
766 348 julius 
 
767 
   // Check instruction in decode stage is what is in the RAM
768 449 julius 
   always @(posedge `CPU_CORE_CLK)
769 348 julius 
     begin
770 415 julius 
        if (`MEM_COHERENCE_TRIGGER)
771 348 julius 
          begin
772 449 julius 
 
773 
             check_for_immu_entry(`PC_TO_CHECK, physical_pc, tlb_miss);
774 
 
775 348 julius 
             // Check if it's a new PC - will also get triggered if the
776 
             // instruction has changed since we last checked it
777 449 julius 
             if (((physical_pc !== last_addr) || (last_mem_word != `INSN_TO_CHECK))
778 
                 & !tlb_miss)
779 348 julius 
               begin
780 
                  // Decode stage not void, check instruction
781 
                  // get PC
782 449 julius 
                  get_insn_from_memory(physical_pc, mem_word);
783 348 julius 
 
784 
                  if (mem_word !== `INSN_TO_CHECK)
785 
                    begin
786 449 julius 
                       $fdisplay(fgeneral, "%t: Instruction mismatch for PC 0x%h (phys. 0x%h) - memory had 0x%h, CPU had 0x%h", $time, `PC_TO_CHECK, physical_pc, mem_word, `INSN_TO_CHECK);
787 
                       $display("%t: Instruction mismatch for PC 0x%h (phys. 0x%h) - memory had 0x%h, CPU had 0x%h", $time, `PC_TO_CHECK, physical_pc, mem_word, `INSN_TO_CHECK);
788 
                       #200
789 348 julius 
                         $finish;
790 
                    end
791 449 julius 
                  last_addr = physical_pc;
792 
                  last_mem_word = mem_word;
793 
 
794 
               end // if (((physical_pc !== last_addr) || (last_mem_word != `INSN_TO_CHECK))...
795 
          end // if (`MEM_COHERENCE_TRIGGER)
796 
     end // always @ (posedge `CPU_CORE_CLK)
797 
 
798 
`endif //  `ifdef MEM_COHERENCE_CHECK
799 
 
800 
   // Trigger on each instruction that gets into writeback stage properly
801 
   reg exception_coming1, exception_coming2, exception_here;
802 
   reg will_jump, jumping, jump_dslot, jumped;
803 
   reg rfe, except_during_rfe;
804 
   reg dslot_expt;
805 
 
806 
 
807 
   // Maintain a copy of GPRS for previous instruction
808 
   reg [31:0] current_gprs [0:31];
809 
   reg [31:0] current_epcr, current_eear, current_esr, current_sr;
810 
   reg [31:0] previous_gprs [0:31];
811 
   reg [31:0] previous_epcr;
812 
   reg [31:0] previous_eear;
813 
   reg [31:0] previous_esr;
814 
   reg [31:0] previous_sr;
815 
 
816 
   task update_current_gprs;
817 
      integer j;
818 
      begin
819 
         for(j=0;j<32;j=j+1)
820 
           begin
821 
              get_gpr(j,current_gprs[j]);
822 
           end
823 
         current_sr = `OR1200_TOP.`CPU_cpu.or1200_sprs.sr ;
824 
         current_esr = `OR1200_TOP.`CPU_cpu.or1200_sprs.epcr ;
825 
         current_epcr = `OR1200_TOP.`CPU_cpu.or1200_sprs.epcr ;
826 
         current_eear = `OR1200_TOP.`CPU_cpu.or1200_sprs.eear ;
827 
      end
828 
   endtask
829 
 
830 
   task update_previous_gprs;
831 
      integer j;
832 
      begin
833 
         for(j=0;j<32;j=j+1)
834 
           begin
835 
              previous_gprs[j] = current_gprs[j];
836 
           end
837 
         previous_sr = current_sr;
838 
         previous_esr = current_esr;
839 
         previous_epcr = current_epcr;
840 
         previous_eear = current_eear;
841 
      end
842 
   endtask // update_previous_gprs
843 
 
844 
   // Maintain a list of addresses we expect the processor to execute
845 
   // Whenever we hit a branch or jump or rfe we add to this list - when we
846 
   // execute it then we remove it from the list.
847 
   reg [31:0] expected_addresses [0:31];
848 
   reg        expected_addresses_waiting [0:31]; // List indicating if address is waiting
849 
   reg        duplicate_expected_addresses_waiting [0:31]; // List indicating if a waiting address will be cleared by the single return
850 
   integer    expected_address_num;
851 
   // Initialise things on reset
852 
   always @(`OR1200_TOP.iwb_rst_i)
853 
     begin
854 
        for (expected_address_num=0;expected_address_num<32;expected_address_num=expected_address_num+1)
855 
          begin
856 
             expected_addresses_waiting[expected_address_num] = 0;
857 
             duplicate_expected_addresses_waiting[expected_address_num] = 0;
858 348 julius 
          end
859 449 julius 
        expected_address_num = 0;
860 
     end
861 
 
862 
   task add_expected_address;
863 
      input [31:0] expected_pc;
864 
      begin
865 
         if (expected_address_num == 31)
866 
           begin
867 
              $display("%t: Too many branches not reached",$time);
868 
              #100;
869 
              $finish;
870 
           end
871 
         if (expected_addresses_waiting[expected_address_num])
872 
           begin
873 
              $display("%t: expected_addresses tracker bugged out. expected_address_num = %0d",$time,expected_address_num);
874 
              #100;
875 
              $finish;
876 
           end
877 
         else
878 
           begin
879 
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
880 
              // Debugging output...
881 
              $display("%t: Adding address 0x%h to expected list index %0d",$time, expected_pc,expected_address_num);
882 
`endif
883 
              // Put the expected PC in the list, increase the index
884 
              expected_addresses[expected_address_num] = expected_pc;
885 
              expected_addresses_waiting[expected_address_num] = 1;
886 
              expected_address_num = expected_address_num + 1;
887 
           end // else: !if(expected_addresses_waiting[expected_address_num])
888 
      end
889 
   endtask // add_address_to_expect
890 
 
891 
   // Use this in the case that there's an execption after a jump, in which
892 
   // case we'll have two entries when we finally jump back (the one the
893 
   // original jump put in, and the one put in by the l.rfe or l.jr/ when
894 
   // returning outside of exception handler), so mark this one as OK for
895 
   // removing the duplicate of
896 
   task mark_duplicate_expected_address;
897 
      begin
898 
         // This will always be done on the first instruction of an exception
899 
         // that has occured after a delay slot instruction, so
900 
         // expected_address_num will be one past the entry for the one we will
901 
         // get a duplicate return call for
902 
         duplicate_expected_addresses_waiting[expected_address_num-1] = 1;
903 
      end
904 
   endtask // mark_duplicate_expected_address
905 
 
906 
 
907 
   task check_expected_address;
908 
      input [31:0] pc;
909 
      input        expecting_hit;
910 
      integer      i,j;
911 
      reg          hit;
912 
      reg          duplicates;
913 348 julius 
 
914 449 julius 
      begin
915 
         hit = 0;
916 
         //$display("%t: check_expected_addr 0x%h, index %0d",
917 
         // $time,pc, expected_address_num);
918 
         if (expected_address_num > 0)
919 
           begin
920 
              // First check the last jump we did
921 
              if (expected_addresses[expected_address_num-1] == pc)
922 
                begin
923 
                   // Jump address hit
924 
                   // Debugging printout:
925 
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
926 
                   $display("%t: PC address 0x%h was in expected list, index %0d",$time, pc,expected_address_num-1);
927 
`endif
928 
                   expected_address_num = expected_address_num-1;
929 
                   expected_addresses_waiting[expected_address_num] = 0;
930 
                   hit = 1;
931 
                end
932 
              else
933 
                begin
934 
                   // Check through the list
935 
                   for(i=0;i<expected_address_num;i=i+1)
936 
                     begin
937 
                        if (expected_addresses[i] == pc)
938 
                          begin
939 
                             // Jump address hit
940 
                             // Debugging printout:
941 
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
942 
                             $display("%t: PC address 0x%h was in expected list, index %0d",$time, pc,i);
943 
`endif
944 
                             for(j=i;j<expected_address_num;j=j+1)
945 
                               begin
946 
                                  // Pull all of the ones above us down one
947 
                                  expected_addresses_waiting[j]
948 
                                    = expected_addresses_waiting[j+1];
949 
                                  expected_addresses[j]
950 
                                    = expected_addresses[j+1];
951 
                                  duplicate_expected_addresses_waiting[j]
952 
                                    = duplicate_expected_addresses_waiting[j+1];
953 
                               end
954 
                             expected_address_num = expected_address_num-1;
955 
                             hit = 1;
956 
                             // quit out. only allow 1 hit
957 
                             i = expected_address_num;
958 
                          end
959 
                     end
960 
                end // else: !if(expected_addresses[expected_ad...
961 
           end // if (expected_address_num > 0)
962 348 julius 
 
963 449 julius 
         // Check for duplicates this way because of the way we've declared
964 
         // the array...
965 
         duplicates=0;
966 
         for(i=0;i<32;i=i+1)
967 
           duplicates = duplicates | duplicate_expected_addresses_waiting[i];
968 
 
969 
         if (hit & duplicates)
970 
           begin
971 
              // If we got a hit, check for duplicates we're also meant to clear
972 
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
973 
              $display;
974 
`endif
975 
              for(i=0;i<expected_address_num;i=i+1)
976 
                begin
977 
                   if(duplicate_expected_addresses_waiting[i] &
978 
                      expected_addresses_waiting[i] &
979 
                      expected_addresses[i] == pc)
980 
                     begin
981 
                        // Found a duplicate call address, clear it
982 
                        duplicate_expected_addresses_waiting[i] = 0;
983 
                        expected_addresses_waiting[i] = 0;
984 
 
985 
                        // Now reorder the list - pull all the ones above us
986 
                        // down by one
987 
                        for(j=i;j<expected_address_num;j=j+1)
988 
                          begin
989 
                             expected_addresses_waiting[j] = expected_addresses_waiting[j+1];
990 
                             expected_addresses[j] = expected_addresses[j+1];
991 
                             duplicate_expected_addresses_waiting[j] = duplicate_expected_addresses_waiting[j+1];
992 
                          end
993 
                        expected_address_num = expected_address_num - 1;
994 
                     end
995 
                end // for (i=0;i<expected_address_num;i=i+1)
996 
           end // if (hit & duplicates)
997 
 
998 
         if (expecting_hit & !hit)
999 
           begin
1000 
              // Expected this address to be one we're supposed to jump to, but it wasn't!
1001 
              $display("%t: Failed to find current PC, 0x%h, in expected PCs for branches/jumps",$time,pc);
1002 
              #100;
1003 
              $finish;
1004 
           end
1005 
 
1006 
      end
1007 
   endtask // check_expected_address
1008 
 
1009 
   // Task to assert value of GPR
1010 
   task assert_gpr_val;
1011 
      input [5:0] regnum;
1012 
      input [31:0] assert_value;
1013 
      input [31:0] pc;
1014 
      reg [31:0]   reg_val;
1015 
 
1016 
      begin
1017 
         get_gpr(regnum, reg_val);
1018 
         if (reg_val !== assert_value)
1019 
           begin
1020 
              $display("%t: Assert r%0d value (0x%h) = 0x%h failed. pc=0x%h",
1021 
                       $time, regnum, reg_val, assert_value,pc);
1022 
              #100;
1023 
              $finish;
1024 
           end
1025 
      end
1026 
   endtask // assert_gpr_val
1027 
 
1028 
   // Task to assert something is true
1029 
   task assert_this;
1030 
      input assert_result;
1031 
      input [31:0] pc;
1032 
      begin
1033 
         if (!assert_result)
1034 
           begin
1035 
              $display("%t: Assert failed for instruction at pc=0x%h",
1036 
                       $time , pc);
1037 
              #100;
1038 
              $finish;
1039 
           end
1040 
      end
1041 
   endtask // assert_gpr_val
1042 
 
1043 
   // The jumping variable doesn't get updated until we do the proper check of
1044 
   // the current instruction reaching the writeback stage. We need to know
1045 
   // earlier, eg. in the exception checking part, if this instruction will
1046 
   // jump. We do that with this task.
1047 
   task check_for_jump;
1048 
      input [31:0] insn;
1049 
      reg [5:0]    opcode;
1050 
      reg          flag;
1051 
      begin
1052 
         opcode = insn[`OR1K_OPCODE_POS];
1053 
         // Use the flag from the previous instruction, as the decision
1054 
         // is made in the execute stage not in te writeback stage,
1055 
         // which is where we're getting our instructions.
1056 
         flag = previous_sr[`OR1200_SR_F];
1057 
 
1058 
         case (opcode)
1059 
           `OR1200_OR32_J,
1060 
             `OR1200_OR32_JR,
1061 
             `OR1200_OR32_JAL,
1062 
             `OR1200_OR32_JALR:
1063 
               will_jump = 1;
1064 
           `OR1200_OR32_BNF:
1065 
             will_jump = !flag;
1066 
           `OR1200_OR32_BF:
1067 
             will_jump = flag;
1068 
           default:
1069 
             will_jump = 0;
1070 
         endcase // case (opcode)
1071 
      end
1072 
   endtask // check_for_jump
1073 
 
1074 
 
1075 
 
1076 
   // Detect exceptions from the processor here
1077 
   reg [13:0] except_trig_r;
1078 
   reg        exception_coming;
1079 
 
1080 
   always @(posedge `CPU_CORE_CLK)
1081 
     if (`OR1200_TOP.iwb_rst_i)
1082 
       begin
1083 
          except_trig_r = 0;
1084 
          exception_coming = 0;
1085 
          except_during_rfe = 0;
1086 
       end
1087 
     else if ((|`OR1200_TOP.`CPU_cpu.`CPU_except.except_trig) && !exception_coming)
1088 
       begin
1089 
          exception_coming  = 1;
1090 
          except_trig_r = `OR1200_TOP.`CPU_cpu.`CPU_except.except_trig;
1091 
          except_during_rfe = rfe;
1092 
       end
1093 
 
1094 
   task check_incoming_exceptions;
1095 
      begin
1096 
 
1097 
         // Exception timing  - depends on the trigger.
1098 
         // Appears to be:
1099 
         // tick timer - dslot - 1 instruction delay, else 2
1100 
         // tlb lookasides - 1 instruction for both
1101 
 
1102 
         casex (except_trig_r)
1103 
           13'b1_xxxx_xxxx_xxxx: begin
1104 
              //except_type <= #1 `OR1200_EXCEPT_TICK;
1105 
              exception_here = exception_coming2;
1106 
              exception_coming2 = jump_dslot ? exception_coming: exception_coming1 ;
1107 
              exception_coming1 = jump_dslot ? 0 : exception_coming;
1108 
           end
1109 
           13'b0_1xxx_xxxx_xxxx: begin
1110 
              //except_type <= #1 `OR1200_EXCEPT_INT;
1111 
              #1;
1112 
           end
1113 
           13'b0_01xx_xxxx_xxxx: begin
1114 
              //except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
1115 
              exception_here = exception_coming2;
1116 
              exception_coming2 = jump_dslot ? exception_coming : exception_coming1 ;
1117 
              exception_coming1 = jump_dslot ? 0 : exception_coming;
1118 
           end
1119 
           13'b0_001x_xxxx_xxxx: begin
1120 
              //except_type <= #1 `OR1200_EXCEPT_IPF;
1121 
              exception_here = exception_coming2;
1122 
              exception_coming2 = jump_dslot ? exception_coming : exception_coming1 ;
1123 
              exception_coming1 = jump_dslot ? 0 : exception_coming;
1124 
           end
1125 
           13'b0_0001_xxxx_xxxx: begin
1126 
              //except_type <= #1 `OR1200_EXCEPT_BUSERR;
1127 
              exception_here = exception_coming;
1128 
              exception_coming2 = 0;
1129 
              exception_coming1 = 0;
1130 
           end
1131 
           13'b0_0000_1xxx_xxxx: begin
1132 
              //except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
1133 
              if (will_jump)
1134 
                begin
1135 
                   // Writeback stage instruction will jump, and we have an
1136 
                   // illegal instruction in the decode/execute stage, which is
1137 
                   // the delay slot, so indicate the exception is coming...
1138 
                   exception_here = exception_coming2;
1139 
                   exception_coming2 = exception_coming;
1140 
                   exception_coming1 = 0;
1141 
                end
1142 
              else
1143 
                begin
1144 
                   exception_here = jump_dslot ?
1145 
                                    exception_coming2 : exception_coming;
1146 
                   exception_coming2 = jump_dslot ? exception_coming : 0;
1147 
                   exception_coming1 = 0;
1148 
                end
1149 
           end
1150 
           13'b0_0000_01xx_xxxx: begin
1151 
              //except_type <= #1 `OR1200_EXCEPT_ALIGN;
1152 
              if(will_jump)
1153 
                begin
1154 
                   exception_here = exception_coming2;
1155 
                   exception_coming2 = exception_coming;
1156 
                   exception_coming1 = 0;
1157 
                end
1158 
              else
1159 
                begin
1160 
                   exception_here =  (rfe) ? exception_coming : exception_coming2;
1161 
                   exception_coming2 = (rfe) ? 0 : exception_coming;
1162 
                   exception_coming1 = 0;
1163 
                end
1164 
           end
1165 
           13'b0_0000_001x_xxxx: begin
1166 
              //except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
1167 
              // Looks like except_trig goes high here after we check the
1168 
              // instruction before the itlb miss after a delay slot, so we
1169 
              // miss the dslot variable (it gets propegated before we call
1170 
              // this task) so we use the jumped variable here to see if we
1171 
              // are an exception after a delay slot
1172 
              //exception_here = (jumped | rfe) ? exception_coming : exception_coming2 ;
1173 
              //exception_coming2 = (jumped | rfe) ? 0 : exception_coming;
1174 
 
1175 
              exception_here = (jumped | rfe) ? exception_coming : exception_coming2 ;
1176 
              exception_coming2 = (jumped | rfe) ? 0 : exception_coming;
1177 
 
1178 
              exception_coming1 = 0;
1179 
           end
1180 
           13'b0_0000_0001_xxxx: begin
1181 
              //except_type <= #1 `OR1200_EXCEPT_DPF;
1182 
              if (jumped) begin // Jumped onto illegal instruction
1183 
                 exception_here = exception_coming ;
1184 
                 exception_coming2 = 0;
1185 
                 exception_coming1 = 0;
1186 
              end
1187 
              else begin
1188 
                 exception_here =  exception_coming2;
1189 
                 exception_coming2 = exception_coming;
1190 
                 exception_coming1 = 0;
1191 
              end
1192 
           end
1193 
           13'b0_0000_0000_1xxx: begin  // Data Bus Error
1194 
              //except_type <= #1 `OR1200_EXCEPT_BUSERR;
1195 
              exception_here = exception_coming2 ;
1196 
              exception_coming2 = exception_coming;
1197 
              exception_coming1 = 0;
1198 
           end
1199 
           13'b0_0000_0000_01xx: begin
1200 
              //except_type <= #1 `OR1200_EXCEPT_RANGE;
1201 
              #1;
1202 
           end
1203 
           13'b0_0000_0000_001x: begin
1204 
              // trap
1205 
              #1;
1206 
           end
1207 
           13'b0_0000_0000_0001: begin
1208 
              //except_type <= #1 `OR1200_EXCEPT_SYSCALL;
1209 
              exception_here = exception_coming2;
1210 
              exception_coming2 = jumped ? exception_coming: exception_coming1 ;
1211 
              exception_coming1 = jumped ? 0 : exception_coming;
1212 
           end
1213 
         endcase // casex (except_trig_r)
1214 
 
1215 
         exception_coming = 0;
1216 
         except_during_rfe = 0;
1217 
 
1218 
      end
1219 
   endtask // check_incoming_exceptions
1220 
 
1221 
 
1222 
 
1223 
 
1224 351 julius 
   /////////////////////////////////////////////////////////////////////////
1225 449 julius 
   // Execution tracking task
1226 351 julius 
   /////////////////////////////////////////////////////////////////////////
1227 348 julius 
 
1228 449 julius 
 
1229 
`ifdef OR1200_SYSTEM_CHECKER
1230 
   always @(posedge `CPU_CORE_CLK)
1231 
     begin
1232 
        if (`OR1200_TOP.iwb_rst_i)
1233 
          begin
1234 
             exception_coming1 = 0;exception_coming2 = 0;exception_here= 0;
1235 
             jumping = 0; jump_dslot = 0; jumped = 0;
1236 
             rfe = 0;
1237 
          end
1238 
        if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze) begin
1239 
           //#2 ;
1240 
           // If instruction isn't a l.nop with bit 16 set (implementation's
1241 
           // filler instruction in pipeline), and do not have an exception
1242 
           // signaled with a dslot instruction in the execute stage
1243 
           if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[`OR1K_OPCODE_POS] !=
1244 
                 `OR1200_OR32_NOP) || !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
1245 
               && !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &&
1246 
                    `OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot)) // and not except start
1247 
             begin
1248 351 julius 
 
1249 449 julius 
                // Propegate jump-tracking variables
1250 
                // If was exception in delay slot, we didn't actually jump
1251 
                // so don't set jumped in this case.
1252 
                jumped = exception_here ? 0 : jump_dslot;
1253 
                jump_dslot = jumping;
1254 
                jumping = 0;
1255 
                rfe = 0;
1256 
 
1257 
                // Now, check if current instruction will jump/branch, this is
1258 
                // needed by the exception checking code, sets will_jump=1
1259 
                check_for_jump(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
1260 
 
1261 
                // Now check if it's an exception this instruction
1262 
                check_incoming_exceptions;
1263 
 
1264 
                // Case where we just went to an exception after a jump, so we
1265 
                // mark the address we were meant to jump to as a place which will
1266 
                // have duplicate return entries in the expected address list
1267 
                if (exception_here & (jumped | jump_dslot))
1268 
                  begin
1269 
                     $display("%t: marked as jump address with exception (dup)"
1270 
                              ,$time);
1271 
                     mark_duplicate_expected_address;
1272 
                  end
1273 
 
1274 
                or1200_check_execution(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn,
1275 
                                       `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
1276 
                                       exception_here);
1277 
                //$write("%t: pc:0x%h\t",$time,
1278 
                //       `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc);
1279 
                // Decode the instruction, print it out
1280 
                //or1200_print_op(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
1281 
                //$write("\t exc:%0h dsl:%0h\n",exception_here,jump_dslot);
1282 
 
1283 
 
1284 
 
1285 
             end
1286 
        end // if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze)
1287 
     end // always @ (posedge `CPU_CORE_CLK)
1288 
`endif
1289 
 
1290 
 
1291 
   task or1200_check_execution;
1292 
      input [31:0] insn;
1293 
      input [31:0] pc;
1294 
      input        exception;
1295 
 
1296 
      reg [5:0]    opcode;
1297 
 
1298 
      reg [25:0]   j_imm;
1299 
      reg [25:0]   br_imm;
1300 
 
1301 
      reg [4:0]    rD_num, rA_num, rB_num;
1302 
      reg [31:0]   rD_val, rA_val, rB_val;
1303 
      reg [15:0]   imm_16bit;
1304 
 
1305 
      reg [15:0]   mtspr_imm;
1306 
 
1307 
      reg [3:0]    alu_op;
1308 
      reg [1:0]    shrot_op;
1309 
 
1310 
      reg [5:0]    shroti_imm;
1311 
 
1312 
      reg [5:0]    sf_op;
1313 
 
1314 
      reg [5:0]    xsync_op;
1315 
 
1316 
      reg          flag;
1317 
 
1318 
      reg [31:0]   br_j_ea; // Branch/jump effective address
1319 
 
1320 
 
1321 
      begin
1322 
 
1323 
         // Instruction opcode
1324 
         opcode = insn[`OR1K_OPCODE_POS];
1325 
         // Immediates for jump or branch instructions
1326 
         j_imm = insn[`OR1K_J_BR_IMM_POS];
1327 
         br_imm = insn[`OR1K_J_BR_IMM_POS];
1328 
         // Register numbers (D, A and B)
1329 
         rD_num = insn[`OR1K_RD_POS];
1330 
         rA_num = insn[`OR1K_RA_POS];
1331 
         rB_num = insn[`OR1K_RB_POS];
1332 
         // Bottom 16 bits when used as immediates in various instructions
1333 
         imm_16bit = insn[15:0];
1334 
         // 16-bit immediate for mtspr instructions
1335 
         mtspr_imm = {insn[25:21],insn[10:0]};
1336 
         // ALU op for ALU instructions
1337 
         alu_op = insn[`OR1K_ALU_OP_POS];
1338 
         // Shift-rotate op for SHROT ALU instructions
1339 
         shrot_op = insn[`OR1K_SHROT_OP_POS];
1340 
         shroti_imm = insn[`OR1K_SHROTI_IMM_POS];
1341 
 
1342 
         // Set flag op
1343 
         sf_op = insn[`OR1K_SF_OP];
1344 
 
1345 
         // Xsync/syscall/trap opcode
1346 
         xsync_op = insn[`OR1K_XSYNC_OP_POS];
1347 
 
1348 
         // Use the flag from the previous instruction, as the decision
1349 
         // is made in the execute stage not in te writeback stage,
1350 
         // which is where we're getting our instructions.
1351 
         flag = previous_sr[`OR1200_SR_F];
1352 
 
1353 
         update_current_gprs;
1354 
 
1355 
         // Check MSbit of the immediate, sign extend if set
1356 
         br_j_ea = j_imm[25] ? pc + {4'hf,j_imm,2'b00} :
1357 
                   pc + {4'h0,j_imm,2'b00};
1358 
 
1359 
         if (exception)
1360 
           begin
1361 
              $display("%t: exception - at 0x%x",$time, pc);
1362 
              // get epcr, put it in the addresses we expect to jump
1363 
              // back to
1364 
              // Maybe DON'T do this. Because maybe in linux things we
1365 
              // interrupt out of, we don't want to execute them again?
1366 
              //add_expected_address(current_epcr);
1367 
           end
1368 
 
1369 
 
1370 
         check_expected_address(pc, (jumped & !exception));
1371 
 
1372 
         rfe = 0;
1373 
 
1374 
         case (opcode)
1375 
           `OR1200_OR32_J:
1376 
             begin
1377 
                //
1378 
                // PC < - exts(Immediate < < 2) + JumpInsnAddr
1379 
                //
1380 
                //The immediate value is shifted left two bits, sign-extended
1381 
                // to program counter width, and then added to the address of
1382 
                // the jump instruction. The result is the effective address
1383 
                // of the jump. The program unconditionally jumps to EA with
1384 
                // a delay of one instruction.
1385 
 
1386 
                add_expected_address(br_j_ea);
1387 
 
1388 
                jumping = 1;
1389 
             end
1390 
           `OR1200_OR32_JAL:
1391 
             begin
1392 
                //
1393 
                //PC < - exts(Immediate < < 2) + JumpInsnAddr
1394 
                //LR < - DelayInsnAddr + 4
1395 
                //
1396 
                // Link reg is r9, check it is PC+8
1397 
                //
1398 
                add_expected_address(br_j_ea);
1399 
                assert_gpr_val(9, pc+8, pc);
1400 
                jumping = 1;    //
1401 
             end
1402 
           `OR1200_OR32_BNF:
1403 
             begin
1404 
                //EA < - exts(Immediate < < 2) + BranchInsnAddr
1405 
                //PC < - EA if SR[F] cleared
1406 
                if (!flag)
1407 
                  begin
1408 
                     add_expected_address(br_j_ea);
1409 
                     jumping = 1;
1410 
                  end
1411 
             end
1412 
           `OR1200_OR32_BF:
1413 
             begin
1414 
                //EA < - exts(Immediate < < 2) + BranchInsnAddr
1415 
                //PC < - EA if SR[F] set
1416 
                if (flag)
1417 
                  begin
1418 
                     add_expected_address(br_j_ea);
1419 
                     jumping = 1;
1420 
                  end
1421 
             end
1422 
           `OR1200_OR32_RFE:
1423 
             begin
1424 
                add_expected_address(current_epcr);
1425 
                // jumping variable keeps track of jumps/branches with delay
1426 
                // slot - there is none for l.rfe
1427 
                rfe = 1;
1428 
             end
1429 
           `OR1200_OR32_JR:
1430 
             begin
1431 
                //PC < - rB
1432 
                get_gpr(rB_num, rB_val);
1433 
                add_expected_address(rB_val);
1434 
                jumping = 1;
1435 
             end
1436 
           `OR1200_OR32_JALR:
1437 
             begin
1438 
                //PC < - rB
1439 
                //LR < - DelayInsnAddr + 4
1440 
                get_gpr(rB_num, rB_val);
1441 
                add_expected_address(rB_val);
1442 
                assert_gpr_val(9, pc+8, pc);
1443 
                jumping = 1;
1444 
             end
1445 
           /*
1446 
            `OR1200_OR32_LWZ,
1447 
            `OR1200_OR32_LBZ,
1448 
            `OR1200_OR32_LBS,
1449 
            `OR1200_OR32_LHZ,
1450 
            `OR1200_OR32_LHS,
1451 
            `OR1200_OR32_SW,
1452 
            `OR1200_OR32_SB,
1453 
            `OR1200_OR32_SH:
1454 
            begin
1455 
            // Should result in databus access if data cache disabled
1456 
            $display("%t: lsu instruction",$time);
1457 
end
1458 
 
1459 
            `OR1200_OR32_MFSPR,
1460 
            `OR1200_OR32_MTSPR:
1461 
            begin
1462 
            // Confirm RF values end up in the correct SPR
1463 
            $display("%t: mxspr",$time);
1464 
end
1465 
 
1466 
            `OR1200_OR32_MOVHI,
1467 
            `OR1200_OR32_ADDI,
1468 
            `OR1200_OR32_ADDIC,
1469 
            `OR1200_OR32_ANDI,
1470 
            `OR1200_OR32_ORI,
1471 
            `OR1200_OR32_XORI,
1472 
            `OR1200_OR32_MULI,
1473 
            `OR1200_OR32_ALU:
1474 
            begin
1475 
            // Double check operations done on RF and immediate values
1476 
            $display("%t: ALU op",$time);
1477 
end
1478 
 
1479 
            `OR1200_OR32_SH_ROTI:
1480 
            begin
1481 
            // Rotate according to immediate - maybe should be in ALU ops
1482 
            $display("%t: rotate op",$time);
1483 
end
1484 
 
1485 
            `OR1200_OR32_SFXXI,
1486 
            `OR1200_OR32_SFXX:
1487 
            begin
1488 
            // Set flag - do the check oursevles, check flag
1489 
            $display("%t: set flag op",$time);
1490 
end
1491 
 
1492 
            `OR1200_OR32_MACI,
1493 
            `OR1200_OR32_MACMSB:
1494 
            begin
1495 
            // Either, multiply signed and accumulate, l.mac
1496 
            // or multiply signed and subtract, l.msb
1497 
            $display("%t: MAC op",$time);
1498 
end
1499 
            */
1500 
 
1501 
           /*default:
1502 
            begin
1503 
            $display("%t: Unknown opcode 0x%h at pc 0x%x\n",
1504 
            $time,opcode, pc);
1505 
end
1506 
            */
1507 
         endcase // case (opcode)
1508 
 
1509 
         update_previous_gprs;
1510 
 
1511 
      end
1512 
   endtask // or1200_check_execution
1513 348 julius 
 
1514 351 julius 
 
1515 449 julius 
   /////////////////////////////////////////////////////////////////////////
1516 
   // Instruction decode task
1517 
   /////////////////////////////////////////////////////////////////////////
1518 351 julius 
 
1519 
   task or1200_print_op;
1520 
      input [31:0] insn;
1521 
 
1522 
      reg [5:0]    opcode;
1523 
 
1524 
      reg [25:0]   j_imm;
1525 
      reg [25:0]   br_imm;
1526 
 
1527 
      reg [4:0]    rD_num, rA_num, rB_num;
1528 
      reg [31:0]   rA_val, rB_val;
1529 
      reg [15:0]   imm_16bit;
1530 
      reg [10:0]   imm_split16bit;
1531 
 
1532 
      reg [3:0]    alu_op;
1533 
      reg [1:0]    shrot_op;
1534 
 
1535 
      reg [5:0]    shroti_imm;
1536 
 
1537 449 julius 
      reg [5:0]    sf_op;
1538 351 julius 
 
1539 449 julius 
      reg [5:0]    xsync_op;
1540 
 
1541 351 julius 
      begin
1542 
         // Instruction opcode
1543 449 julius 
         opcode = insn[`OR1K_OPCODE_POS];
1544 351 julius 
         // Immediates for jump or branch instructions
1545 449 julius 
         j_imm = insn[`OR1K_J_BR_IMM_POS];
1546 
         br_imm = insn[`OR1K_J_BR_IMM_POS];
1547 351 julius 
         // Register numbers (D, A and B)
1548 449 julius 
         rD_num = insn[`OR1K_RD_POS];
1549 
         rA_num = insn[`OR1K_RA_POS];
1550 
         rB_num = insn[`OR1K_RB_POS];
1551 351 julius 
         // Bottom 16 bits when used as immediates in various instructions
1552 
         imm_16bit = insn[15:0];
1553 
         // Bottom 11 bits used as immediates for l.sX instructions
1554 
 
1555 
         // Split 16-bit immediate for l.mtspr/l.sX instructions
1556 
         imm_split16bit = {insn[25:21],insn[10:0]};
1557 
         // ALU op for ALU instructions
1558 449 julius 
         alu_op = insn[`OR1K_ALU_OP_POS];
1559 351 julius 
         // Shift-rotate op for SHROT ALU instructions
1560 449 julius 
         shrot_op = insn[`OR1K_SHROT_OP_POS];
1561 
         shroti_imm = insn[`OR1K_SHROTI_IMM_POS];
1562 351 julius 
 
1563 
         // Set flag op
1564 449 julius 
         sf_op = insn[`OR1K_SF_OP];
1565 351 julius 
 
1566 449 julius 
         // Xsync/syscall/trap opcode
1567 
         xsync_op = insn[`OR1K_XSYNC_OP_POS];
1568 
 
1569 351 julius 
         case (opcode)
1570 
           `OR1200_OR32_J:
1571 
             begin
1572 449 julius 
                $fwrite(finsn,"l.j 0x%h", {j_imm,2'b00});
1573 351 julius 
             end
1574 
 
1575 
           `OR1200_OR32_JAL:
1576 
             begin
1577 449 julius 
                $fwrite(finsn,"l.jal 0x%h", {j_imm,2'b00});
1578 351 julius 
             end
1579 
 
1580 
           `OR1200_OR32_BNF:
1581 
             begin
1582 449 julius 
                $fwrite(finsn,"l.bnf 0x%h", {br_imm,2'b00});
1583 351 julius 
             end
1584 
 
1585 
           `OR1200_OR32_BF:
1586 
             begin
1587 449 julius 
                $fwrite(finsn,"l.bf 0x%h", {br_imm,2'b00});
1588 351 julius 
             end
1589 
 
1590 
           `OR1200_OR32_RFE:
1591 
             begin
1592 449 julius 
                $fwrite(finsn,"l.rfe");
1593 351 julius 
             end
1594 
 
1595 
           `OR1200_OR32_JR:
1596 
             begin
1597 449 julius 
                $fwrite(finsn,"l.jr r%0d",rB_num);
1598 351 julius 
             end
1599 
 
1600 
           `OR1200_OR32_JALR:
1601 
             begin
1602 449 julius 
                $fwrite(finsn,"l.jalr r%0d",rB_num);
1603 351 julius 
             end
1604 
 
1605 
           `OR1200_OR32_LWZ:
1606 
             begin
1607 449 julius 
                $fwrite(finsn,"l.lwz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1608 351 julius 
             end
1609 
 
1610 
           `OR1200_OR32_LBZ:
1611 
             begin
1612 449 julius 
                $fwrite(finsn,"l.lbz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1613 351 julius 
             end
1614 
 
1615 
           `OR1200_OR32_LBS:
1616 
             begin
1617 449 julius 
                $fwrite(finsn,"l.lbs r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1618 351 julius 
             end
1619 
 
1620 
           `OR1200_OR32_LHZ:
1621 
             begin
1622 449 julius 
                $fwrite(finsn,"l.lhz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1623 351 julius 
             end
1624 
 
1625 
           `OR1200_OR32_LHS:
1626 
             begin
1627 449 julius 
                $fwrite(finsn,"l.lhs r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1628 351 julius 
             end
1629 
 
1630 
           `OR1200_OR32_SW:
1631 
             begin
1632 449 julius 
                $fwrite(finsn,"l.sw 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
1633 351 julius 
             end
1634 
 
1635 
           `OR1200_OR32_SB:
1636 
             begin
1637 449 julius 
                $fwrite(finsn,"l.sb 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
1638 351 julius 
             end
1639 
 
1640 
           `OR1200_OR32_SH:
1641 
             begin
1642 449 julius 
                $fwrite(finsn,"l.sh 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
1643 351 julius 
             end
1644 
 
1645 
           `OR1200_OR32_MFSPR:
1646 
             begin
1647 449 julius 
                $fwrite(finsn,"l.mfspr r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit,);
1648 351 julius 
             end
1649 
 
1650 
           `OR1200_OR32_MTSPR:
1651 
             begin
1652 449 julius 
                $fwrite(finsn,"l.mtspr r%0d,r%0d,0x%h",rA_num,rB_num,imm_split16bit);
1653 351 julius 
             end
1654 
 
1655 
           `OR1200_OR32_MOVHI:
1656 
             begin
1657 
                if (!insn[16])
1658 449 julius 
                  $fwrite(finsn,"l.movhi r%0d,0x%h",rD_num,imm_16bit);
1659 351 julius 
                else
1660 449 julius 
                  $fwrite(finsn,"l.macrc r%0d",rD_num);
1661 351 julius 
             end
1662 
 
1663 
           `OR1200_OR32_ADDI:
1664 
             begin
1665 449 julius 
                $fwrite(finsn,"l.addi r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1666 351 julius 
             end
1667 
 
1668 
           `OR1200_OR32_ADDIC:
1669 
             begin
1670 449 julius 
                $fwrite(finsn,"l.addic r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1671 351 julius 
             end
1672 
 
1673 
           `OR1200_OR32_ANDI:
1674 
             begin
1675 449 julius 
                $fwrite(finsn,"l.andi r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1676 351 julius 
             end
1677 
 
1678 
           `OR1200_OR32_ORI:
1679 
             begin
1680 449 julius 
                $fwrite(finsn,"l.ori r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1681 351 julius 
             end
1682 
 
1683 
           `OR1200_OR32_XORI:
1684 
             begin
1685 449 julius 
                $fwrite(finsn,"l.xori r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1686 351 julius 
             end
1687 
 
1688 
           `OR1200_OR32_MULI:
1689 
             begin
1690 449 julius 
                $fwrite(finsn,"l.muli r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1691 351 julius 
             end
1692 
 
1693 
           `OR1200_OR32_ALU:
1694 
             begin
1695 
                case(alu_op)
1696 
                  `OR1200_ALUOP_ADD:
1697 449 julius 
                    $fwrite(finsn,"l.add ");
1698 351 julius 
                  `OR1200_ALUOP_ADDC:
1699 449 julius 
                    $fwrite(finsn,"l.addc ");
1700 351 julius 
                  `OR1200_ALUOP_SUB:
1701 449 julius 
                    $fwrite(finsn,"l.sub ");
1702 351 julius 
                  `OR1200_ALUOP_AND:
1703 449 julius 
                    $fwrite(finsn,"l.and ");
1704 351 julius 
                  `OR1200_ALUOP_OR:
1705 449 julius 
                    $fwrite(finsn,"l.or ");
1706 351 julius 
                  `OR1200_ALUOP_XOR:
1707 449 julius 
                    $fwrite(finsn,"l.xor ");
1708 351 julius 
                  `OR1200_ALUOP_MUL:
1709 449 julius 
                    $fwrite(finsn,"l.mul ");
1710 351 julius 
                  `OR1200_ALUOP_SHROT:
1711 
                    begin
1712 
                       case(shrot_op)
1713 
                         `OR1200_SHROTOP_SLL:
1714 449 julius 
                           $fwrite(finsn,"l.sll ");
1715 351 julius 
                         `OR1200_SHROTOP_SRL:
1716 449 julius 
                           $fwrite(finsn,"l.srl ");
1717 351 julius 
                         `OR1200_SHROTOP_SRA:
1718 449 julius 
                           $fwrite(finsn,"l.sra ");
1719 351 julius 
                         `OR1200_SHROTOP_ROR:
1720 449 julius 
                           $fwrite(finsn,"l.ror ");
1721 351 julius 
                       endcase // case (shrot_op)
1722 
                    end
1723 
                  `OR1200_ALUOP_DIV:
1724 449 julius 
                    $fwrite(finsn,"l.div ");
1725 351 julius 
                  `OR1200_ALUOP_DIVU:
1726 449 julius 
                    $fwrite(finsn,"l.divu ");
1727 351 julius 
                  `OR1200_ALUOP_CMOV:
1728 449 julius 
                    $fwrite(finsn,"l.cmov ");
1729 351 julius 
                endcase // case (alu_op)
1730 449 julius 
                $fwrite(finsn,"r%0d,r%0d,r%0d",rD_num,rA_num,rB_num);
1731 351 julius 
             end
1732 
 
1733 
           `OR1200_OR32_SH_ROTI:
1734 
             begin
1735 
                case(shrot_op)
1736 
                  `OR1200_SHROTOP_SLL:
1737 449 julius 
                    $fwrite(finsn,"l.slli ");
1738 351 julius 
                  `OR1200_SHROTOP_SRL:
1739 449 julius 
                    $fwrite(finsn,"l.srli ");
1740 351 julius 
                  `OR1200_SHROTOP_SRA:
1741 449 julius 
                    $fwrite(finsn,"l.srai ");
1742 351 julius 
                  `OR1200_SHROTOP_ROR:
1743 449 julius 
                    $fwrite(finsn,"l.rori ");
1744 351 julius 
                endcase // case (shrot_op)
1745 449 julius 
                $fwrite(finsn,"r%0d,r%0d,0x%h",rD_num,rA_num,shroti_imm);
1746 351 julius 
             end
1747 
 
1748 
           `OR1200_OR32_SFXXI:
1749 
             begin
1750 
                case(sf_op[2:0])
1751 
                  `OR1200_COP_SFEQ:
1752 449 julius 
                    $fwrite(finsn,"l.sfeqi ");
1753 351 julius 
                  `OR1200_COP_SFNE:
1754 449 julius 
                    $fwrite(finsn,"l.sfnei ");
1755 351 julius 
                  `OR1200_COP_SFGT:
1756 
                    begin
1757 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1758 449 julius 
                         $fwrite(finsn,"l.sfgtsi ");
1759 351 julius 
                       else
1760 449 julius 
                         $fwrite(finsn,"l.sfgtui ");
1761 351 julius 
                    end
1762 
                  `OR1200_COP_SFGE:
1763 
                    begin
1764 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1765 449 julius 
                         $fwrite(finsn,"l.sfgesi ");
1766 351 julius 
                       else
1767 449 julius 
                         $fwrite(finsn,"l.sfgeui ");
1768 351 julius 
                    end
1769 
                  `OR1200_COP_SFLT:
1770 
                    begin
1771 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1772 449 julius 
                         $fwrite(finsn,"l.sfltsi ");
1773 351 julius 
                       else
1774 449 julius 
                         $fwrite(finsn,"l.sfltui ");
1775 351 julius 
                    end
1776 
                  `OR1200_COP_SFLE:
1777 
                    begin
1778 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1779 449 julius 
                         $fwrite(finsn,"l.sflesi ");
1780 351 julius 
                       else
1781 449 julius 
                         $fwrite(finsn,"l.sfleui ");
1782 351 julius 
                    end
1783 
                endcase // case (sf_op[2:0])
1784 
 
1785 449 julius 
                $fwrite(finsn,"r%0d,0x%h",rA_num, imm_16bit);
1786 351 julius 
 
1787 
             end // case: `OR1200_OR32_SFXXI
1788 
 
1789 
           `OR1200_OR32_SFXX:
1790 
             begin
1791 
                case(sf_op[2:0])
1792 
                  `OR1200_COP_SFEQ:
1793 449 julius 
                    $fwrite(finsn,"l.sfeq ");
1794 351 julius 
                  `OR1200_COP_SFNE:
1795 449 julius 
                    $fwrite(finsn,"l.sfne ");
1796 351 julius 
                  `OR1200_COP_SFGT:
1797 
                    begin
1798 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1799 449 julius 
                         $fwrite(finsn,"l.sfgts ");
1800 351 julius 
                       else
1801 449 julius 
                         $fwrite(finsn,"l.sfgtu ");
1802 351 julius 
                    end
1803 
                  `OR1200_COP_SFGE:
1804 
                    begin
1805 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1806 449 julius 
                         $fwrite(finsn,"l.sfges ");
1807 351 julius 
                       else
1808 449 julius 
                         $fwrite(finsn,"l.sfgeu ");
1809 351 julius 
                    end
1810 
                  `OR1200_COP_SFLT:
1811 
                    begin
1812 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1813 449 julius 
                         $fwrite(finsn,"l.sflts ");
1814 351 julius 
                       else
1815 449 julius 
                         $fwrite(finsn,"l.sfltu ");
1816 351 julius 
                    end
1817 
                  `OR1200_COP_SFLE:
1818 
                    begin
1819 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1820 449 julius 
                         $fwrite(finsn,"l.sfles ");
1821 351 julius 
                       else
1822 449 julius 
                         $fwrite(finsn,"l.sfleu ");
1823 351 julius 
                    end
1824 
 
1825 
                endcase // case (sf_op[2:0])
1826 
 
1827 449 julius 
                $fwrite(finsn,"r%0d,r%0d",rA_num, rB_num);
1828 351 julius 
 
1829 
             end
1830 
 
1831 
           `OR1200_OR32_MACI:
1832 
             begin
1833 449 julius 
                $fwrite(finsn,"l.maci r%0d,0x%h",rA_num,imm_16bit);
1834 351 julius 
             end
1835 
 
1836 
           `OR1200_OR32_MACMSB:
1837 
             begin
1838 
                if(insn[3:0] == 4'h1)
1839 449 julius 
                  $fwrite(finsn,"l.mac ");
1840 351 julius 
                else if(insn[3:0] == 4'h2)
1841 449 julius 
                  $fwrite(finsn,"l.msb ");
1842 351 julius 
 
1843 449 julius 
                $fwrite(finsn,"r%0d,r%0d",rA_num,rB_num);
1844 351 julius 
             end
1845 
 
1846 
           `OR1200_OR32_NOP:
1847 
             begin
1848 449 julius 
                $fwrite(finsn,"l.nop 0x%0h",imm_16bit);
1849 351 julius 
             end
1850 
 
1851 
           `OR1200_OR32_XSYNC:
1852 
             begin
1853 
                case (xsync_op)
1854 
                  5'd0:
1855 449 julius 
                    $fwrite(finsn,"l.sys 0x%h",imm_16bit);
1856 351 julius 
                  5'd8:
1857 449 julius 
                    $fwrite(finsn,"l.trap 0x%h",imm_16bit);
1858 351 julius 
                  5'd16:
1859 449 julius 
                    $fwrite(finsn,"l.msync");
1860 351 julius 
                  5'd20:
1861 449 julius 
                    $fwrite(finsn,"l.psync");
1862 351 julius 
                  5'd24:
1863 449 julius 
                    $fwrite(finsn,"l.csync");
1864 351 julius 
                  default:
1865 
                    begin
1866 
                       $display("%t: Instruction with opcode 0x%h has bad specific type information: 0x%h",$time,opcode,insn);
1867 449 julius 
                       $fwrite(finsn,"%t: Instruction with opcode 0x%h has has bad specific type information: 0x%h",$time,opcode,insn);
1868 351 julius 
                    end
1869 
                endcase // case (xsync_op)
1870 
             end
1871 
 
1872 
           default:
1873 
             begin
1874 
                $display("%t: Unknown opcode 0x%h",$time,opcode);
1875 449 julius 
                $fwrite(finsn,"%t: Unknown opcode 0x%h",$time,opcode);
1876 351 julius 
             end
1877 
 
1878 
         endcase // case (opcode)
1879 
 
1880 
      end
1881 
   endtask // or1200_print_op
1882 
 
1883 
 
1884 
 
1885 6 julius 
endmodule

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