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1 6 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3 449 julius
////  or1200_monitor.v                                            ////
4 360 julius
////                                                              ////
5
////  OR1200 processor monitor module                             ////
6
////                                                              ////
7 449 julius
////  Author(s):                                                  ////
8
////      - Damjan Lampret, lampret@opencores.org                 ////
9
////      - Julius Baxter, julius@opencores.org                   ////
10
////                                                              ////
11 360 julius
//////////////////////////////////////////////////////////////////////
12
////                                                              ////
13 348 julius
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
14 6 julius
////                                                              ////
15
//// This source file may be used and distributed without         ////
16
//// restriction provided that this copyright statement is not    ////
17
//// removed from the file and that any derivative work contains  ////
18
//// the original copyright notice and the associated disclaimer. ////
19
////                                                              ////
20
//// This source file is free software; you can redistribute it   ////
21
//// and/or modify it under the terms of the GNU Lesser General   ////
22
//// Public License as published by the Free Software Foundation; ////
23
//// either version 2.1 of the License, or (at your option) any   ////
24
//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
27
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
28
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
29
//// PURPOSE.  See the GNU Lesser General Public License for more ////
30
//// details.                                                     ////
31
////                                                              ////
32
//// You should have received a copy of the GNU Lesser General    ////
33
//// Public License along with this source; if not, download it   ////
34
//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
36
//////////////////////////////////////////////////////////////////////
37 67 julius
 
38 55 julius
`include "timescale.v"
39 6 julius
`include "or1200_defines.v"
40 485 julius
`include "or1200_monitor_defines.v"
41 360 julius
`include "test-defines.v"
42 415 julius
 
43 449 julius
 
44 6 julius
module or1200_monitor;
45
 
46
   integer fexe;
47 449 julius
   integer finsn;
48
 
49 6 julius
   reg [23:0] ref;
50 397 julius
`ifdef OR1200_MONITOR_SPRS
51 6 julius
   integer    fspr;
52 397 julius
`endif
53 6 julius
   integer    fgeneral;
54 397 julius
`ifdef OR1200_MONITOR_LOOKUP
55 6 julius
   integer    flookup;
56 397 julius
`endif
57 6 julius
   integer    r3;
58
   integer    insns;
59
 
60 348 julius
 
61 6 julius
   //
62
   // Initialization
63
   //
64
   initial begin
65
      ref = 0;
66 397 julius
`ifdef OR1200_MONITOR_EXEC_STATE
67 360 julius
      fexe = $fopen({"../out/",`TEST_NAME_STRING,"-executed.log"});
68 449 julius
`endif
69
`ifdef OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
70
      finsn = fexe;
71 397 julius
`endif
72 6 julius
      $timeformat (-9, 2, " ns", 12);
73 397 julius
`ifdef OR1200_MONITOR_SPRS
74 360 julius
      fspr = $fopen({"../out/",`TEST_NAME_STRING,"-sprs.log"});
75 397 julius
`endif
76 360 julius
      fgeneral = $fopen({"../out/",`TEST_NAME_STRING,"-general.log"});
77 397 julius
`ifdef OR1200_MONITOR_LOOKUP
78 360 julius
      flookup = $fopen({"../out/",`TEST_NAME_STRING,"-lookup.log"});
79 397 julius
`endif
80 6 julius
      insns = 0;
81
 
82
   end
83
 
84
   //
85
   // Get GPR
86
   //
87
   task get_gpr;
88
      input     [4:0]    gpr_no;
89
      output [31:0]      gpr;
90
      integer           j;
91
      begin
92 348 julius
 
93 449 julius
`ifdef OR1200_RFRAM_GENERIC
94 6 julius
         for(j = 0; j < 32; j = j + 1) begin
95 348 julius
            gpr[j] = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no*32+j];
96 6 julius
         end
97 348 julius
 
98 449 julius
`else
99 348 julius
         //gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no];
100
         gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.get_gpr(gpr_no);
101
 
102 449 julius
`endif
103 6 julius
 
104 348 julius
 
105
      end
106
   endtask
107
 
108 6 julius
   //
109
   // Write state of the OR1200 registers into a file
110
   //
111
   // Limitation: only a small subset of register file RAMs
112
   // are supported
113
   //
114
   task display_arch_state;
115
      reg [5:0] i;
116
      reg [31:0] r;
117
      integer    j;
118
      begin
119 397 julius
`ifdef OR1200_MONITOR_EXEC_STATE
120 6 julius
         ref = ref + 1;
121 397 julius
 `ifdef OR1200_MONITOR_LOOKUP
122 6 julius
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
123 397 julius
 `endif
124 351 julius
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h", insns,
125
                 `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
126
                 `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
127 449 julius
 `ifdef OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
128 351 julius
         $fwrite(fexe,"\t");
129
         // Decode the instruction, print it out
130
         or1200_print_op(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
131
 `endif
132 6 julius
         for(i = 0; i < 32; i = i + 1) begin
133
            if (i % 4 == 0)
134
              $fdisplay(fexe);
135
            get_gpr(i, r);
136
            $fwrite(fexe, "GPR%d: %h  ", i, r);
137
         end
138
         $fdisplay(fexe);
139 348 julius
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
140 6 julius
         $fwrite(fexe, "SR   : %h  ", r);
141 348 julius
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
142 6 julius
         $fwrite(fexe, "EPCR0: %h  ", r);
143 348 julius
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
144 6 julius
         $fwrite(fexe, "EEAR0: %h  ", r);
145 348 julius
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
146 6 julius
         $fdisplay(fexe, "ESR0 : %h", r);
147 397 julius
`endif //  `ifdef OR1200_MONITOR_EXEC_STATE
148 348 julius
`ifdef OR1200_DISPLAY_EXECUTED
149
         ref = ref + 1;
150 397 julius
 `ifdef OR1200_MONITOR_LOOKUP
151 348 julius
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
152 397 julius
 `endif
153 348 julius
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
154 6 julius
`endif
155 348 julius
         insns = insns + 1;
156 449 julius
      end
157 6 julius
   endtask // display_arch_state
158
 
159
   /* Keep a trace buffer of the last lot of instructions and addresses
160
    * "executed",as read from the writeback stage, and cause a $finish if we hit
161
    * an instruction that is invalid, such as all zeros.
162
    * Currently, only breaks on an all zero instruction, but should probably be
163
    * made to break for anything with an X in it too. And of course ideally this
164
    * shouldn't be needed - but is handy if someone changes something and stops
165
    * the test continuing forever.
166
    */
167 49 julius
   integer num_nul_inst;
168
   initial num_nul_inst = 0;
169 449 julius
 
170 6 julius
   task monitor_for_crash;
171 348 julius
`define OR1200_MONITOR_CRASH_TRACE_SIZE 32
172
      //Trace buffer of 32 instructions
173
      reg [31:0] insn_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
174
      //Trace buffer of the addresses of those instructions
175
      reg [31:0] addr_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
176 449 julius
      integer    i;
177 6 julius
 
178 449 julius
      begin
179
         if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h00000000)
180
           num_nul_inst = num_nul_inst + 1;
181
         else
182
           num_nul_inst = 0; // Reset it
183 49 julius
 
184 449 julius
         if (num_nul_inst == 1000) // Sat a loop a bit too long...
185
           begin
186
              $fdisplay(fgeneral, "ERROR - no instruction at PC %h",
187
                        `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc);
188
              $fdisplay(fgeneral, "Crash trace: Last %d instructions: ",
189
                        `OR1200_MONITOR_CRASH_TRACE_SIZE);
190 6 julius
 
191 449 julius
              $fdisplay(fgeneral, "PC\t\tINSTR");
192
              for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
193
                 $fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);
194
              end
195 485 julius
              $display("*");
196
              $display("* or1200_monitor : OR1200 crash detected (suspected CPU PC corruption)");
197
              $display("*");
198
 
199 449 julius
              #100 $finish;
200
           end
201
         else
202
           begin
203
              for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
204
                 insn_trace[i] = insn_trace[i-1];
205
                 addr_trace[i] = addr_trace[i-1];
206
              end
207
              insn_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn;
208
              addr_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc;
209
           end
210
 
211
      end
212 6 julius
   endtask // monitor_for_crash
213 348 julius
 
214 6 julius
 
215 348 julius
   //
216
   // Write state of the OR1200 registers into a file; version for exception
217
   //
218
   task display_arch_state_except;
219
      reg [5:0] i;
220
      reg [31:0] r;
221
      integer    j;
222
      begin
223 397 julius
`ifdef OR1200_MONITOR_EXEC_STATE
224 348 julius
         ref = ref + 1;
225 397 julius
 `ifdef OR1200_MONITOR_LOOKUP
226 348 julius
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
227 397 julius
 `endif
228 348 julius
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h  (exception)", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
229
         for(i = 0; i < 32; i = i + 1) begin
230
            if (i % 4 == 0)
231
              $fdisplay(fexe);
232
            get_gpr(i, r);
233
            $fwrite(fexe, "GPR%d: %h  ", i, r);
234
         end
235
         $fdisplay(fexe);
236
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
237
         $fwrite(fexe, "SR   : %h  ", r);
238
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
239
         $fwrite(fexe, "EPCR0: %h  ", r);
240
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
241
         $fwrite(fexe, "EEAR0: %h  ", r);
242
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
243
         $fdisplay(fexe, "ESR0 : %h", r);
244
         insns = insns + 1;
245 397 julius
`endif //  `ifdef OR1200_MONITOR_EXEC_STATE
246 348 julius
`ifdef OR1200_DISPLAY_EXECUTED
247
         ref = ref + 1;
248 397 julius
 `ifdef OR1200_MONITOR_LOOKUP
249 348 julius
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
250 397 julius
 `endif
251 348 julius
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h  (exception)", insns,
252
                 `OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc,
253
                 `OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
254
         insns = insns + 1;
255
`endif
256
 
257 449 julius
      end
258 348 julius
   endtask
259
 
260 6 julius
   integer iwb_progress;
261
   reg [31:0] iwb_progress_addr;
262
   //
263
   // WISHBONE bus checker
264
   //
265
   always @(posedge `OR1200_TOP.iwb_clk_i)
266
     if (`OR1200_TOP.iwb_rst_i) begin
267
        iwb_progress = 0;
268
        iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
269
     end
270
     else begin
271
        if (`OR1200_TOP.iwb_cyc_o && (iwb_progress != 2)) begin
272
           iwb_progress = 1;
273
        end
274
        if (`OR1200_TOP.iwb_stb_o) begin
275
           if (iwb_progress >= 1) begin
276
              if (iwb_progress == 1)
277
                iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
278
              iwb_progress = 2;
279
           end
280
           else begin
281
              $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o raised without `OR1200_TOP.iwb_cyc_o, at %t\n", $time);
282
              #100 $finish;
283
           end
284
        end
285
        if (`OR1200_TOP.iwb_ack_i & `OR1200_TOP.iwb_err_i) begin
286
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i and `OR1200_TOP.iwb_err_i raised at the same time, at %t\n", $time);
287
        end
288
        if ((iwb_progress == 2) && (iwb_progress_addr != `OR1200_TOP.iwb_adr_o)) begin
289
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_adr_o changed while waiting for `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
290
           #100 $finish;
291
        end
292
        if (`OR1200_TOP.iwb_ack_i | `OR1200_TOP.iwb_err_i)
293
          if (iwb_progress == 2) begin
294
             iwb_progress = 0;
295
             iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
296
          end
297
          else begin
298
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
299
             #100 $finish;
300
          end
301
        if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
302
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
303 348 julius
           #100 $finish;
304 6 julius
        end
305
     end
306
 
307
   integer dwb_progress;
308 449 julius
   reg [31:0] dwb_progress_addr;
309
   //
310
   // WISHBONE bus checker
311
   //
312
   always @(posedge `OR1200_TOP.dwb_clk_i)
313
     if (`OR1200_TOP.dwb_rst_i)
314
       dwb_progress = 0;
315
     else begin
316
        if (`OR1200_TOP.dwb_cyc_o && (dwb_progress != 2))
317
          dwb_progress = 1;
318
        if (`OR1200_TOP.dwb_stb_o)
319
          if (dwb_progress >= 1) begin
320
             if (dwb_progress == 1)
321
               dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
322
             dwb_progress = 2;
323
          end
324
          else begin
325
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o raised without `OR1200_TOP.dwb_cyc_o, at %t\n", $time);
326
             #100 $finish;
327
          end
328
        if (`OR1200_TOP.dwb_ack_i & `OR1200_TOP.dwb_err_i) begin
329
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i and `OR1200_TOP.dwb_err_i raised at the same time, at %t\n", $time);
330
        end
331
        if ((dwb_progress == 2) && (dwb_progress_addr != `OR1200_TOP.dwb_adr_o)) begin
332
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_adr_o changed while waiting for `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
333
           #100 $finish;
334
        end
335
        if (`OR1200_TOP.dwb_ack_i | `OR1200_TOP.dwb_err_i)
336
          if (dwb_progress == 2) begin
337
             dwb_progress = 0;
338
             dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
339
          end
340
          else begin
341
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i/`OR1200_TOP.dwb_err_i raised without `OR1200_TOP.dwb_cyc_i/`OR1200_TOP.dwb_stb_i, at %t\n", $time);
342
             #100 $finish;
343
          end
344
        if ((dwb_progress == 2) && !`OR1200_TOP.dwb_stb_o) begin
345
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o lowered without `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
346
           #100 $finish;
347
        end
348 6 julius
     end
349
 
350 449 julius
   //
351
   // Hooks for:
352
   // - displaying registers
353
   // - end of simulation
354
   // - access to SPRs
355
   //
356
   always @(posedge `CPU_CORE_CLK)
357 348 julius
     if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze) begin
358 449 julius
        //      #2;
359 348 julius
        if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP)
360
             | !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
361
            & !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &
362
                `OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot))
363 6 julius
          begin
364
             display_arch_state;
365
             monitor_for_crash;
366
          end
367
        else
368 348 julius
          if (`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe)
369 6 julius
            display_arch_state_except;
370 348 julius
        // small hack to stop simulation (l.nop 1):
371
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
372 6 julius
           get_gpr(3, r3);
373
           $fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
374 456 julius
`ifdef OR1200_MONITOR_VERBOSE_NOPS
375 468 julius
           $display("exit(%h)",r3);
376 456 julius
`endif
377 6 julius
           $finish;
378
        end
379 348 julius
        // debug if test (l.nop 10)
380
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
381 6 julius
           $fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
382
        end
383 348 julius
        // simulation reports (l.nop 2)
384
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
385 6 julius
           get_gpr(3, r3);
386 468 julius
           $fdisplay(fgeneral, "%t: l.nop report (0x%h)", $time, r3);
387 456 julius
`ifdef OR1200_MONITOR_VERBOSE_NOPS
388 468 julius
           $display("report (0x%h);", r3);
389 456 julius
`endif
390 348 julius
        end
391
        // simulation printfs (l.nop 3)
392
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0003) begin
393
           get_gpr(3, r3);
394 6 julius
           $fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);
395
        end
396 348 julius
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0004) begin
397
           // simulation putc (l.nop 4)
398
           get_gpr(3, r3);
399
           $write("%c", r3);
400
           $fdisplay(fgeneral, "%t: l.nop putc (%c)", $time, r3);
401
        end
402 397 julius
`ifdef OR1200_MONITOR_SPRS
403
        if (`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
404 6 julius
          $fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
405 397 julius
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
406 348 julius
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_dat_o);
407 397 julius
        if ((|`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_cs) &
408
            !`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
409 6 julius
          $fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
410 348 julius
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
411
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.to_wbmux);
412 397 julius
`endif
413 6 julius
     end
414
 
415 348 julius
 
416 415 julius
`ifdef RAM_WB
417 439 julius
 `define RAM_WB_TOP `DUT_TOP.ram_wb0.ram_wb_b3_0
418 415 julius
   task get_insn_from_wb_ram;
419
      input [31:0] addr;
420
      output [31:0] insn;
421
      begin
422 477 julius
         insn = `RAM_WB_TOP.get_mem32(addr[31:2]);
423 415 julius
      end
424
   endtask // get_insn_from_wb_ram
425
`endif
426
 
427 348 julius
`ifdef VERSATILE_SDRAM
428 415 julius
 `define SDRAM_TOP `TB_TOP.sdram0
429 348 julius
   // Bit selects to define the bank
430
   // 32 MB part with 4 banks
431
 `define SDRAM_BANK_SEL_BITS 24:23
432
 `define SDRAM_WORD_SEL_TOP_BIT 22
433
   // Gets instruction word from correct bank
434
   task get_insn_from_sdram;
435
      input [31:0] addr;
436
      output [31:0] insn;
437
      reg [`SDRAM_WORD_SEL_TOP_BIT-1:0] word_addr;
438 449 julius
 
439 348 julius
      begin
440
         word_addr = addr[`SDRAM_WORD_SEL_TOP_BIT:2];
441
         if (addr[`SDRAM_BANK_SEL_BITS] == 2'b00)
442
           begin
443
 
444
              //$display("%t: get_insn_from_sdram bank0, word 0x%h, (%h and %h in SDRAM)", $time, word_addr, `SDRAM_TOP.Bank0[{word_addr,1'b0}], `SDRAM_TOP.Bank0[{word_addr,1'b1}]);         
445
              insn[15:0] = `SDRAM_TOP.Bank0[{word_addr,1'b1}];
446
              insn[31:16] = `SDRAM_TOP.Bank0[{word_addr,1'b0}];
447
           end
448
      end
449
 
450
   endtask // get_insn_from_sdram
451
`endif //  `ifdef VERSATILE_SDRAM
452
 
453
`ifdef XILINX_DDR2
454 415 julius
 `define DDR2_TOP `TB_TOP.gen_cs[0]
455 348 julius
   // Gets instruction word from correct bank
456
   task get_insn_from_xilinx_ddr2;
457
      input [31:0] addr;
458
      output [31:0] insn;
459 415 julius
      reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2,
460
                     ddr2_array_line3;
461 348 julius
      integer        word_in_line_num;
462
      begin
463 449 julius
         // Get our 4 128-bit chunks (8 half-words in each!! Confused yet?), 
464
         // 16 words total
465 348 julius
         `DDR2_TOP.gen[0].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line0);
466
         `DDR2_TOP.gen[1].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line1);
467
         `DDR2_TOP.gen[2].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line2);
468
         `DDR2_TOP.gen[3].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line3);
469
         case (addr[5:2])
470
           4'h0:
471
             begin
472
                insn[15:0] = ddr2_array_line0[15:0];
473
                insn[31:16] = ddr2_array_line1[15:0];
474
             end
475
           4'h1:
476
             begin
477
                insn[15:0] = ddr2_array_line2[15:0];
478
                insn[31:16] = ddr2_array_line3[15:0];
479
             end
480
           4'h2:
481
             begin
482
                insn[15:0] = ddr2_array_line0[31:16];
483
                insn[31:16] = ddr2_array_line1[31:16];
484
             end
485
           4'h3:
486
             begin
487
                insn[15:0] = ddr2_array_line2[31:16];
488
                insn[31:16] = ddr2_array_line3[31:16];
489
             end
490
           4'h4:
491
             begin
492
                insn[15:0] = ddr2_array_line0[47:32];
493
                insn[31:16] = ddr2_array_line1[47:32];
494
             end
495
           4'h5:
496
             begin
497
                insn[15:0] = ddr2_array_line2[47:32];
498
                insn[31:16] = ddr2_array_line3[47:32];
499
             end
500
           4'h6:
501
             begin
502
                insn[15:0] = ddr2_array_line0[63:48];
503
                insn[31:16] = ddr2_array_line1[63:48];
504
             end
505
           4'h7:
506
             begin
507
                insn[15:0] = ddr2_array_line2[63:48];
508
                insn[31:16] = ddr2_array_line3[63:48];
509
             end
510
           4'h8:
511
             begin
512
                insn[15:0] = ddr2_array_line0[79:64];
513
                insn[31:16] = ddr2_array_line1[79:64];
514
             end
515
           4'h9:
516
             begin
517
                insn[15:0] = ddr2_array_line2[79:64];
518
                insn[31:16] = ddr2_array_line3[79:64];
519
             end
520
           4'ha:
521
             begin
522
                insn[15:0] = ddr2_array_line0[95:80];
523
                insn[31:16] = ddr2_array_line1[95:80];
524
             end
525
           4'hb:
526
             begin
527
                insn[15:0] = ddr2_array_line2[95:80];
528
                insn[31:16] = ddr2_array_line3[95:80];
529
             end
530
           4'hc:
531
             begin
532
                insn[15:0] = ddr2_array_line0[111:96];
533
                insn[31:16] = ddr2_array_line1[111:96];
534
             end
535
           4'hd:
536
             begin
537
                insn[15:0] = ddr2_array_line2[111:96];
538
                insn[31:16] = ddr2_array_line3[111:96];
539
             end
540
           4'he:
541
             begin
542
                insn[15:0] = ddr2_array_line0[127:112];
543
                insn[31:16] = ddr2_array_line1[127:112];
544
             end
545
           4'hf:
546
             begin
547
                insn[15:0] = ddr2_array_line2[127:112];
548
                insn[31:16] = ddr2_array_line3[127:112];
549
             end
550
         endcase // case (addr[5:2])
551
      end
552
   endtask // get_insn_from_xilinx_ddr2
553
`endif
554
 
555
 
556
   task get_insn_from_memory;
557
      input [31:0] id_pc;
558
      output [31:0] insn;
559
      begin
560
         // do a decode of which server we should look in
561
         case (id_pc[31:28])
562
`ifdef VERSATILE_SDRAM
563
           4'h0:
564
             get_insn_from_sdram(id_pc, insn);
565
`endif
566
`ifdef XILINX_DDR2
567
           4'h0:
568
             get_insn_from_xilinx_ddr2(id_pc, insn);
569 415 julius
`endif
570
`ifdef RAM_WB
571
           4'h0:
572
             get_insn_from_wb_ram(id_pc, insn);
573
`endif
574 348 julius
           4'hf:
575
             // Flash isn't stored in a memory, it's an FSM so just skip/ignore
576
             insn = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn;
577
           default:
578
             begin
579
                $fdisplay(fgeneral, "%t: Unknown memory server for address 0x%h", $time,id_pc);
580
                insn = 32'hxxxxxxxx; // Unknown server
581
             end
582
         endcase // case (id_pc[31:28])
583
      end
584
   endtask // get_insn_from_memory
585
 
586
 
587 449 julius
   //
588
   // Look in the iMMU TLB MR for this address' page, if MMUs are on and enabled
589
   //
590
   task check_for_immu_entry;
591
      input [31:0] pc;
592
      output [31:0] physical_pc;
593
      output        mmu_tlb_miss;
594
      integer       w,x;
595
 
596
      reg [31:`OR1200_IMMU_PS] pc_vpn;
597
 
598
      reg [`OR1200_ITLBTRW-1:0] itlb_tr;
599
      reg [`OR1200_ITLBMRW-1:0] itlb_mr;
600
 
601
      integer                   tlb_index;
602
      reg                       mmu_en;
603
 
604
 
605
      begin
606
         mmu_tlb_miss = 0;
607
 
608
`ifdef OR1200_NO_IMMU
609
         physical_pc = pc;
610
`else
611
         mmu_en = `OR1200_TOP.`CPU_immu_top.immu_en;
612
         // If MMU is enabled
613
         if (mmu_en)
614
           begin
615
 
616
              // Look in the iTLB for mapping - get virtual page number
617
              pc_vpn = pc[31:`OR1200_IMMU_PS];
618
 
619
              tlb_index = pc[`OR1200_ITLB_INDX];
620
 
621
              // Look at the ITLB match register
622
              itlb_mr = `OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_mr_ram.mem[tlb_index];
623
 
624
              // Get the translate register here too, in case there's an error, we print it
625
              itlb_tr = `OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_tr_ram.mem[tlb_index];
626
 
627
              if ((itlb_mr[`OR1200_ITLBMR_V_BITS] === 1'b1) & (itlb_mr[`OR1200_ITLBMRW-1:1] === pc[`OR1200_ITLB_TAG]))
628
                begin
629
                   // Page number in match register matches page number of virtual PC, so get the physical
630
                   // address from the translate memory            
631
                   // Now pull the physical page number out of the tranlsate register (it's after bottom 3 bits)
632
                   physical_pc = {itlb_tr[`OR1200_ITLBTRW-1:`OR1200_ITLBTRW-(32-`OR1200_IMMU_PS)],pc[`OR1200_IMMU_PS-1:0]};
633
                   //$display("check_for_immu_entry: found match for virtual PC 0x%h in entry %d of iMMU, mr = 0x%x tr = 0x%x, phys. PC = 0x%h", pc, pc[`OR1200_ITLB_INDX], itlb_mr, itlb_tr, physical_pc);
634
                end // if ((itlb_mr[`OR1200_ITLBMR_V_BITS]) & (itlb_mr[`OR1200_ITLBMRW-1:1] == pc[`OR1200_ITLB_TAG]))
635
              else
636
                begin
637
 
638
                   // Wait a couple of clocks, see if we're doing a miss
639
                   @(posedge `CPU_CORE_CLK);
640
                   @(posedge `CPU_CORE_CLK);
641
                   if (!(`OR1200_TOP.`CPU_immu_top.miss)) // MMU should indicate miss
642
                     begin
643
                        $display("%t: check_for_immu_entry - ERROR - no match found for virtual PC 0x%h in entry %d of iMMU, mr = 0x%x tr = 0x%x, and no miss generated",
644
                                 $time, pc, pc[`OR1200_ITLB_INDX], itlb_mr, itlb_tr);
645
                        #100;
646
                        $finish;
647
                     end
648
                   else
649
                     begin
650
                        mmu_tlb_miss = 1; // Started a miss, so ignore this instruction
651
                     end
652
                end // else: !if((itlb_mr[`OR1200_ITLBMR_V_BITS]) & (itlb_mr[`OR1200_ITLBMRW-1:1] == pc[`OR1200_ITLB_TAG]))
653
 
654
           end // if (`OR1200_TOP.`CPU_immu_top.immu_en === 1'b1)
655
         else
656
           physical_pc = pc;
657
`endif // !`ifdef OR1200_NO_IMMU
658
      end
659
   endtask // check_for_immu_entry
660
 
661
 
662
   /*
663
    Instruction memory coherence checking.
664
 
665
    For new instruction executed in the pipeline - ensure it matches
666
    what is in the main program memory. Perform MMU translations if
667
    it is enabled.
668
    */
669
 
670
   reg [31:0] mem_word;
671 348 julius
   reg [31:0] last_addr = 0;
672
   reg [31:0] last_mem_word;
673 449 julius
   reg [31:0] physical_pc;
674
   reg        tlb_miss;
675
 
676 348 julius
 
677 415 julius
`ifdef MEM_COHERENCE_CHECK
678
 `define MEM_COHERENCE_TRIGGER (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_void === 1'b0)
679
 
680 449 julius
 `define INSN_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn
681
 `define PC_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_except.id_pc
682 348 julius
 
683
   // Check instruction in decode stage is what is in the RAM
684 449 julius
   always @(posedge `CPU_CORE_CLK)
685 348 julius
     begin
686 415 julius
        if (`MEM_COHERENCE_TRIGGER)
687 348 julius
          begin
688 449 julius
 
689
             check_for_immu_entry(`PC_TO_CHECK, physical_pc, tlb_miss);
690
 
691 348 julius
             // Check if it's a new PC - will also get triggered if the
692
             // instruction has changed since we last checked it
693 477 julius
             if (((physical_pc !== last_addr) ||
694
                  (last_mem_word != `INSN_TO_CHECK)) & !tlb_miss)
695 348 julius
               begin
696
                  // Decode stage not void, check instruction
697
                  // get PC
698 449 julius
                  get_insn_from_memory(physical_pc, mem_word);
699 348 julius
 
700
                  if (mem_word !== `INSN_TO_CHECK)
701
                    begin
702 477 julius
                       $fdisplay(fgeneral, "%t: Instruction mismatch for PC 0x%h (phys. 0x%h) - memory had 0x%h, CPU had 0x%h",
703
                                 $time, `PC_TO_CHECK, physical_pc, mem_word,
704
                                 `INSN_TO_CHECK);
705
                       $display("%t: Instruction mismatch for PC 0x%h (phys. 0x%h) - memory had 0x%h, CPU had 0x%h",
706
                                $time, `PC_TO_CHECK, physical_pc, mem_word,
707
                                `INSN_TO_CHECK);
708
                       #200;
709
                       $finish;
710 348 julius
                    end
711 449 julius
                  last_addr = physical_pc;
712
                  last_mem_word = mem_word;
713
 
714
               end // if (((physical_pc !== last_addr) || (last_mem_word != `INSN_TO_CHECK))...      
715
          end // if (`MEM_COHERENCE_TRIGGER)    
716
     end // always @ (posedge `CPU_CORE_CLK)
717
 
718
`endif //  `ifdef MEM_COHERENCE_CHECK
719
 
720
   // Trigger on each instruction that gets into writeback stage properly
721
   reg exception_coming1, exception_coming2, exception_here;
722
   reg will_jump, jumping, jump_dslot, jumped;
723
   reg rfe, except_during_rfe;
724
   reg dslot_expt;
725
 
726
 
727
   // Maintain a copy of GPRS for previous instruction
728
   reg [31:0] current_gprs [0:31];
729
   reg [31:0] current_epcr, current_eear, current_esr, current_sr;
730
   reg [31:0] previous_gprs [0:31];
731
   reg [31:0] previous_epcr;
732
   reg [31:0] previous_eear;
733
   reg [31:0] previous_esr;
734
   reg [31:0] previous_sr;
735
 
736
   task update_current_gprs;
737
      integer j;
738
      begin
739
         for(j=0;j<32;j=j+1)
740
           begin
741
              get_gpr(j,current_gprs[j]);
742
           end
743 491 julius
         current_sr = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr ;
744
         current_esr = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr ;
745
         current_epcr = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr ;
746
         current_eear = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear ;
747 449 julius
      end
748
   endtask
749
 
750
   task update_previous_gprs;
751
      integer j;
752
      begin
753
         for(j=0;j<32;j=j+1)
754
           begin
755
              previous_gprs[j] = current_gprs[j];
756
           end
757
         previous_sr = current_sr;
758
         previous_esr = current_esr;
759
         previous_epcr = current_epcr;
760
         previous_eear = current_eear;
761
      end
762
   endtask // update_previous_gprs
763
 
764
   // Maintain a list of addresses we expect the processor to execute
765
   // Whenever we hit a branch or jump or rfe we add to this list - when we
766
   // execute it then we remove it from the list.
767
   reg [31:0] expected_addresses [0:31];
768
   reg        expected_addresses_waiting [0:31]; // List indicating if address is waiting
769
   reg        duplicate_expected_addresses_waiting [0:31]; // List indicating if a waiting address will be cleared by the single return
770
   integer    expected_address_num;
771
   // Initialise things on reset
772
   always @(`OR1200_TOP.iwb_rst_i)
773
     begin
774
        for (expected_address_num=0;expected_address_num<32;expected_address_num=expected_address_num+1)
775
          begin
776
             expected_addresses_waiting[expected_address_num] = 0;
777
             duplicate_expected_addresses_waiting[expected_address_num] = 0;
778 348 julius
          end
779 449 julius
        expected_address_num = 0;
780
     end
781
 
782
   task add_expected_address;
783
      input [31:0] expected_pc;
784
      begin
785
         if (expected_address_num == 31)
786
           begin
787
              $display("%t: Too many branches not reached",$time);
788
              #100;
789
              $finish;
790
           end
791
         if (expected_addresses_waiting[expected_address_num])
792
           begin
793
              $display("%t: expected_addresses tracker bugged out. expected_address_num = %0d",$time,expected_address_num);
794
              #100;
795
              $finish;
796
           end
797
         else
798
           begin
799
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
800
              // Debugging output...
801
              $display("%t: Adding address 0x%h to expected list index %0d",$time, expected_pc,expected_address_num);
802
`endif
803
              // Put the expected PC in the list, increase the index
804
              expected_addresses[expected_address_num] = expected_pc;
805
              expected_addresses_waiting[expected_address_num] = 1;
806
              expected_address_num = expected_address_num + 1;
807
           end // else: !if(expected_addresses_waiting[expected_address_num])
808
      end
809
   endtask // add_address_to_expect
810
 
811
   // Use this in the case that there's an execption after a jump, in which 
812
   // case we'll have two entries when we finally jump back (the one the 
813
   // original jump put in, and the one put in by the l.rfe or l.jr/ when 
814
   // returning outside of exception handler), so mark this one as OK for 
815
   // removing the duplicate of
816
   task mark_duplicate_expected_address;
817
      begin
818
         // This will always be done on the first instruction of an exception 
819
         // that has occured after a delay slot instruction, so 
820
         // expected_address_num will be one past the entry for the one we will
821
         // get a duplicate return call for
822
         duplicate_expected_addresses_waiting[expected_address_num-1] = 1;
823
      end
824
   endtask // mark_duplicate_expected_address
825
 
826
 
827
   task check_expected_address;
828
      input [31:0] pc;
829
      input        expecting_hit;
830
      integer      i,j;
831
      reg          hit;
832
      reg          duplicates;
833 348 julius
 
834 449 julius
      begin
835
         hit = 0;
836
         //$display("%t: check_expected_addr 0x%h, index %0d",
837
         // $time,pc, expected_address_num);     
838
         if (expected_address_num > 0)
839
           begin
840
              // First check the last jump we did
841
              if (expected_addresses[expected_address_num-1] == pc)
842
                begin
843
                   // Jump address hit
844
                   // Debugging printout:
845
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
846
                   $display("%t: PC address 0x%h was in expected list, index %0d",$time, pc,expected_address_num-1);
847
`endif
848
                   expected_address_num = expected_address_num-1;
849
                   expected_addresses_waiting[expected_address_num] = 0;
850
                   hit = 1;
851
                end
852
              else
853
                begin
854
                   // Check through the list
855
                   for(i=0;i<expected_address_num;i=i+1)
856
                     begin
857
                        if (expected_addresses[i] == pc)
858
                          begin
859
                             // Jump address hit
860
                             // Debugging printout:
861
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
862
                             $display("%t: PC address 0x%h was in expected list, index %0d",$time, pc,i);
863
`endif
864
                             for(j=i;j<expected_address_num;j=j+1)
865
                               begin
866
                                  // Pull all of the ones above us down one
867
                                  expected_addresses_waiting[j]
868
                                    = expected_addresses_waiting[j+1];
869
                                  expected_addresses[j]
870
                                    = expected_addresses[j+1];
871
                                  duplicate_expected_addresses_waiting[j]
872
                                    = duplicate_expected_addresses_waiting[j+1];
873
                               end
874
                             expected_address_num = expected_address_num-1;
875
                             hit = 1;
876
                             // quit out. only allow 1 hit
877
                             i = expected_address_num;
878
                          end
879
                     end
880
                end // else: !if(expected_addresses[expected_ad...
881
           end // if (expected_address_num > 0)
882 348 julius
 
883 449 julius
         // Check for duplicates this way because of the way we've declared
884
         // the array...
885
         duplicates=0;
886
         for(i=0;i<32;i=i+1)
887
           duplicates = duplicates | duplicate_expected_addresses_waiting[i];
888
 
889
         if (hit & duplicates)
890
           begin
891
              // If we got a hit, check for duplicates we're also meant to clear
892
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
893
              $display;
894
`endif
895
              for(i=0;i<expected_address_num;i=i+1)
896
                begin
897
                   if(duplicate_expected_addresses_waiting[i] &
898
                      expected_addresses_waiting[i] &
899
                      expected_addresses[i] == pc)
900
                     begin
901
                        // Found a duplicate call address, clear it
902
                        duplicate_expected_addresses_waiting[i] = 0;
903
                        expected_addresses_waiting[i] = 0;
904
 
905
                        // Now reorder the list - pull all the ones above us
906
                        // down by one
907
                        for(j=i;j<expected_address_num;j=j+1)
908
                          begin
909
                             expected_addresses_waiting[j] = expected_addresses_waiting[j+1];
910
                             expected_addresses[j] = expected_addresses[j+1];
911
                             duplicate_expected_addresses_waiting[j] = duplicate_expected_addresses_waiting[j+1];
912
                          end
913
                        expected_address_num = expected_address_num - 1;
914
                     end
915
                end // for (i=0;i<expected_address_num;i=i+1)
916
           end // if (hit & duplicates)
917
 
918
         if (expecting_hit & !hit)
919
           begin
920
              // Expected this address to be one we're supposed to jump to, but it wasn't!
921
              $display("%t: Failed to find current PC, 0x%h, in expected PCs for branches/jumps",$time,pc);
922
              #100;
923
              $finish;
924
           end
925
 
926
      end
927
   endtask // check_expected_address
928
 
929
   // Task to assert value of GPR
930
   task assert_gpr_val;
931
      input [5:0] regnum;
932
      input [31:0] assert_value;
933
      input [31:0] pc;
934
      reg [31:0]   reg_val;
935
 
936
      begin
937
         get_gpr(regnum, reg_val);
938
         if (reg_val !== assert_value)
939
           begin
940
              $display("%t: Assert r%0d value (0x%h) = 0x%h failed. pc=0x%h",
941
                       $time, regnum, reg_val, assert_value,pc);
942
              #100;
943
              $finish;
944
           end
945
      end
946
   endtask // assert_gpr_val
947
 
948
   // Task to assert something is true
949
   task assert_this;
950
      input assert_result;
951
      input [31:0] pc;
952
      begin
953
         if (!assert_result)
954
           begin
955
              $display("%t: Assert failed for instruction at pc=0x%h",
956
                       $time , pc);
957
              #100;
958
              $finish;
959
           end
960
      end
961
   endtask // assert_gpr_val             
962
 
963
   // The jumping variable doesn't get updated until we do the proper check of
964
   // the current instruction reaching the writeback stage. We need to know
965
   // earlier, eg. in the exception checking part, if this instruction will
966
   // jump. We do that with this task.
967
   task check_for_jump;
968
      input [31:0] insn;
969
      reg [5:0]    opcode;
970
      reg          flag;
971
      begin
972
         opcode = insn[`OR1K_OPCODE_POS];
973
         // Use the flag from the previous instruction, as the decision 
974
         // is made in the execute stage not in te writeback stage, 
975
         // which is where we're getting our instructions.
976
         flag = previous_sr[`OR1200_SR_F];
977
 
978
         case (opcode)
979
           `OR1200_OR32_J,
980
             `OR1200_OR32_JR,
981
             `OR1200_OR32_JAL,
982
             `OR1200_OR32_JALR:
983
               will_jump = 1;
984
           `OR1200_OR32_BNF:
985
             will_jump = !flag;
986
           `OR1200_OR32_BF:
987
             will_jump = flag;
988
           default:
989
             will_jump = 0;
990
         endcase // case (opcode)
991
      end
992
   endtask // check_for_jump   
993
 
994
 
995
 
996
   // Detect exceptions from the processor here
997
   reg [13:0] except_trig_r;
998
   reg        exception_coming;
999
 
1000
   always @(posedge `CPU_CORE_CLK)
1001
     if (`OR1200_TOP.iwb_rst_i)
1002
       begin
1003
          except_trig_r = 0;
1004
          exception_coming = 0;
1005
          except_during_rfe = 0;
1006
       end
1007
     else if ((|`OR1200_TOP.`CPU_cpu.`CPU_except.except_trig) && !exception_coming)
1008
       begin
1009
          exception_coming  = 1;
1010
          except_trig_r = `OR1200_TOP.`CPU_cpu.`CPU_except.except_trig;
1011
          except_during_rfe = rfe;
1012
       end
1013
 
1014
   task check_incoming_exceptions;
1015
      begin
1016
 
1017
         // Exception timing  - depends on the trigger.
1018
         // Appears to be: 
1019
         // tick timer - dslot - 1 instruction delay, else 2
1020
         // tlb lookasides - 1 instruction for both
1021
 
1022
         casex (except_trig_r)
1023
           13'b1_xxxx_xxxx_xxxx: begin
1024
              //except_type <= #1 `OR1200_EXCEPT_TICK;
1025
              exception_here = exception_coming2;
1026
              exception_coming2 = jump_dslot ? exception_coming: exception_coming1 ;
1027
              exception_coming1 = jump_dslot ? 0 : exception_coming;
1028
           end
1029
           13'b0_1xxx_xxxx_xxxx: begin
1030
              //except_type <= #1 `OR1200_EXCEPT_INT;
1031
              #1;
1032
           end
1033
           13'b0_01xx_xxxx_xxxx: begin
1034
              //except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
1035
              exception_here = exception_coming2;
1036
              exception_coming2 = jump_dslot ? exception_coming : exception_coming1 ;
1037
              exception_coming1 = jump_dslot ? 0 : exception_coming;
1038
           end
1039
           13'b0_001x_xxxx_xxxx: begin
1040
              //except_type <= #1 `OR1200_EXCEPT_IPF;
1041
              exception_here = exception_coming2;
1042
              exception_coming2 = jump_dslot ? exception_coming : exception_coming1 ;
1043
              exception_coming1 = jump_dslot ? 0 : exception_coming;
1044
           end
1045
           13'b0_0001_xxxx_xxxx: begin
1046
              //except_type <= #1 `OR1200_EXCEPT_BUSERR;
1047
              exception_here = exception_coming;
1048
              exception_coming2 = 0;
1049
              exception_coming1 = 0;
1050
           end
1051
           13'b0_0000_1xxx_xxxx: begin
1052
              //except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
1053
              if (will_jump)
1054
                begin
1055
                   // Writeback stage instruction will jump, and we have an
1056
                   // illegal instruction in the decode/execute stage, which is
1057
                   // the delay slot, so indicate the exception is coming...
1058
                   exception_here = exception_coming2;
1059
                   exception_coming2 = exception_coming;
1060
                   exception_coming1 = 0;
1061
                end
1062
              else
1063
                begin
1064
                   exception_here = jump_dslot ?
1065
                                    exception_coming2 : exception_coming;
1066
                   exception_coming2 = jump_dslot ? exception_coming : 0;
1067
                   exception_coming1 = 0;
1068
                end
1069
           end
1070
           13'b0_0000_01xx_xxxx: begin
1071
              //except_type <= #1 `OR1200_EXCEPT_ALIGN;
1072
              if(will_jump)
1073
                begin
1074
                   exception_here = exception_coming2;
1075
                   exception_coming2 = exception_coming;
1076
                   exception_coming1 = 0;
1077
                end
1078
              else
1079
                begin
1080
                   exception_here =  (rfe) ? exception_coming : exception_coming2;
1081
                   exception_coming2 = (rfe) ? 0 : exception_coming;
1082
                   exception_coming1 = 0;
1083
                end
1084
           end
1085
           13'b0_0000_001x_xxxx: begin
1086
              //except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
1087
              // Looks like except_trig goes high here after we check the
1088
              // instruction before the itlb miss after a delay slot, so we
1089
              // miss the dslot variable (it gets propegated before we call
1090
              // this task) so we use the jumped variable here to see if we
1091
              // are an exception after a delay slot          
1092
              //exception_here = (jumped | rfe) ? exception_coming : exception_coming2 ;
1093
              //exception_coming2 = (jumped | rfe) ? 0 : exception_coming;
1094
 
1095
              exception_here = (jumped | rfe) ? exception_coming : exception_coming2 ;
1096
              exception_coming2 = (jumped | rfe) ? 0 : exception_coming;
1097
 
1098
              exception_coming1 = 0;
1099
           end
1100
           13'b0_0000_0001_xxxx: begin
1101
              //except_type <= #1 `OR1200_EXCEPT_DPF;
1102
              if (jumped) begin // Jumped onto illegal instruction
1103
                 exception_here = exception_coming ;
1104
                 exception_coming2 = 0;
1105
                 exception_coming1 = 0;
1106
              end
1107
              else begin
1108
                 exception_here =  exception_coming2;
1109
                 exception_coming2 = exception_coming;
1110
                 exception_coming1 = 0;
1111
              end
1112
           end
1113
           13'b0_0000_0000_1xxx: begin  // Data Bus Error
1114
              //except_type <= #1 `OR1200_EXCEPT_BUSERR;
1115
              exception_here = exception_coming2 ;
1116
              exception_coming2 = exception_coming;
1117
              exception_coming1 = 0;
1118
           end
1119
           13'b0_0000_0000_01xx: begin
1120
              //except_type <= #1 `OR1200_EXCEPT_RANGE;
1121
              #1;
1122
           end
1123
           13'b0_0000_0000_001x: begin
1124
              // trap         
1125
              #1;
1126
           end
1127
           13'b0_0000_0000_0001: begin
1128
              //except_type <= #1 `OR1200_EXCEPT_SYSCALL;
1129
              exception_here = exception_coming2;
1130
              exception_coming2 = jumped ? exception_coming: exception_coming1 ;
1131
              exception_coming1 = jumped ? 0 : exception_coming;
1132
           end
1133
         endcase // casex (except_trig_r)
1134
 
1135
         exception_coming = 0;
1136
         except_during_rfe = 0;
1137
 
1138
      end
1139
   endtask // check_incoming_exceptions
1140
 
1141
 
1142
 
1143
 
1144 351 julius
   /////////////////////////////////////////////////////////////////////////
1145 449 julius
   // Execution tracking task
1146 351 julius
   /////////////////////////////////////////////////////////////////////////
1147 348 julius
 
1148 449 julius
 
1149
`ifdef OR1200_SYSTEM_CHECKER
1150
   always @(posedge `CPU_CORE_CLK)
1151
     begin
1152
        if (`OR1200_TOP.iwb_rst_i)
1153
          begin
1154
             exception_coming1 = 0;exception_coming2 = 0;exception_here= 0;
1155
             jumping = 0; jump_dslot = 0; jumped = 0;
1156
             rfe = 0;
1157
          end
1158
        if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze) begin
1159
           //#2 ;
1160
           // If instruction isn't a l.nop with bit 16 set (implementation's 
1161
           // filler instruction in pipeline), and do not have an exception 
1162
           // signaled with a dslot instruction in the execute stage
1163
           if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[`OR1K_OPCODE_POS] !=
1164
                 `OR1200_OR32_NOP) || !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
1165
               && !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &&
1166
                    `OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot)) // and not except start
1167
             begin
1168 351 julius
 
1169 449 julius
                // Propegate jump-tracking variables
1170
                // If was exception in delay slot, we didn't actually jump
1171
                // so don't set jumped in this case.
1172
                jumped = exception_here ? 0 : jump_dslot;
1173
                jump_dslot = jumping;
1174
                jumping = 0;
1175
                rfe = 0;
1176
 
1177
                // Now, check if current instruction will jump/branch, this is
1178
                // needed by the exception checking code, sets will_jump=1
1179
                check_for_jump(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
1180
 
1181
                // Now check if it's an exception this instruction
1182
                check_incoming_exceptions;
1183
 
1184
                // Case where we just went to an exception after a jump, so we 
1185
                // mark the address we were meant to jump to as a place which will
1186
                // have duplicate return entries in the expected address list
1187
                if (exception_here & (jumped | jump_dslot))
1188
                  begin
1189
                     $display("%t: marked as jump address with exception (dup)"
1190
                              ,$time);
1191
                     mark_duplicate_expected_address;
1192
                  end
1193
 
1194
                or1200_check_execution(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn,
1195
                                       `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
1196
                                       exception_here);
1197
                //$write("%t: pc:0x%h\t",$time,
1198
                //       `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc);
1199
                // Decode the instruction, print it out
1200
                //or1200_print_op(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn); 
1201
                //$write("\t exc:%0h dsl:%0h\n",exception_here,jump_dslot);
1202
 
1203
 
1204
 
1205
             end
1206
        end // if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze)
1207
     end // always @ (posedge `CPU_CORE_CLK)
1208
`endif
1209
 
1210
 
1211
   task or1200_check_execution;
1212
      input [31:0] insn;
1213
      input [31:0] pc;
1214
      input        exception;
1215
 
1216
      reg [5:0]    opcode;
1217
 
1218
      reg [25:0]   j_imm;
1219
      reg [25:0]   br_imm;
1220
 
1221
      reg [4:0]    rD_num, rA_num, rB_num;
1222
      reg [31:0]   rD_val, rA_val, rB_val;
1223
      reg [15:0]   imm_16bit;
1224
 
1225
      reg [15:0]   mtspr_imm;
1226
 
1227
      reg [3:0]    alu_op;
1228
      reg [1:0]    shrot_op;
1229
 
1230
      reg [5:0]    shroti_imm;
1231
 
1232
      reg [5:0]    sf_op;
1233
 
1234
      reg [5:0]    xsync_op;
1235
 
1236
      reg          flag;
1237
 
1238
      reg [31:0]   br_j_ea; // Branch/jump effective address
1239
 
1240
 
1241
      begin
1242
 
1243
         // Instruction opcode
1244
         opcode = insn[`OR1K_OPCODE_POS];
1245
         // Immediates for jump or branch instructions
1246
         j_imm = insn[`OR1K_J_BR_IMM_POS];
1247
         br_imm = insn[`OR1K_J_BR_IMM_POS];
1248
         // Register numbers (D, A and B)
1249
         rD_num = insn[`OR1K_RD_POS];
1250
         rA_num = insn[`OR1K_RA_POS];
1251
         rB_num = insn[`OR1K_RB_POS];
1252
         // Bottom 16 bits when used as immediates in various instructions
1253
         imm_16bit = insn[15:0];
1254
         // 16-bit immediate for mtspr instructions
1255
         mtspr_imm = {insn[25:21],insn[10:0]};
1256
         // ALU op for ALU instructions
1257
         alu_op = insn[`OR1K_ALU_OP_POS];
1258
         // Shift-rotate op for SHROT ALU instructions
1259
         shrot_op = insn[`OR1K_SHROT_OP_POS];
1260
         shroti_imm = insn[`OR1K_SHROTI_IMM_POS];
1261
 
1262
         // Set flag op
1263
         sf_op = insn[`OR1K_SF_OP];
1264
 
1265
         // Xsync/syscall/trap opcode
1266
         xsync_op = insn[`OR1K_XSYNC_OP_POS];
1267
 
1268
         // Use the flag from the previous instruction, as the decision 
1269
         // is made in the execute stage not in te writeback stage, 
1270
         // which is where we're getting our instructions.
1271
         flag = previous_sr[`OR1200_SR_F];
1272
 
1273
         update_current_gprs;
1274
 
1275
         // Check MSbit of the immediate, sign extend if set
1276
         br_j_ea = j_imm[25] ? pc + {4'hf,j_imm,2'b00} :
1277
                   pc + {4'h0,j_imm,2'b00};
1278
 
1279
         if (exception)
1280
           begin
1281
              $display("%t: exception - at 0x%x",$time, pc);
1282
              // get epcr, put it in the addresses we expect to jump
1283
              // back to
1284
              // Maybe DON'T do this. Because maybe in linux things we 
1285
              // interrupt out of, we don't want to execute them again?
1286
              //add_expected_address(current_epcr);
1287
           end
1288
 
1289
 
1290
         check_expected_address(pc, (jumped & !exception));
1291
 
1292
         rfe = 0;
1293
 
1294
         case (opcode)
1295
           `OR1200_OR32_J:
1296
             begin
1297
                //
1298
                // PC < - exts(Immediate < < 2) + JumpInsnAddr
1299
                //
1300
                //The immediate value is shifted left two bits, sign-extended 
1301
                // to program counter width, and then added to the address of 
1302
                // the jump instruction. The result is the effective address 
1303
                // of the jump. The program unconditionally jumps to EA with 
1304
                // a delay of one instruction.
1305
 
1306
                add_expected_address(br_j_ea);
1307
 
1308
                jumping = 1;
1309
             end
1310
           `OR1200_OR32_JAL:
1311
             begin
1312
                //
1313
                //PC < - exts(Immediate < < 2) + JumpInsnAddr
1314
                //LR < - DelayInsnAddr + 4
1315
                //
1316
                // Link reg is r9, check it is PC+8
1317
                //
1318
                add_expected_address(br_j_ea);
1319
                assert_gpr_val(9, pc+8, pc);
1320
                jumping = 1;    // 
1321
             end
1322
           `OR1200_OR32_BNF:
1323
             begin
1324
                //EA < - exts(Immediate < < 2) + BranchInsnAddr
1325
                //PC < - EA if SR[F] cleared
1326
                if (!flag)
1327
                  begin
1328
                     add_expected_address(br_j_ea);
1329
                     jumping = 1;
1330
                  end
1331
             end
1332
           `OR1200_OR32_BF:
1333
             begin
1334
                //EA < - exts(Immediate < < 2) + BranchInsnAddr
1335
                //PC < - EA if SR[F] set
1336
                if (flag)
1337
                  begin
1338
                     add_expected_address(br_j_ea);
1339
                     jumping = 1;
1340
                  end
1341
             end
1342
           `OR1200_OR32_RFE:
1343
             begin
1344
                add_expected_address(current_epcr);
1345
                // jumping variable keeps track of jumps/branches with delay 
1346
                // slot - there is none for l.rfe
1347
                rfe = 1;
1348
             end
1349
           `OR1200_OR32_JR:
1350
             begin
1351
                //PC < - rB
1352
                get_gpr(rB_num, rB_val);
1353
                add_expected_address(rB_val);
1354
                jumping = 1;
1355
             end
1356
           `OR1200_OR32_JALR:
1357
             begin
1358
                //PC < - rB
1359
                //LR < - DelayInsnAddr + 4
1360
                get_gpr(rB_num, rB_val);
1361
                add_expected_address(rB_val);
1362
                assert_gpr_val(9, pc+8, pc);
1363
                jumping = 1;
1364
             end
1365
           /*
1366
            `OR1200_OR32_LWZ,
1367
            `OR1200_OR32_LBZ,
1368
            `OR1200_OR32_LBS,
1369
            `OR1200_OR32_LHZ,
1370
            `OR1200_OR32_LHS,
1371
            `OR1200_OR32_SW,
1372
            `OR1200_OR32_SB,
1373
            `OR1200_OR32_SH:
1374
            begin
1375
            // Should result in databus access if data cache disabled
1376
            $display("%t: lsu instruction",$time);
1377
end
1378
 
1379
            `OR1200_OR32_MFSPR,
1380
            `OR1200_OR32_MTSPR:
1381
            begin
1382
            // Confirm RF values end up in the correct SPR
1383
            $display("%t: mxspr",$time);
1384
end
1385
 
1386
            `OR1200_OR32_MOVHI,
1387
            `OR1200_OR32_ADDI,
1388
            `OR1200_OR32_ADDIC,
1389
            `OR1200_OR32_ANDI,
1390
            `OR1200_OR32_ORI,
1391
            `OR1200_OR32_XORI,
1392
            `OR1200_OR32_MULI,
1393
            `OR1200_OR32_ALU:
1394
            begin
1395
            // Double check operations done on RF and immediate values
1396
            $display("%t: ALU op",$time);
1397
end
1398
 
1399
            `OR1200_OR32_SH_ROTI:
1400
            begin
1401
            // Rotate according to immediate - maybe should be in ALU ops
1402
            $display("%t: rotate op",$time);
1403
end
1404
 
1405
            `OR1200_OR32_SFXXI,
1406
            `OR1200_OR32_SFXX:
1407
            begin
1408
            // Set flag - do the check oursevles, check flag
1409
            $display("%t: set flag op",$time);
1410
end
1411
 
1412
            `OR1200_OR32_MACI,
1413
            `OR1200_OR32_MACMSB:
1414
            begin
1415
            // Either, multiply signed and accumulate, l.mac
1416
            // or multiply signed and subtract, l.msb
1417
            $display("%t: MAC op",$time);
1418
end
1419
            */
1420
 
1421
           /*default:
1422
            begin
1423
            $display("%t: Unknown opcode 0x%h at pc 0x%x\n",
1424
            $time,opcode, pc);
1425
end
1426
            */
1427
         endcase // case (opcode)
1428
 
1429
         update_previous_gprs;
1430
 
1431
      end
1432
   endtask // or1200_check_execution
1433 348 julius
 
1434 351 julius
 
1435 449 julius
   /////////////////////////////////////////////////////////////////////////
1436
   // Instruction decode task
1437
   /////////////////////////////////////////////////////////////////////////
1438 351 julius
 
1439
   task or1200_print_op;
1440
      input [31:0] insn;
1441
 
1442
      reg [5:0]    opcode;
1443
 
1444
      reg [25:0]   j_imm;
1445
      reg [25:0]   br_imm;
1446
 
1447
      reg [4:0]    rD_num, rA_num, rB_num;
1448
      reg [31:0]   rA_val, rB_val;
1449
      reg [15:0]   imm_16bit;
1450
      reg [10:0]   imm_split16bit;
1451
 
1452
      reg [3:0]    alu_op;
1453
      reg [1:0]    shrot_op;
1454
 
1455
      reg [5:0]    shroti_imm;
1456
 
1457 449 julius
      reg [5:0]    sf_op;
1458 351 julius
 
1459 449 julius
      reg [5:0]    xsync_op;
1460
 
1461 351 julius
      begin
1462
         // Instruction opcode
1463 449 julius
         opcode = insn[`OR1K_OPCODE_POS];
1464 351 julius
         // Immediates for jump or branch instructions
1465 449 julius
         j_imm = insn[`OR1K_J_BR_IMM_POS];
1466
         br_imm = insn[`OR1K_J_BR_IMM_POS];
1467 351 julius
         // Register numbers (D, A and B)
1468 449 julius
         rD_num = insn[`OR1K_RD_POS];
1469
         rA_num = insn[`OR1K_RA_POS];
1470
         rB_num = insn[`OR1K_RB_POS];
1471 351 julius
         // Bottom 16 bits when used as immediates in various instructions
1472
         imm_16bit = insn[15:0];
1473
         // Bottom 11 bits used as immediates for l.sX instructions
1474
 
1475
         // Split 16-bit immediate for l.mtspr/l.sX instructions
1476
         imm_split16bit = {insn[25:21],insn[10:0]};
1477
         // ALU op for ALU instructions
1478 449 julius
         alu_op = insn[`OR1K_ALU_OP_POS];
1479 351 julius
         // Shift-rotate op for SHROT ALU instructions
1480 449 julius
         shrot_op = insn[`OR1K_SHROT_OP_POS];
1481
         shroti_imm = insn[`OR1K_SHROTI_IMM_POS];
1482 351 julius
 
1483
         // Set flag op
1484 449 julius
         sf_op = insn[`OR1K_SF_OP];
1485 351 julius
 
1486 449 julius
         // Xsync/syscall/trap opcode
1487
         xsync_op = insn[`OR1K_XSYNC_OP_POS];
1488
 
1489 351 julius
         case (opcode)
1490
           `OR1200_OR32_J:
1491
             begin
1492 449 julius
                $fwrite(finsn,"l.j 0x%h", {j_imm,2'b00});
1493 351 julius
             end
1494
 
1495
           `OR1200_OR32_JAL:
1496
             begin
1497 449 julius
                $fwrite(finsn,"l.jal 0x%h", {j_imm,2'b00});
1498 351 julius
             end
1499
 
1500
           `OR1200_OR32_BNF:
1501
             begin
1502 449 julius
                $fwrite(finsn,"l.bnf 0x%h", {br_imm,2'b00});
1503 351 julius
             end
1504
 
1505
           `OR1200_OR32_BF:
1506
             begin
1507 449 julius
                $fwrite(finsn,"l.bf 0x%h", {br_imm,2'b00});
1508 351 julius
             end
1509
 
1510
           `OR1200_OR32_RFE:
1511
             begin
1512 449 julius
                $fwrite(finsn,"l.rfe");
1513 351 julius
             end
1514
 
1515
           `OR1200_OR32_JR:
1516
             begin
1517 449 julius
                $fwrite(finsn,"l.jr r%0d",rB_num);
1518 351 julius
             end
1519
 
1520
           `OR1200_OR32_JALR:
1521
             begin
1522 449 julius
                $fwrite(finsn,"l.jalr r%0d",rB_num);
1523 351 julius
             end
1524
 
1525
           `OR1200_OR32_LWZ:
1526
             begin
1527 449 julius
                $fwrite(finsn,"l.lwz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1528 351 julius
             end
1529
 
1530
           `OR1200_OR32_LBZ:
1531
             begin
1532 449 julius
                $fwrite(finsn,"l.lbz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1533 351 julius
             end
1534
 
1535
           `OR1200_OR32_LBS:
1536
             begin
1537 449 julius
                $fwrite(finsn,"l.lbs r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1538 351 julius
             end
1539
 
1540
           `OR1200_OR32_LHZ:
1541
             begin
1542 449 julius
                $fwrite(finsn,"l.lhz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1543 351 julius
             end
1544
 
1545
           `OR1200_OR32_LHS:
1546
             begin
1547 449 julius
                $fwrite(finsn,"l.lhs r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1548 351 julius
             end
1549
 
1550
           `OR1200_OR32_SW:
1551
             begin
1552 449 julius
                $fwrite(finsn,"l.sw 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
1553 351 julius
             end
1554
 
1555
           `OR1200_OR32_SB:
1556
             begin
1557 449 julius
                $fwrite(finsn,"l.sb 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
1558 351 julius
             end
1559
 
1560
           `OR1200_OR32_SH:
1561
             begin
1562 449 julius
                $fwrite(finsn,"l.sh 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
1563 351 julius
             end
1564
 
1565
           `OR1200_OR32_MFSPR:
1566
             begin
1567 449 julius
                $fwrite(finsn,"l.mfspr r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit,);
1568 351 julius
             end
1569
 
1570
           `OR1200_OR32_MTSPR:
1571
             begin
1572 449 julius
                $fwrite(finsn,"l.mtspr r%0d,r%0d,0x%h",rA_num,rB_num,imm_split16bit);
1573 351 julius
             end
1574
 
1575
           `OR1200_OR32_MOVHI:
1576
             begin
1577
                if (!insn[16])
1578 449 julius
                  $fwrite(finsn,"l.movhi r%0d,0x%h",rD_num,imm_16bit);
1579 351 julius
                else
1580 449 julius
                  $fwrite(finsn,"l.macrc r%0d",rD_num);
1581 351 julius
             end
1582
 
1583
           `OR1200_OR32_ADDI:
1584
             begin
1585 449 julius
                $fwrite(finsn,"l.addi r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1586 351 julius
             end
1587
 
1588
           `OR1200_OR32_ADDIC:
1589
             begin
1590 449 julius
                $fwrite(finsn,"l.addic r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1591 351 julius
             end
1592
 
1593
           `OR1200_OR32_ANDI:
1594
             begin
1595 449 julius
                $fwrite(finsn,"l.andi r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1596 351 julius
             end
1597
 
1598
           `OR1200_OR32_ORI:
1599
             begin
1600 449 julius
                $fwrite(finsn,"l.ori r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1601 351 julius
             end
1602
 
1603
           `OR1200_OR32_XORI:
1604
             begin
1605 449 julius
                $fwrite(finsn,"l.xori r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1606 351 julius
             end
1607
 
1608
           `OR1200_OR32_MULI:
1609
             begin
1610 449 julius
                $fwrite(finsn,"l.muli r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1611 351 julius
             end
1612
 
1613
           `OR1200_OR32_ALU:
1614
             begin
1615
                case(alu_op)
1616
                  `OR1200_ALUOP_ADD:
1617 449 julius
                    $fwrite(finsn,"l.add ");
1618 351 julius
                  `OR1200_ALUOP_ADDC:
1619 449 julius
                    $fwrite(finsn,"l.addc ");
1620 351 julius
                  `OR1200_ALUOP_SUB:
1621 449 julius
                    $fwrite(finsn,"l.sub ");
1622 351 julius
                  `OR1200_ALUOP_AND:
1623 449 julius
                    $fwrite(finsn,"l.and ");
1624 351 julius
                  `OR1200_ALUOP_OR:
1625 449 julius
                    $fwrite(finsn,"l.or ");
1626 351 julius
                  `OR1200_ALUOP_XOR:
1627 449 julius
                    $fwrite(finsn,"l.xor ");
1628 351 julius
                  `OR1200_ALUOP_MUL:
1629 449 julius
                    $fwrite(finsn,"l.mul ");
1630 351 julius
                  `OR1200_ALUOP_SHROT:
1631
                    begin
1632
                       case(shrot_op)
1633
                         `OR1200_SHROTOP_SLL:
1634 449 julius
                           $fwrite(finsn,"l.sll ");
1635 351 julius
                         `OR1200_SHROTOP_SRL:
1636 449 julius
                           $fwrite(finsn,"l.srl ");
1637 351 julius
                         `OR1200_SHROTOP_SRA:
1638 449 julius
                           $fwrite(finsn,"l.sra ");
1639 351 julius
                         `OR1200_SHROTOP_ROR:
1640 449 julius
                           $fwrite(finsn,"l.ror ");
1641 351 julius
                       endcase // case (shrot_op)
1642
                    end
1643
                  `OR1200_ALUOP_DIV:
1644 449 julius
                    $fwrite(finsn,"l.div ");
1645 351 julius
                  `OR1200_ALUOP_DIVU:
1646 449 julius
                    $fwrite(finsn,"l.divu ");
1647 351 julius
                  `OR1200_ALUOP_CMOV:
1648 449 julius
                    $fwrite(finsn,"l.cmov ");
1649 351 julius
                endcase // case (alu_op)
1650 449 julius
                $fwrite(finsn,"r%0d,r%0d,r%0d",rD_num,rA_num,rB_num);
1651 351 julius
             end
1652
 
1653
           `OR1200_OR32_SH_ROTI:
1654
             begin
1655
                case(shrot_op)
1656
                  `OR1200_SHROTOP_SLL:
1657 449 julius
                    $fwrite(finsn,"l.slli ");
1658 351 julius
                  `OR1200_SHROTOP_SRL:
1659 449 julius
                    $fwrite(finsn,"l.srli ");
1660 351 julius
                  `OR1200_SHROTOP_SRA:
1661 449 julius
                    $fwrite(finsn,"l.srai ");
1662 351 julius
                  `OR1200_SHROTOP_ROR:
1663 449 julius
                    $fwrite(finsn,"l.rori ");
1664 351 julius
                endcase // case (shrot_op)
1665 449 julius
                $fwrite(finsn,"r%0d,r%0d,0x%h",rD_num,rA_num,shroti_imm);
1666 351 julius
             end
1667
 
1668
           `OR1200_OR32_SFXXI:
1669
             begin
1670
                case(sf_op[2:0])
1671
                  `OR1200_COP_SFEQ:
1672 449 julius
                    $fwrite(finsn,"l.sfeqi ");
1673 351 julius
                  `OR1200_COP_SFNE:
1674 449 julius
                    $fwrite(finsn,"l.sfnei ");
1675 351 julius
                  `OR1200_COP_SFGT:
1676
                    begin
1677
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1678 449 julius
                         $fwrite(finsn,"l.sfgtsi ");
1679 351 julius
                       else
1680 449 julius
                         $fwrite(finsn,"l.sfgtui ");
1681 351 julius
                    end
1682
                  `OR1200_COP_SFGE:
1683
                    begin
1684
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1685 449 julius
                         $fwrite(finsn,"l.sfgesi ");
1686 351 julius
                       else
1687 449 julius
                         $fwrite(finsn,"l.sfgeui ");
1688 351 julius
                    end
1689
                  `OR1200_COP_SFLT:
1690
                    begin
1691
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1692 449 julius
                         $fwrite(finsn,"l.sfltsi ");
1693 351 julius
                       else
1694 449 julius
                         $fwrite(finsn,"l.sfltui ");
1695 351 julius
                    end
1696
                  `OR1200_COP_SFLE:
1697
                    begin
1698
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1699 449 julius
                         $fwrite(finsn,"l.sflesi ");
1700 351 julius
                       else
1701 449 julius
                         $fwrite(finsn,"l.sfleui ");
1702 351 julius
                    end
1703
                endcase // case (sf_op[2:0])
1704
 
1705 449 julius
                $fwrite(finsn,"r%0d,0x%h",rA_num, imm_16bit);
1706 351 julius
 
1707
             end // case: `OR1200_OR32_SFXXI
1708
 
1709
           `OR1200_OR32_SFXX:
1710
             begin
1711
                case(sf_op[2:0])
1712
                  `OR1200_COP_SFEQ:
1713 449 julius
                    $fwrite(finsn,"l.sfeq ");
1714 351 julius
                  `OR1200_COP_SFNE:
1715 449 julius
                    $fwrite(finsn,"l.sfne ");
1716 351 julius
                  `OR1200_COP_SFGT:
1717
                    begin
1718
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1719 449 julius
                         $fwrite(finsn,"l.sfgts ");
1720 351 julius
                       else
1721 449 julius
                         $fwrite(finsn,"l.sfgtu ");
1722 351 julius
                    end
1723
                  `OR1200_COP_SFGE:
1724
                    begin
1725
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1726 449 julius
                         $fwrite(finsn,"l.sfges ");
1727 351 julius
                       else
1728 449 julius
                         $fwrite(finsn,"l.sfgeu ");
1729 351 julius
                    end
1730
                  `OR1200_COP_SFLT:
1731
                    begin
1732
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1733 449 julius
                         $fwrite(finsn,"l.sflts ");
1734 351 julius
                       else
1735 449 julius
                         $fwrite(finsn,"l.sfltu ");
1736 351 julius
                    end
1737
                  `OR1200_COP_SFLE:
1738
                    begin
1739
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1740 449 julius
                         $fwrite(finsn,"l.sfles ");
1741 351 julius
                       else
1742 449 julius
                         $fwrite(finsn,"l.sfleu ");
1743 351 julius
                    end
1744
 
1745
                endcase // case (sf_op[2:0])
1746
 
1747 449 julius
                $fwrite(finsn,"r%0d,r%0d",rA_num, rB_num);
1748 351 julius
 
1749
             end
1750
 
1751
           `OR1200_OR32_MACI:
1752
             begin
1753 449 julius
                $fwrite(finsn,"l.maci r%0d,0x%h",rA_num,imm_16bit);
1754 351 julius
             end
1755
 
1756
           `OR1200_OR32_MACMSB:
1757
             begin
1758
                if(insn[3:0] == 4'h1)
1759 449 julius
                  $fwrite(finsn,"l.mac ");
1760 351 julius
                else if(insn[3:0] == 4'h2)
1761 449 julius
                  $fwrite(finsn,"l.msb ");
1762 351 julius
 
1763 449 julius
                $fwrite(finsn,"r%0d,r%0d",rA_num,rB_num);
1764 351 julius
             end
1765
 
1766
           `OR1200_OR32_NOP:
1767
             begin
1768 449 julius
                $fwrite(finsn,"l.nop 0x%0h",imm_16bit);
1769 351 julius
             end
1770
 
1771
           `OR1200_OR32_XSYNC:
1772
             begin
1773
                case (xsync_op)
1774
                  5'd0:
1775 449 julius
                    $fwrite(finsn,"l.sys 0x%h",imm_16bit);
1776 351 julius
                  5'd8:
1777 449 julius
                    $fwrite(finsn,"l.trap 0x%h",imm_16bit);
1778 351 julius
                  5'd16:
1779 449 julius
                    $fwrite(finsn,"l.msync");
1780 351 julius
                  5'd20:
1781 449 julius
                    $fwrite(finsn,"l.psync");
1782 351 julius
                  5'd24:
1783 449 julius
                    $fwrite(finsn,"l.csync");
1784 351 julius
                  default:
1785
                    begin
1786
                       $display("%t: Instruction with opcode 0x%h has bad specific type information: 0x%h",$time,opcode,insn);
1787 449 julius
                       $fwrite(finsn,"%t: Instruction with opcode 0x%h has has bad specific type information: 0x%h",$time,opcode,insn);
1788 351 julius
                    end
1789
                endcase // case (xsync_op)
1790
             end
1791
 
1792
           default:
1793
             begin
1794
                $display("%t: Unknown opcode 0x%h",$time,opcode);
1795 449 julius
                $fwrite(finsn,"%t: Unknown opcode 0x%h",$time,opcode);
1796 351 julius
             end
1797
 
1798
         endcase // case (opcode)
1799
 
1800
      end
1801
   endtask // or1200_print_op
1802
 
1803
 
1804
 
1805 6 julius
endmodule

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