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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's simulation monitor                                 ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Simulation monitor                                          ////
////                                                              ////
////  To Do:                                                      ////
////   - move it to bench                                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_monitor.v,v $
// Revision 1.4  2004/04/05 08:46:06  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3  2003/04/07 01:32:53  lampret
// Added get_gpr support for OR1200_RFRAM_GENERIC
//
// Revision 1.2  2002/08/12 05:38:11  lampret
// Added more WISHBONE protocol checks. Removed nop.log. Added general.log and lookup.log.
//
// Revision 1.1  2002/03/28 19:59:55  lampret
// Added bench directory
//
// Revision 1.9  2002/02/01 19:56:54  lampret
// Fixed combinational loops.
//
// Revision 1.8  2002/01/28 01:25:22  lampret
// Fixed display of new 'void' nop insns.
//
// Revision 1.7  2002/01/19 14:10:39  lampret
// Fixed OR1200_XILINX_RAM32X1D.
//
// Revision 1.6  2002/01/18 07:57:56  lampret
// Added support for reading XILINX_RAM32X1D register file.
//
// Revision 1.5  2002/01/14 06:19:35  lampret
// Added debug model for testing du. Updated or1200_monitor.
//
// Revision 1.4  2002/01/03 08:40:15  lampret
// Added second clock as RISC main clock. Updated or120_monitor.
//
// Revision 1.3  2001/11/23 08:50:35  lampret
// Typos.
//
// Revision 1.2  2001/11/10 04:22:55  lampret
// Modified monitor tu support exceptions.
//
// Revision 1.1.1.1  2001/11/04 18:51:07  lampret
// First import.
//
// Revision 1.1  2001/08/20 18:17:52  damjan
// Initial revision
//
// Revision 1.1  2001/08/13 03:37:07  lampret
// Added monitor.v and timescale.v
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
`include "timescale.v"
`include "or1200_defines.v"
`include "orpsoc_testbench_defines.v"
 
//
// Top of OR1200 inside test bench
//
`define OR1200_TOP orpsoc_testbench.dut.i_or1k.i_or1200_top
 
//
// Enable display_arch_state task
//
//`define OR1200_DISPLAY_ARCH_STATE
 
module or1200_monitor;
 
   integer fexe;
   reg [23:0] ref;
   integer    fspr;
   integer    fgeneral;
   integer    flookup;
   integer    r3;
   integer    insns;
 
   //
   // Initialization
   //
   initial begin
      ref = 0;
      fexe = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-executed.log"});
      $timeformat (-9, 2, " ns", 12);
      fspr = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-sprs.log"});
      fgeneral = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-general.log"});
      flookup = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-lookup.log"});
      insns = 0;
 
   end
 
   //
   // Get GPR
   //
   task get_gpr;
      input     [4:0]    gpr_no;
      output [31:0]      gpr;
      integer           j;
      begin
`ifdef OR1200_RFRAM_GENERIC
         for(j = 0; j < 32; j = j + 1) begin
            gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no*32+j];
         end
`else
 `ifdef OR1200_XILINX_RAM32X1D
         gpr[0] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0.mem[gpr_no];
         gpr[1] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1.mem[gpr_no];
         gpr[2] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_2.mem[gpr_no];
         gpr[3] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_3.mem[gpr_no];
         gpr[4] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_4.mem[gpr_no];
         gpr[5] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_5.mem[gpr_no];
         gpr[6] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_6.mem[gpr_no];
         gpr[7] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_7.mem[gpr_no];
         gpr[8] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0.mem[gpr_no];
gpr[9] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1.mem[gpr_no];
         gpr[10] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_2.mem[gpr_no];
gpr[11] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_3.mem[gpr_no];
         gpr[12] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_4.mem[gpr_no];
gpr[13] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_5.mem[gpr_no];
         gpr[14] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_6.mem[gpr_no];
gpr[15] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_7.mem[gpr_no];
         gpr[16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0.mem[gpr_no];
gpr[17] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1.mem[gpr_no];
gpr[18] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_2.mem[gpr_no];
gpr[19] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_3.mem[gpr_no];
gpr[20] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_4.mem[gpr_no];
gpr[21] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_5.mem[gpr_no];
gpr[22] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_6.mem[gpr_no];
gpr[23] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_7.mem[gpr_no];
gpr[24] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0.mem[gpr_no];
gpr[25] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1.mem[gpr_no];
gpr[26] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_2.mem[gpr_no];
gpr[27] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_3.mem[gpr_no];
gpr[28] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_4.mem[gpr_no];
gpr[29] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_5.mem[gpr_no];
gpr[30] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_6.mem[gpr_no];
gpr[31] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_7.mem[gpr_no];
`else
 `ifdef OR1200_XILINX_RAMB4
         for(j = 0; j < 16; j = j + 1) begin
            gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_0.mem[gpr_no*16+j];
         end
for(j = 0; j < 16; j = j + 1) begin
   gpr[j+16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[gpr_no*16+j];
end
 `else
  `ifdef OR1200_ARTISAN_SDP
  `else
gpr = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no];
  `endif
 `endif
`endif
`endif
         end
 endtask
 
   //
   // Write state of the OR1200 registers into a file
   //
   // Limitation: only a small subset of register file RAMs
   // are supported
   //
   task display_arch_state;
      reg [5:0] i;
      reg [31:0] r;
      integer    j;
      begin
`ifdef OR1200_DISPLAY_ARCH_STATE
         ref = ref + 1;
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h", insns, `OR1200_TOP.or1200_cpu.or1200_except.wb_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn);
         for(i = 0; i < 32; i = i + 1) begin
            if (i % 4 == 0)
              $fdisplay(fexe);
            get_gpr(i, r);
            $fwrite(fexe, "GPR%d: %h  ", i, r);
         end
         $fdisplay(fexe);
         r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
         $fwrite(fexe, "SR   : %h  ", r);
         r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
         $fwrite(fexe, "EPCR0: %h  ", r);
         r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
         $fwrite(fexe, "EEAR0: %h  ", r);
         r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
         $fdisplay(fexe, "ESR0 : %h", r);
         insns = insns + 1;
`endif
end
   endtask // display_arch_state
 
   /* Keep a trace buffer of the last lot of instructions and addresses
    * "executed",as read from the writeback stage, and cause a $finish if we hit
    * an instruction that is invalid, such as all zeros.
    * Currently, only breaks on an all zero instruction, but should probably be
    * made to break for anything with an X in it too. And of course ideally this
    * shouldn't be needed - but is handy if someone changes something and stops
    * the test continuing forever.
    */
   integer num_nul_inst;
   initial num_nul_inst = 0;
 
   task monitor_for_crash;
      `define OR1200_MONITOR_CRASH_TRACE_SIZE 32
      reg [31:0] insn_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1]; //Trace buffer of 32 instructions
      reg [31:0] addr_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1]; //Trace buffer of the addresses of those instructions
      integer i;
 
     begin
        if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h00000000)
          num_nul_inst = num_nul_inst + 1;
 
        if (num_nul_inst == 1000) // Sat a loop a bit too long...
          begin
             $fdisplay(fgeneral, "ERROR - no instruction at PC %h", `OR1200_TOP.or1200_cpu.or1200_except.wb_pc);
             $fdisplay(fgeneral, "Crash trace: Last %d instructions: ",`OR1200_MONITOR_CRASH_TRACE_SIZE);
 
             $fdisplay(fgeneral, "PC\t\tINSTR");
             for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
                $fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);
             end
             #100 $finish;
          end
        else
          begin
             for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
                insn_trace[i] = insn_trace[i-1];
                addr_trace[i] = addr_trace[i-1];
             end
             insn_trace[0] = `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn;
             addr_trace[0] = `OR1200_TOP.or1200_cpu.or1200_except.wb_pc;
          end
 
     end
   endtask // monitor_for_crash
 
 
   //
   // Write state of the OR1200 registers into a file; version for exception
   //
   task display_arch_state_except;
      reg [5:0] i;
      reg [31:0] r;
      integer    j;
      begin
`ifdef OR1200_DISPLAY_ARCH_STATE
         ref = ref + 1;
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h  (exception)", insns, `OR1200_TOP.or1200_cpu.or1200_except.ex_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.ex_insn);
         for(i = 0; i < 32; i = i + 1) begin
            if (i % 4 == 0)
              $fdisplay(fexe);
            get_gpr(i, r);
            $fwrite(fexe, "GPR%d: %h  ", i, r);
         end
         $fdisplay(fexe);
         r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
         $fwrite(fexe, "SR   : %h  ", r);
         r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
         $fwrite(fexe, "EPCR0: %h  ", r);
         r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
         $fwrite(fexe, "EEAR0: %h  ", r);
         r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
         $fdisplay(fexe, "ESR0 : %h", r);
         insns = insns + 1;
`endif
end
   endtask
 
   integer iwb_progress;
   reg [31:0] iwb_progress_addr;
   //
   // WISHBONE bus checker
   //
   always @(posedge `OR1200_TOP.iwb_clk_i)
     if (`OR1200_TOP.iwb_rst_i) begin
        iwb_progress = 0;
        iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
     end
     else begin
        if (`OR1200_TOP.iwb_cyc_o && (iwb_progress != 2)) begin
           iwb_progress = 1;
        end
        if (`OR1200_TOP.iwb_stb_o) begin
           if (iwb_progress >= 1) begin
              if (iwb_progress == 1)
                iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
              iwb_progress = 2;
           end
           else begin
              $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o raised without `OR1200_TOP.iwb_cyc_o, at %t\n", $time);
              #100 $finish;
           end
        end
        if (`OR1200_TOP.iwb_ack_i & `OR1200_TOP.iwb_err_i) begin
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i and `OR1200_TOP.iwb_err_i raised at the same time, at %t\n", $time);
        end
        if ((iwb_progress == 2) && (iwb_progress_addr != `OR1200_TOP.iwb_adr_o)) begin
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_adr_o changed while waiting for `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
           #100 $finish;
        end
        if (`OR1200_TOP.iwb_ack_i | `OR1200_TOP.iwb_err_i)
          if (iwb_progress == 2) begin
             iwb_progress = 0;
             iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
          end
          else begin
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
             #100 $finish;
          end
        if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
           /*                   #100 $finish;*/
        end
     end
 
   integer dwb_progress;
reg [31:0] dwb_progress_addr;
//
// WISHBONE bus checker
//
always @(posedge `OR1200_TOP.dwb_clk_i)
  if (`OR1200_TOP.dwb_rst_i)
    dwb_progress = 0;
  else begin
     if (`OR1200_TOP.dwb_cyc_o && (dwb_progress != 2))
       dwb_progress = 1;
     if (`OR1200_TOP.dwb_stb_o)
       if (dwb_progress >= 1) begin
          if (dwb_progress == 1)
            dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
          dwb_progress = 2;
       end
       else begin
          $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o raised without `OR1200_TOP.dwb_cyc_o, at %t\n", $time);
          #100 $finish;
       end
     if (`OR1200_TOP.dwb_ack_i & `OR1200_TOP.dwb_err_i) begin
        $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i and `OR1200_TOP.dwb_err_i raised at the same time, at %t\n", $time);
     end
     if ((dwb_progress == 2) && (dwb_progress_addr != `OR1200_TOP.dwb_adr_o)) begin
        $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_adr_o changed while waiting for `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
        #100 $finish;
     end
     if (`OR1200_TOP.dwb_ack_i | `OR1200_TOP.dwb_err_i)
       if (dwb_progress == 2) begin
          dwb_progress = 0;
          dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
       end
       else begin
          $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i/`OR1200_TOP.dwb_err_i raised without `OR1200_TOP.dwb_cyc_i/`OR1200_TOP.dwb_stb_i, at %t\n", $time);
          #100 $finish;
       end
     if ((dwb_progress == 2) && !`OR1200_TOP.dwb_stb_o) begin
        $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o lowered without `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
        #100 $finish;
     end
       end
 
//
// Hooks for:
// - displaying registers
// - end of simulation
// - access to SPRs
//
   always @(posedge `OR1200_TOP.or1200_cpu.or1200_ctrl.clk)
     if (!`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_freeze) begin
        #2;
        if (((`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP) || !`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[16])
            && !(`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe && `OR1200_TOP.or1200_cpu.or1200_except.ex_dslot))
          begin
             display_arch_state;
             monitor_for_crash;
          end
        else
          if (`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe)
            display_arch_state_except;
        if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0001) begin // small hack to stop simulation (l.nop 1)
           get_gpr(3, r3);
           $fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
           $finish;
        end
        if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_000a) begin // debug if test (l.nop 10)
           $fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
`ifdef DBG_IF_MODEL
           xess_top.i_xess_fpga.dbg_if_model.dbg_if_test_go = 1;
`endif
        end
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0002) begin // simulation reports (l.nop 2)
   get_gpr(3, r3);
   $fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
end
        if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0003) begin // simulation printfs (l.nop 3)
           get_gpr(3, r3);
           $fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);
        end
        if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MTSR)  // l.mtspr
          $fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
                    `OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.spr_dat_o);
        if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MFSR)  // l.mfspr
          $fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
                    `OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.to_wbmux);
     end
 
endmodule

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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [or1200_monitor.v] - Blame information for rev 55

Line No.	Rev	Author	Line
1	6	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's simulation monitor ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Simulation monitor ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - move it to bench ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: or1200_monitor.v,v $`
47			`// Revision 1.4 2004/04/05 08:46:06 lampret`
48			`// Merged branch_qmem into main tree.`
49			`//`
50			`// Revision 1.3 2003/04/07 01:32:53 lampret`
51			`// Added get_gpr support for OR1200_RFRAM_GENERIC`
52			`//`
53			`// Revision 1.2 2002/08/12 05:38:11 lampret`
54			`// Added more WISHBONE protocol checks. Removed nop.log. Added general.log and lookup.log.`
55			`//`
56			`// Revision 1.1 2002/03/28 19:59:55 lampret`
57			`// Added bench directory`
58			`//`
59			`// Revision 1.9 2002/02/01 19:56:54 lampret`
60			`// Fixed combinational loops.`
61			`//`
62			`// Revision 1.8 2002/01/28 01:25:22 lampret`
63			`// Fixed display of new 'void' nop insns.`
64			`//`
65			`// Revision 1.7 2002/01/19 14:10:39 lampret`
66			`// Fixed OR1200_XILINX_RAM32X1D.`
67			`//`
68			`// Revision 1.6 2002/01/18 07:57:56 lampret`
69			`// Added support for reading XILINX_RAM32X1D register file.`
70			`//`
71			`// Revision 1.5 2002/01/14 06:19:35 lampret`
72			`// Added debug model for testing du. Updated or1200_monitor.`
73			`//`
74			`// Revision 1.4 2002/01/03 08:40:15 lampret`
75			`// Added second clock as RISC main clock. Updated or120_monitor.`
76			`//`
77			`// Revision 1.3 2001/11/23 08:50:35 lampret`
78			`// Typos.`
79			`//`
80			`// Revision 1.2 2001/11/10 04:22:55 lampret`
81			`// Modified monitor tu support exceptions.`
82			`//`
83			`// Revision 1.1.1.1 2001/11/04 18:51:07 lampret`
84			`// First import.`
85			`//`
86			`// Revision 1.1 2001/08/20 18:17:52 damjan`
87			`// Initial revision`
88			`//`
89			`// Revision 1.1 2001/08/13 03:37:07 lampret`
90			`// Added monitor.v and timescale.v`
91			`//`
92			`// Revision 1.1 2001/07/20 00:46:03 lampret`
93			`// Development version of RTL. Libraries are missing.`
94			`//`
95			`//`
96	55	julius	`include "timescale.v"
97	6	julius	`include "or1200_defines.v"
98			`include "orpsoc_testbench_defines.v"
99
100			`//`
101			`// Top of OR1200 inside test bench`
102			`//`
103			`define OR1200_TOP orpsoc_testbench.dut.i_or1k.i_or1200_top
104
105			`//`
106			`// Enable display_arch_state task`
107			`//`
108			//`define OR1200_DISPLAY_ARCH_STATE
109
110			`module or1200_monitor;`
111
112			`integer fexe;`
113			`reg [23:0] ref;`
114			`integer fspr;`
115			`integer fgeneral;`
116			`integer flookup;`
117			`integer r3;`
118			`integer insns;`
119
120			`//`
121			`// Initialization`
122			`//`
123			`initial begin`
124			`ref = 0;`
125			fexe = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-executed.log"});
126			`$timeformat (-9, 2, " ns", 12);`
127			fspr = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-sprs.log"});
128			fgeneral = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-general.log"});
129			flookup = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-lookup.log"});
130			`insns = 0;`
131
132			`end`
133
134			`//`
135			`// Get GPR`
136			`//`
137			`task get_gpr;`
138			`input [4:0] gpr_no;`
139			`output [31:0] gpr;`
140			`integer j;`
141			`begin`
142			`ifdef OR1200_RFRAM_GENERIC
143			`for(j = 0; j < 32; j = j + 1) begin`
144			gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no*32+j];
145			`end`
146			`else
147			`ifdef OR1200_XILINX_RAM32X1D
148			gpr[0] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0.mem[gpr_no];
149			gpr[1] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1.mem[gpr_no];
150			gpr[2] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_2.mem[gpr_no];
151			gpr[3] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_3.mem[gpr_no];
152			gpr[4] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_4.mem[gpr_no];
153			gpr[5] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_5.mem[gpr_no];
154			gpr[6] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_6.mem[gpr_no];
155			gpr[7] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_7.mem[gpr_no];
156			gpr[8] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0.mem[gpr_no];
157			gpr[9] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1.mem[gpr_no];
158			gpr[10] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_2.mem[gpr_no];
159			gpr[11] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_3.mem[gpr_no];
160			gpr[12] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_4.mem[gpr_no];
161			gpr[13] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_5.mem[gpr_no];
162			gpr[14] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_6.mem[gpr_no];
163			gpr[15] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_7.mem[gpr_no];
164			gpr[16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0.mem[gpr_no];
165			gpr[17] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1.mem[gpr_no];
166			gpr[18] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_2.mem[gpr_no];
167			gpr[19] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_3.mem[gpr_no];
168			gpr[20] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_4.mem[gpr_no];
169			gpr[21] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_5.mem[gpr_no];
170			gpr[22] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_6.mem[gpr_no];
171			gpr[23] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_7.mem[gpr_no];
172			gpr[24] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0.mem[gpr_no];
173			gpr[25] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1.mem[gpr_no];
174			gpr[26] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_2.mem[gpr_no];
175			gpr[27] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_3.mem[gpr_no];
176			gpr[28] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_4.mem[gpr_no];
177			gpr[29] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_5.mem[gpr_no];
178			gpr[30] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_6.mem[gpr_no];
179			gpr[31] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_7.mem[gpr_no];
180			`else
181			`ifdef OR1200_XILINX_RAMB4
182			`for(j = 0; j < 16; j = j + 1) begin`
183			gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_0.mem[gpr_no*16+j];
184			`end`
185			`for(j = 0; j < 16; j = j + 1) begin`
186			gpr[j+16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[gpr_no*16+j];
187			`end`
188			`else
189			`ifdef OR1200_ARTISAN_SDP
190			`else
191			gpr = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no];
192			`endif
193			`endif
194			`endif
195			`endif
196			`end`
197			`endtask`
198
199			`//`
200			`// Write state of the OR1200 registers into a file`
201			`//`
202			`// Limitation: only a small subset of register file RAMs`
203			`// are supported`
204			`//`
205			`task display_arch_state;`
206			`reg [5:0] i;`
207			`reg [31:0] r;`
208			`integer j;`
209			`begin`
210			`ifdef OR1200_DISPLAY_ARCH_STATE
211			`ref = ref + 1;`
212			`$fdisplay(flookup, "Instruction %d: %t", insns, $time);`
213			$fwrite(fexe, "\nEXECUTED(%d): %h: %h", insns, `OR1200_TOP.or1200_cpu.or1200_except.wb_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn);
214			`for(i = 0; i < 32; i = i + 1) begin`
215			`if (i % 4 == 0)`
216			`$fdisplay(fexe);`
217			`get_gpr(i, r);`
218			`$fwrite(fexe, "GPR%d: %h ", i, r);`
219			`end`
220			`$fdisplay(fexe);`
221			r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
222			`$fwrite(fexe, "SR : %h ", r);`
223			r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
224			`$fwrite(fexe, "EPCR0: %h ", r);`
225			r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
226			`$fwrite(fexe, "EEAR0: %h ", r);`
227			r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
228			`$fdisplay(fexe, "ESR0 : %h", r);`
229			`insns = insns + 1;`
230			`endif
231			`end`
232			`endtask // display_arch_state`
233
234			`/* Keep a trace buffer of the last lot of instructions and addresses`
235			`* "executed",as read from the writeback stage, and cause a $finish if we hit`
236			`* an instruction that is invalid, such as all zeros.`
237			`* Currently, only breaks on an all zero instruction, but should probably be`
238			`* made to break for anything with an X in it too. And of course ideally this`
239			`* shouldn't be needed - but is handy if someone changes something and stops`
240			`* the test continuing forever.`
241			`*/`
242	49	julius	`integer num_nul_inst;`
243			`initial num_nul_inst = 0;`
244
245	6	julius	`task monitor_for_crash;`
246			`define OR1200_MONITOR_CRASH_TRACE_SIZE 32
247			reg [31:0] insn_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1]; //Trace buffer of 32 instructions
248			reg [31:0] addr_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1]; //Trace buffer of the addresses of those instructions
249			`integer i;`
250
251			`begin`
252			if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h00000000)
253	49	julius	`num_nul_inst = num_nul_inst + 1;`
254
255			`if (num_nul_inst == 1000) // Sat a loop a bit too long...`
256	6	julius	`begin`
257			$fdisplay(fgeneral, "ERROR - no instruction at PC %h", `OR1200_TOP.or1200_cpu.or1200_except.wb_pc);
258			$fdisplay(fgeneral, "Crash trace: Last %d instructions: ",`OR1200_MONITOR_CRASH_TRACE_SIZE);
259
260			`$fdisplay(fgeneral, "PC\t\tINSTR");`
261			for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
262			`$fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);`
263			`end`
264			`#100 $finish;`
265			`end`
266			`else`
267			`begin`
268			for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
269			`insn_trace[i] = insn_trace[i-1];`
270			`addr_trace[i] = addr_trace[i-1];`
271			`end`
272			insn_trace[0] = `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn;
273			addr_trace[0] = `OR1200_TOP.or1200_cpu.or1200_except.wb_pc;
274			`end`
275
276			`end`
277			`endtask // monitor_for_crash`
278
279
280			`//`
281			`// Write state of the OR1200 registers into a file; version for exception`
282			`//`
283			`task display_arch_state_except;`
284			`reg [5:0] i;`
285			`reg [31:0] r;`
286			`integer j;`
287			`begin`
288			`ifdef OR1200_DISPLAY_ARCH_STATE
289			`ref = ref + 1;`
290			`$fdisplay(flookup, "Instruction %d: %t", insns, $time);`
291			$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns, `OR1200_TOP.or1200_cpu.or1200_except.ex_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.ex_insn);
292			`for(i = 0; i < 32; i = i + 1) begin`
293			`if (i % 4 == 0)`
294			`$fdisplay(fexe);`
295			`get_gpr(i, r);`
296			`$fwrite(fexe, "GPR%d: %h ", i, r);`
297			`end`
298			`$fdisplay(fexe);`
299			r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
300			`$fwrite(fexe, "SR : %h ", r);`
301			r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
302			`$fwrite(fexe, "EPCR0: %h ", r);`
303			r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
304			`$fwrite(fexe, "EEAR0: %h ", r);`
305			r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
306			`$fdisplay(fexe, "ESR0 : %h", r);`
307			`insns = insns + 1;`
308			`endif
309			`end`
310			`endtask`
311
312			`integer iwb_progress;`
313			`reg [31:0] iwb_progress_addr;`
314			`//`
315			`// WISHBONE bus checker`
316			`//`
317			always @(posedge `OR1200_TOP.iwb_clk_i)
318			if (`OR1200_TOP.iwb_rst_i) begin
319			`iwb_progress = 0;`
320			iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
321			`end`
322			`else begin`
323			if (`OR1200_TOP.iwb_cyc_o && (iwb_progress != 2)) begin
324			`iwb_progress = 1;`
325			`end`
326			if (`OR1200_TOP.iwb_stb_o) begin
327			`if (iwb_progress >= 1) begin`
328			`if (iwb_progress == 1)`
329			iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
330			`iwb_progress = 2;`
331			`end`
332			`else begin`
333			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o raised without `OR1200_TOP.iwb_cyc_o, at %t\n", $time);
334			`#100 $finish;`
335			`end`
336			`end`
337			if (`OR1200_TOP.iwb_ack_i & `OR1200_TOP.iwb_err_i) begin
338			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i and `OR1200_TOP.iwb_err_i raised at the same time, at %t\n", $time);
339			`end`
340			if ((iwb_progress == 2) && (iwb_progress_addr != `OR1200_TOP.iwb_adr_o)) begin
341			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_adr_o changed while waiting for `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
342			`#100 $finish;`
343			`end`
344			if (`OR1200_TOP.iwb_ack_i \| `OR1200_TOP.iwb_err_i)
345			`if (iwb_progress == 2) begin`
346			`iwb_progress = 0;`
347			iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
348			`end`
349			`else begin`
350			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
351			`#100 $finish;`
352			`end`
353			if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
354			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
355			`/* #100 $finish;*/`
356			`end`
357			`end`
358
359			`integer dwb_progress;`
360			`reg [31:0] dwb_progress_addr;`
361			`//`
362			`// WISHBONE bus checker`
363			`//`
364			always @(posedge `OR1200_TOP.dwb_clk_i)
365			if (`OR1200_TOP.dwb_rst_i)
366			`dwb_progress = 0;`
367			`else begin`
368			if (`OR1200_TOP.dwb_cyc_o && (dwb_progress != 2))
369			`dwb_progress = 1;`
370			if (`OR1200_TOP.dwb_stb_o)
371			`if (dwb_progress >= 1) begin`
372			`if (dwb_progress == 1)`
373			dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
374			`dwb_progress = 2;`
375			`end`
376			`else begin`
377			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o raised without `OR1200_TOP.dwb_cyc_o, at %t\n", $time);
378			`#100 $finish;`
379			`end`
380			if (`OR1200_TOP.dwb_ack_i & `OR1200_TOP.dwb_err_i) begin
381			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i and `OR1200_TOP.dwb_err_i raised at the same time, at %t\n", $time);
382			`end`
383			if ((dwb_progress == 2) && (dwb_progress_addr != `OR1200_TOP.dwb_adr_o)) begin
384			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_adr_o changed while waiting for `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
385			`#100 $finish;`
386			`end`
387			if (`OR1200_TOP.dwb_ack_i \| `OR1200_TOP.dwb_err_i)
388			`if (dwb_progress == 2) begin`
389			`dwb_progress = 0;`
390			dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
391			`end`
392			`else begin`
393			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i/`OR1200_TOP.dwb_err_i raised without `OR1200_TOP.dwb_cyc_i/`OR1200_TOP.dwb_stb_i, at %t\n", $time);
394			`#100 $finish;`
395			`end`
396			if ((dwb_progress == 2) && !`OR1200_TOP.dwb_stb_o) begin
397			$fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o lowered without `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
398			`#100 $finish;`
399			`end`
400			`end`
401
402			`//`
403			`// Hooks for:`
404			`// - displaying registers`
405			`// - end of simulation`
406			`// - access to SPRs`
407			`//`
408			always @(posedge `OR1200_TOP.or1200_cpu.or1200_ctrl.clk)
409			if (!`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_freeze) begin
410			`#2;`
411			if (((`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP) \|\| !`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[16])
412			&& !(`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe && `OR1200_TOP.or1200_cpu.or1200_except.ex_dslot))
413			`begin`
414			`display_arch_state;`
415			`monitor_for_crash;`
416			`end`
417			`else`
418			if (`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe)
419			`display_arch_state_except;`
420			if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0001) begin // small hack to stop simulation (l.nop 1)
421			`get_gpr(3, r3);`
422			`$fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);`
423			`$finish;`
424			`end`
425			if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_000a) begin // debug if test (l.nop 10)
426			`$fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);`
427			`ifdef DBG_IF_MODEL
428			`xess_top.i_xess_fpga.dbg_if_model.dbg_if_test_go = 1;`
429			`endif
430			`end`
431			if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0002) begin // simulation reports (l.nop 2)
432			`get_gpr(3, r3);`
433			`$fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);`
434			`end`
435			if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0003) begin // simulation printfs (l.nop 3)
436			`get_gpr(3, r3);`
437			`$fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);`
438			`end`
439			if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MTSR) // l.mtspr
440			`$fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,`
441			`OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.spr_dat_o);
442			if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MFSR) // l.mfspr
443			`$fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,`
444			`OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.to_wbmux);
445			`end`
446
447			`endmodule`