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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [or1200_monitor.v] - Blame information for rev 6

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1 6 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's simulation monitor                                 ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Simulation monitor                                          ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - move it to bench                                         ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46
// $Log: or1200_monitor.v,v $
47
// Revision 1.4  2004/04/05 08:46:06  lampret
48
// Merged branch_qmem into main tree.
49
//
50
// Revision 1.3  2003/04/07 01:32:53  lampret
51
// Added get_gpr support for OR1200_RFRAM_GENERIC
52
//
53
// Revision 1.2  2002/08/12 05:38:11  lampret
54
// Added more WISHBONE protocol checks. Removed nop.log. Added general.log and lookup.log.
55
//
56
// Revision 1.1  2002/03/28 19:59:55  lampret
57
// Added bench directory
58
//
59
// Revision 1.9  2002/02/01 19:56:54  lampret
60
// Fixed combinational loops.
61
//
62
// Revision 1.8  2002/01/28 01:25:22  lampret
63
// Fixed display of new 'void' nop insns.
64
//
65
// Revision 1.7  2002/01/19 14:10:39  lampret
66
// Fixed OR1200_XILINX_RAM32X1D.
67
//
68
// Revision 1.6  2002/01/18 07:57:56  lampret
69
// Added support for reading XILINX_RAM32X1D register file.
70
//
71
// Revision 1.5  2002/01/14 06:19:35  lampret
72
// Added debug model for testing du. Updated or1200_monitor.
73
//
74
// Revision 1.4  2002/01/03 08:40:15  lampret
75
// Added second clock as RISC main clock. Updated or120_monitor.
76
//
77
// Revision 1.3  2001/11/23 08:50:35  lampret
78
// Typos.
79
//
80
// Revision 1.2  2001/11/10 04:22:55  lampret
81
// Modified monitor tu support exceptions.
82
//
83
// Revision 1.1.1.1  2001/11/04 18:51:07  lampret
84
// First import.
85
//
86
// Revision 1.1  2001/08/20 18:17:52  damjan
87
// Initial revision
88
//
89
// Revision 1.1  2001/08/13 03:37:07  lampret
90
// Added monitor.v and timescale.v
91
//
92
// Revision 1.1  2001/07/20 00:46:03  lampret
93
// Development version of RTL. Libraries are missing.
94
//
95
//
96
 
97
`include "or1200_defines.v"
98
`include "orpsoc_testbench_defines.v"
99
 
100
//
101
// Top of OR1200 inside test bench
102
//
103
`define OR1200_TOP orpsoc_testbench.dut.i_or1k.i_or1200_top
104
 
105
//
106
// Enable display_arch_state task
107
//
108
//`define OR1200_DISPLAY_ARCH_STATE
109
 
110
module or1200_monitor;
111
 
112
   integer fexe;
113
   reg [23:0] ref;
114
   integer    fspr;
115
   integer    fgeneral;
116
   integer    flookup;
117
   integer    r3;
118
   integer    insns;
119
 
120
   //
121
   // Initialization
122
   //
123
   initial begin
124
      ref = 0;
125
      fexe = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-executed.log"});
126
      $timeformat (-9, 2, " ns", 12);
127
      fspr = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-sprs.log"});
128
      fgeneral = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-general.log"});
129
      flookup = $fopen({`TEST_RESULTS_DIR,`TEST_NAME_STRING,"-lookup.log"});
130
      insns = 0;
131
 
132
   end
133
 
134
   //
135
   // Get GPR
136
   //
137
   task get_gpr;
138
      input     [4:0]    gpr_no;
139
      output [31:0]      gpr;
140
      integer           j;
141
      begin
142
`ifdef OR1200_RFRAM_GENERIC
143
         for(j = 0; j < 32; j = j + 1) begin
144
            gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no*32+j];
145
         end
146
`else
147
 `ifdef OR1200_XILINX_RAM32X1D
148
         gpr[0] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_0.mem[gpr_no];
149
         gpr[1] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_1.mem[gpr_no];
150
         gpr[2] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_2.mem[gpr_no];
151
         gpr[3] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_3.mem[gpr_no];
152
         gpr[4] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_4.mem[gpr_no];
153
         gpr[5] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_5.mem[gpr_no];
154
         gpr[6] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_6.mem[gpr_no];
155
         gpr[7] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_0.ram32x1d_7.mem[gpr_no];
156
         gpr[8] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_0.mem[gpr_no];
157
gpr[9] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_1.mem[gpr_no];
158
         gpr[10] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_2.mem[gpr_no];
159
gpr[11] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_3.mem[gpr_no];
160
         gpr[12] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_4.mem[gpr_no];
161
gpr[13] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_5.mem[gpr_no];
162
         gpr[14] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_6.mem[gpr_no];
163
gpr[15] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_1.ram32x1d_7.mem[gpr_no];
164
         gpr[16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_0.mem[gpr_no];
165
gpr[17] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_1.mem[gpr_no];
166
gpr[18] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_2.mem[gpr_no];
167
gpr[19] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_3.mem[gpr_no];
168
gpr[20] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_4.mem[gpr_no];
169
gpr[21] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_5.mem[gpr_no];
170
gpr[22] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_6.mem[gpr_no];
171
gpr[23] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_2.ram32x1d_7.mem[gpr_no];
172
gpr[24] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_0.mem[gpr_no];
173
gpr[25] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_1.mem[gpr_no];
174
gpr[26] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_2.mem[gpr_no];
175
gpr[27] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_3.mem[gpr_no];
176
gpr[28] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_4.mem[gpr_no];
177
gpr[29] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_5.mem[gpr_no];
178
gpr[30] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_6.mem[gpr_no];
179
gpr[31] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.xcv_ram32x8d_3.ram32x1d_7.mem[gpr_no];
180
`else
181
 `ifdef OR1200_XILINX_RAMB4
182
         for(j = 0; j < 16; j = j + 1) begin
183
            gpr[j] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_0.mem[gpr_no*16+j];
184
         end
185
for(j = 0; j < 16; j = j + 1) begin
186
   gpr[j+16] = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.ramb4_s16_1.mem[gpr_no*16+j];
187
end
188
 `else
189
  `ifdef OR1200_ARTISAN_SDP
190
  `else
191
gpr = `OR1200_TOP.or1200_cpu.or1200_rf.rf_a.mem[gpr_no];
192
  `endif
193
 `endif
194
`endif
195
`endif
196
         end
197
 endtask
198
 
199
   //
200
   // Write state of the OR1200 registers into a file
201
   //
202
   // Limitation: only a small subset of register file RAMs
203
   // are supported
204
   //
205
   task display_arch_state;
206
      reg [5:0] i;
207
      reg [31:0] r;
208
      integer    j;
209
      begin
210
`ifdef OR1200_DISPLAY_ARCH_STATE
211
         ref = ref + 1;
212
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
213
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h", insns, `OR1200_TOP.or1200_cpu.or1200_except.wb_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn);
214
         for(i = 0; i < 32; i = i + 1) begin
215
            if (i % 4 == 0)
216
              $fdisplay(fexe);
217
            get_gpr(i, r);
218
            $fwrite(fexe, "GPR%d: %h  ", i, r);
219
         end
220
         $fdisplay(fexe);
221
         r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
222
         $fwrite(fexe, "SR   : %h  ", r);
223
         r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
224
         $fwrite(fexe, "EPCR0: %h  ", r);
225
         r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
226
         $fwrite(fexe, "EEAR0: %h  ", r);
227
         r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
228
         $fdisplay(fexe, "ESR0 : %h", r);
229
         insns = insns + 1;
230
`endif
231
end
232
   endtask // display_arch_state
233
 
234
   /* Keep a trace buffer of the last lot of instructions and addresses
235
    * "executed",as read from the writeback stage, and cause a $finish if we hit
236
    * an instruction that is invalid, such as all zeros.
237
    * Currently, only breaks on an all zero instruction, but should probably be
238
    * made to break for anything with an X in it too. And of course ideally this
239
    * shouldn't be needed - but is handy if someone changes something and stops
240
    * the test continuing forever.
241
    */
242
   task monitor_for_crash;
243
      `define OR1200_MONITOR_CRASH_TRACE_SIZE 32
244
      reg [31:0] insn_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1]; //Trace buffer of 32 instructions
245
      reg [31:0] addr_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1]; //Trace buffer of the addresses of those instructions
246
      integer i;
247
 
248
     begin
249
        if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h00000000)
250
          begin
251
             $fdisplay(fgeneral, "ERROR - no instruction at PC %h", `OR1200_TOP.or1200_cpu.or1200_except.wb_pc);
252
             $fdisplay(fgeneral, "Crash trace: Last %d instructions: ",`OR1200_MONITOR_CRASH_TRACE_SIZE);
253
 
254
             $fdisplay(fgeneral, "PC\t\tINSTR");
255
             for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
256
                $fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);
257
             end
258
             #100 $finish;
259
          end
260
        else
261
          begin
262
             for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
263
                insn_trace[i] = insn_trace[i-1];
264
                addr_trace[i] = addr_trace[i-1];
265
             end
266
             insn_trace[0] = `OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn;
267
             addr_trace[0] = `OR1200_TOP.or1200_cpu.or1200_except.wb_pc;
268
          end
269
 
270
     end
271
   endtask // monitor_for_crash
272
 
273
 
274
   //
275
   // Write state of the OR1200 registers into a file; version for exception
276
   //
277
   task display_arch_state_except;
278
      reg [5:0] i;
279
      reg [31:0] r;
280
      integer    j;
281
      begin
282
`ifdef OR1200_DISPLAY_ARCH_STATE
283
         ref = ref + 1;
284
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
285
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h  (exception)", insns, `OR1200_TOP.or1200_cpu.or1200_except.ex_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.ex_insn);
286
         for(i = 0; i < 32; i = i + 1) begin
287
            if (i % 4 == 0)
288
              $fdisplay(fexe);
289
            get_gpr(i, r);
290
            $fwrite(fexe, "GPR%d: %h  ", i, r);
291
         end
292
         $fdisplay(fexe);
293
         r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
294
         $fwrite(fexe, "SR   : %h  ", r);
295
         r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
296
         $fwrite(fexe, "EPCR0: %h  ", r);
297
         r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
298
         $fwrite(fexe, "EEAR0: %h  ", r);
299
         r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
300
         $fdisplay(fexe, "ESR0 : %h", r);
301
         insns = insns + 1;
302
`endif
303
end
304
   endtask
305
 
306
   integer iwb_progress;
307
   reg [31:0] iwb_progress_addr;
308
   //
309
   // WISHBONE bus checker
310
   //
311
   always @(posedge `OR1200_TOP.iwb_clk_i)
312
     if (`OR1200_TOP.iwb_rst_i) begin
313
        iwb_progress = 0;
314
        iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
315
     end
316
     else begin
317
        if (`OR1200_TOP.iwb_cyc_o && (iwb_progress != 2)) begin
318
           iwb_progress = 1;
319
        end
320
        if (`OR1200_TOP.iwb_stb_o) begin
321
           if (iwb_progress >= 1) begin
322
              if (iwb_progress == 1)
323
                iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
324
              iwb_progress = 2;
325
           end
326
           else begin
327
              $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o raised without `OR1200_TOP.iwb_cyc_o, at %t\n", $time);
328
              #100 $finish;
329
           end
330
        end
331
        if (`OR1200_TOP.iwb_ack_i & `OR1200_TOP.iwb_err_i) begin
332
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i and `OR1200_TOP.iwb_err_i raised at the same time, at %t\n", $time);
333
        end
334
        if ((iwb_progress == 2) && (iwb_progress_addr != `OR1200_TOP.iwb_adr_o)) begin
335
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_adr_o changed while waiting for `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
336
           #100 $finish;
337
        end
338
        if (`OR1200_TOP.iwb_ack_i | `OR1200_TOP.iwb_err_i)
339
          if (iwb_progress == 2) begin
340
             iwb_progress = 0;
341
             iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
342
          end
343
          else begin
344
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
345
             #100 $finish;
346
          end
347
        if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
348
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
349
           /*                   #100 $finish;*/
350
        end
351
     end
352
 
353
   integer dwb_progress;
354
reg [31:0] dwb_progress_addr;
355
//
356
// WISHBONE bus checker
357
//
358
always @(posedge `OR1200_TOP.dwb_clk_i)
359
  if (`OR1200_TOP.dwb_rst_i)
360
    dwb_progress = 0;
361
  else begin
362
     if (`OR1200_TOP.dwb_cyc_o && (dwb_progress != 2))
363
       dwb_progress = 1;
364
     if (`OR1200_TOP.dwb_stb_o)
365
       if (dwb_progress >= 1) begin
366
          if (dwb_progress == 1)
367
            dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
368
          dwb_progress = 2;
369
       end
370
       else begin
371
          $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o raised without `OR1200_TOP.dwb_cyc_o, at %t\n", $time);
372
          #100 $finish;
373
       end
374
     if (`OR1200_TOP.dwb_ack_i & `OR1200_TOP.dwb_err_i) begin
375
        $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i and `OR1200_TOP.dwb_err_i raised at the same time, at %t\n", $time);
376
     end
377
     if ((dwb_progress == 2) && (dwb_progress_addr != `OR1200_TOP.dwb_adr_o)) begin
378
        $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_adr_o changed while waiting for `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
379
        #100 $finish;
380
     end
381
     if (`OR1200_TOP.dwb_ack_i | `OR1200_TOP.dwb_err_i)
382
       if (dwb_progress == 2) begin
383
          dwb_progress = 0;
384
          dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
385
       end
386
       else begin
387
          $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i/`OR1200_TOP.dwb_err_i raised without `OR1200_TOP.dwb_cyc_i/`OR1200_TOP.dwb_stb_i, at %t\n", $time);
388
          #100 $finish;
389
       end
390
     if ((dwb_progress == 2) && !`OR1200_TOP.dwb_stb_o) begin
391
        $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o lowered without `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
392
        #100 $finish;
393
     end
394
       end
395
 
396
//
397
// Hooks for:
398
// - displaying registers
399
// - end of simulation
400
// - access to SPRs
401
//
402
   always @(posedge `OR1200_TOP.or1200_cpu.or1200_ctrl.clk)
403
     if (!`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_freeze) begin
404
        #2;
405
        if (((`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP) || !`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn[16])
406
            && !(`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe && `OR1200_TOP.or1200_cpu.or1200_except.ex_dslot))
407
          begin
408
             display_arch_state;
409
             monitor_for_crash;
410
          end
411
        else
412
          if (`OR1200_TOP.or1200_cpu.or1200_except.except_flushpipe)
413
            display_arch_state_except;
414
        if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0001) begin // small hack to stop simulation (l.nop 1)
415
           get_gpr(3, r3);
416
           $fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
417
           $finish;
418
        end
419
        if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_000a) begin // debug if test (l.nop 10)
420
           $fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
421
`ifdef DBG_IF_MODEL
422
           xess_top.i_xess_fpga.dbg_if_model.dbg_if_test_go = 1;
423
`endif
424
        end
425
if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0002) begin // simulation reports (l.nop 2)
426
   get_gpr(3, r3);
427
   $fdisplay(fgeneral, "%t: l.nop report (%h)", $time, r3);
428
end
429
        if (`OR1200_TOP.or1200_cpu.or1200_ctrl.wb_insn == 32'h1500_0003) begin // simulation printfs (l.nop 3)
430
           get_gpr(3, r3);
431
           $fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);
432
        end
433
        if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MTSR)  // l.mtspr
434
          $fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
435
                    `OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.spr_dat_o);
436
        if (`OR1200_TOP.or1200_cpu.or1200_sprs.sprs_op == `OR1200_ALUOP_MFSR)  // l.mfspr
437
          $fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
438
                    `OR1200_TOP.or1200_cpu.or1200_sprs.spr_addr, `OR1200_TOP.or1200_cpu.or1200_sprs.to_wbmux);
439
     end
440
 
441
endmodule

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