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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [or1200_monitor.v] - Blame information for rev 789

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1 6 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3 449 julius
////  or1200_monitor.v                                            ////
4 360 julius
////                                                              ////
5
////  OR1200 processor monitor module                             ////
6
////                                                              ////
7 449 julius
////  Author(s):                                                  ////
8
////      - Damjan Lampret, lampret@opencores.org                 ////
9
////      - Julius Baxter, julius@opencores.org                   ////
10
////                                                              ////
11 360 julius
//////////////////////////////////////////////////////////////////////
12
////                                                              ////
13 348 julius
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
14 6 julius
////                                                              ////
15
//// This source file may be used and distributed without         ////
16
//// restriction provided that this copyright statement is not    ////
17
//// removed from the file and that any derivative work contains  ////
18
//// the original copyright notice and the associated disclaimer. ////
19
////                                                              ////
20
//// This source file is free software; you can redistribute it   ////
21
//// and/or modify it under the terms of the GNU Lesser General   ////
22
//// Public License as published by the Free Software Foundation; ////
23
//// either version 2.1 of the License, or (at your option) any   ////
24
//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
27
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
28
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
29
//// PURPOSE.  See the GNU Lesser General Public License for more ////
30
//// details.                                                     ////
31
////                                                              ////
32
//// You should have received a copy of the GNU Lesser General    ////
33
//// Public License along with this source; if not, download it   ////
34
//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
36
//////////////////////////////////////////////////////////////////////
37 67 julius
 
38 55 julius
`include "timescale.v"
39 6 julius
`include "or1200_defines.v"
40 485 julius
`include "or1200_monitor_defines.v"
41 360 julius
`include "test-defines.v"
42 415 julius
 
43 449 julius
 
44 6 julius
module or1200_monitor;
45
 
46
   integer fexe;
47 449 julius
   integer finsn;
48
 
49 6 julius
   reg [23:0] ref;
50 397 julius
`ifdef OR1200_MONITOR_SPRS
51 6 julius
   integer    fspr;
52 397 julius
`endif
53 6 julius
   integer    fgeneral;
54 397 julius
`ifdef OR1200_MONITOR_LOOKUP
55 6 julius
   integer    flookup;
56 397 julius
`endif
57 6 julius
   integer    r3;
58
   integer    insns;
59
 
60 348 julius
 
61 6 julius
   //
62
   // Initialization
63
   //
64
   initial begin
65
      ref = 0;
66 397 julius
`ifdef OR1200_MONITOR_EXEC_STATE
67 360 julius
      fexe = $fopen({"../out/",`TEST_NAME_STRING,"-executed.log"});
68 449 julius
`endif
69
`ifdef OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
70
      finsn = fexe;
71 397 julius
`endif
72 6 julius
      $timeformat (-9, 2, " ns", 12);
73 397 julius
`ifdef OR1200_MONITOR_SPRS
74 360 julius
      fspr = $fopen({"../out/",`TEST_NAME_STRING,"-sprs.log"});
75 397 julius
`endif
76 360 julius
      fgeneral = $fopen({"../out/",`TEST_NAME_STRING,"-general.log"});
77 397 julius
`ifdef OR1200_MONITOR_LOOKUP
78 360 julius
      flookup = $fopen({"../out/",`TEST_NAME_STRING,"-lookup.log"});
79 397 julius
`endif
80 6 julius
      insns = 0;
81
 
82
   end
83
 
84
   //
85
   // Get GPR
86
   //
87
   task get_gpr;
88
      input     [4:0]    gpr_no;
89
      output [31:0]      gpr;
90
      integer           j;
91
      begin
92 348 julius
 
93 449 julius
`ifdef OR1200_RFRAM_GENERIC
94 6 julius
         for(j = 0; j < 32; j = j + 1) begin
95 348 julius
            gpr[j] = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no*32+j];
96 6 julius
         end
97 348 julius
 
98 449 julius
`else
99 348 julius
         //gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no];
100
         gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.get_gpr(gpr_no);
101
 
102 449 julius
`endif
103 6 julius
 
104 348 julius
 
105
      end
106
   endtask
107
 
108 6 julius
   //
109
   // Write state of the OR1200 registers into a file
110
   //
111
   // Limitation: only a small subset of register file RAMs
112
   // are supported
113
   //
114
   task display_arch_state;
115
      reg [5:0] i;
116
      reg [31:0] r;
117
      integer    j;
118
      begin
119 397 julius
`ifdef OR1200_MONITOR_EXEC_STATE
120 6 julius
         ref = ref + 1;
121 397 julius
 `ifdef OR1200_MONITOR_LOOKUP
122 6 julius
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
123 397 julius
 `endif
124 351 julius
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h", insns,
125
                 `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
126
                 `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
127 449 julius
 `ifdef OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
128 351 julius
         $fwrite(fexe,"\t");
129
         // Decode the instruction, print it out
130
         or1200_print_op(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
131
 `endif
132 6 julius
         for(i = 0; i < 32; i = i + 1) begin
133
            if (i % 4 == 0)
134
              $fdisplay(fexe);
135
            get_gpr(i, r);
136
            $fwrite(fexe, "GPR%d: %h  ", i, r);
137
         end
138
         $fdisplay(fexe);
139 348 julius
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
140 6 julius
         $fwrite(fexe, "SR   : %h  ", r);
141 348 julius
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
142 6 julius
         $fwrite(fexe, "EPCR0: %h  ", r);
143 348 julius
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
144 6 julius
         $fwrite(fexe, "EEAR0: %h  ", r);
145 348 julius
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
146 6 julius
         $fdisplay(fexe, "ESR0 : %h", r);
147 397 julius
`endif //  `ifdef OR1200_MONITOR_EXEC_STATE
148 348 julius
`ifdef OR1200_DISPLAY_EXECUTED
149
         ref = ref + 1;
150 397 julius
 `ifdef OR1200_MONITOR_LOOKUP
151 348 julius
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
152 397 julius
 `endif
153 348 julius
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
154 6 julius
`endif
155 348 julius
         insns = insns + 1;
156 449 julius
      end
157 6 julius
   endtask // display_arch_state
158
 
159
   /* Keep a trace buffer of the last lot of instructions and addresses
160
    * "executed",as read from the writeback stage, and cause a $finish if we hit
161
    * an instruction that is invalid, such as all zeros.
162
    * Currently, only breaks on an all zero instruction, but should probably be
163
    * made to break for anything with an X in it too. And of course ideally this
164
    * shouldn't be needed - but is handy if someone changes something and stops
165
    * the test continuing forever.
166
    */
167 49 julius
   integer num_nul_inst;
168
   initial num_nul_inst = 0;
169 449 julius
 
170 6 julius
   task monitor_for_crash;
171 348 julius
`define OR1200_MONITOR_CRASH_TRACE_SIZE 32
172
      //Trace buffer of 32 instructions
173
      reg [31:0] insn_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
174
      //Trace buffer of the addresses of those instructions
175
      reg [31:0] addr_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
176 449 julius
      integer    i;
177 6 julius
 
178 449 julius
      begin
179
         if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h00000000)
180
           num_nul_inst = num_nul_inst + 1;
181
         else
182
           num_nul_inst = 0; // Reset it
183 49 julius
 
184 449 julius
         if (num_nul_inst == 1000) // Sat a loop a bit too long...
185
           begin
186
              $fdisplay(fgeneral, "ERROR - no instruction at PC %h",
187
                        `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc);
188
              $fdisplay(fgeneral, "Crash trace: Last %d instructions: ",
189
                        `OR1200_MONITOR_CRASH_TRACE_SIZE);
190 6 julius
 
191 449 julius
              $fdisplay(fgeneral, "PC\t\tINSTR");
192
              for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
193
                 $fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);
194
              end
195 485 julius
              $display("*");
196
              $display("* or1200_monitor : OR1200 crash detected (suspected CPU PC corruption)");
197
              $display("*");
198
 
199 449 julius
              #100 $finish;
200
           end
201
         else
202
           begin
203
              for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
204
                 insn_trace[i] = insn_trace[i-1];
205
                 addr_trace[i] = addr_trace[i-1];
206
              end
207
              insn_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn;
208
              addr_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc;
209
           end
210
 
211
      end
212 6 julius
   endtask // monitor_for_crash
213 348 julius
 
214 6 julius
 
215 348 julius
   //
216
   // Write state of the OR1200 registers into a file; version for exception
217
   //
218
   task display_arch_state_except;
219
      reg [5:0] i;
220
      reg [31:0] r;
221
      integer    j;
222
      begin
223 397 julius
`ifdef OR1200_MONITOR_EXEC_STATE
224 348 julius
         ref = ref + 1;
225 397 julius
 `ifdef OR1200_MONITOR_LOOKUP
226 348 julius
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
227 397 julius
 `endif
228 348 julius
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h  (exception)", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
229
         for(i = 0; i < 32; i = i + 1) begin
230
            if (i % 4 == 0)
231
              $fdisplay(fexe);
232
            get_gpr(i, r);
233
            $fwrite(fexe, "GPR%d: %h  ", i, r);
234
         end
235
         $fdisplay(fexe);
236
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
237
         $fwrite(fexe, "SR   : %h  ", r);
238
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
239
         $fwrite(fexe, "EPCR0: %h  ", r);
240
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
241
         $fwrite(fexe, "EEAR0: %h  ", r);
242
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
243
         $fdisplay(fexe, "ESR0 : %h", r);
244
         insns = insns + 1;
245 397 julius
`endif //  `ifdef OR1200_MONITOR_EXEC_STATE
246 348 julius
`ifdef OR1200_DISPLAY_EXECUTED
247
         ref = ref + 1;
248 397 julius
 `ifdef OR1200_MONITOR_LOOKUP
249 348 julius
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
250 397 julius
 `endif
251 348 julius
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h  (exception)", insns,
252
                 `OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc,
253
                 `OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
254
         insns = insns + 1;
255
`endif
256
 
257 449 julius
      end
258 348 julius
   endtask
259
 
260 6 julius
   integer iwb_progress;
261
   reg [31:0] iwb_progress_addr;
262
   //
263
   // WISHBONE bus checker
264
   //
265
   always @(posedge `OR1200_TOP.iwb_clk_i)
266
     if (`OR1200_TOP.iwb_rst_i) begin
267
        iwb_progress = 0;
268
        iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
269
     end
270
     else begin
271
        if (`OR1200_TOP.iwb_cyc_o && (iwb_progress != 2)) begin
272
           iwb_progress = 1;
273
        end
274
        if (`OR1200_TOP.iwb_stb_o) begin
275
           if (iwb_progress >= 1) begin
276
              if (iwb_progress == 1)
277
                iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
278
              iwb_progress = 2;
279
           end
280
           else begin
281
              $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o raised without `OR1200_TOP.iwb_cyc_o, at %t\n", $time);
282
              #100 $finish;
283
           end
284
        end
285
        if (`OR1200_TOP.iwb_ack_i & `OR1200_TOP.iwb_err_i) begin
286
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i and `OR1200_TOP.iwb_err_i raised at the same time, at %t\n", $time);
287
        end
288
        if ((iwb_progress == 2) && (iwb_progress_addr != `OR1200_TOP.iwb_adr_o)) begin
289
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_adr_o changed while waiting for `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
290
           #100 $finish;
291
        end
292
        if (`OR1200_TOP.iwb_ack_i | `OR1200_TOP.iwb_err_i)
293
          if (iwb_progress == 2) begin
294
             iwb_progress = 0;
295
             iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
296
          end
297
          else begin
298
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
299
             #100 $finish;
300
          end
301
        if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
302
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
303 348 julius
           #100 $finish;
304 6 julius
        end
305
     end
306
 
307
   integer dwb_progress;
308 449 julius
   reg [31:0] dwb_progress_addr;
309
   //
310
   // WISHBONE bus checker
311
   //
312
   always @(posedge `OR1200_TOP.dwb_clk_i)
313
     if (`OR1200_TOP.dwb_rst_i)
314
       dwb_progress = 0;
315
     else begin
316
        if (`OR1200_TOP.dwb_cyc_o && (dwb_progress != 2))
317
          dwb_progress = 1;
318
        if (`OR1200_TOP.dwb_stb_o)
319
          if (dwb_progress >= 1) begin
320
             if (dwb_progress == 1)
321
               dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
322
             dwb_progress = 2;
323
          end
324
          else begin
325
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o raised without `OR1200_TOP.dwb_cyc_o, at %t\n", $time);
326
             #100 $finish;
327
          end
328
        if (`OR1200_TOP.dwb_ack_i & `OR1200_TOP.dwb_err_i) begin
329
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i and `OR1200_TOP.dwb_err_i raised at the same time, at %t\n", $time);
330
        end
331
        if ((dwb_progress == 2) && (dwb_progress_addr != `OR1200_TOP.dwb_adr_o)) begin
332
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_adr_o changed while waiting for `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
333
           #100 $finish;
334
        end
335
        if (`OR1200_TOP.dwb_ack_i | `OR1200_TOP.dwb_err_i)
336
          if (dwb_progress == 2) begin
337
             dwb_progress = 0;
338
             dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
339
          end
340
          else begin
341
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i/`OR1200_TOP.dwb_err_i raised without `OR1200_TOP.dwb_cyc_i/`OR1200_TOP.dwb_stb_i, at %t\n", $time);
342
             #100 $finish;
343
          end
344
        if ((dwb_progress == 2) && !`OR1200_TOP.dwb_stb_o) begin
345
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o lowered without `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
346
           #100 $finish;
347
        end
348 6 julius
     end
349
 
350 449 julius
   //
351
   // Hooks for:
352
   // - displaying registers
353
   // - end of simulation
354
   // - access to SPRs
355
   //
356
   always @(posedge `CPU_CORE_CLK)
357 348 julius
     if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze) begin
358 449 julius
        //      #2;
359 348 julius
        if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP)
360
             | !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
361
            & !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &
362
                `OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot))
363 6 julius
          begin
364
             display_arch_state;
365
             monitor_for_crash;
366
          end
367
        else
368 348 julius
          if (`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe)
369 6 julius
            display_arch_state_except;
370 348 julius
        // small hack to stop simulation (l.nop 1):
371
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
372 6 julius
           get_gpr(3, r3);
373
           $fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
374 456 julius
`ifdef OR1200_MONITOR_VERBOSE_NOPS
375 789 julius
       // Note that the 'expect' scripts in or1ksim's test suite look for strings
376
       // like "exit(1)", therefore something like "exit(  1)" would fail.
377
       $display("exit(%0d)",r3);
378 456 julius
`endif
379 6 julius
           $finish;
380
        end
381 348 julius
        // debug if test (l.nop 10)
382
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
383 6 julius
           $fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
384
        end
385 348 julius
        // simulation reports (l.nop 2)
386
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
387 6 julius
           get_gpr(3, r3);
388 468 julius
           $fdisplay(fgeneral, "%t: l.nop report (0x%h)", $time, r3);
389 456 julius
`ifdef OR1200_MONITOR_VERBOSE_NOPS
390 789 julius
           // Note that the 'expect' scripts in or1ksim's test suite look for strings
391
           // like "report(0x7ffffffe);", therefore something like "report (0x7ffffffe);"
392
           // (note the extra space character) would fail.
393
           $display("report(0x%h);", r3);
394 456 julius
`endif
395 348 julius
        end
396
        // simulation printfs (l.nop 3)
397
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0003) begin
398
           get_gpr(3, r3);
399 6 julius
           $fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);
400
        end
401 348 julius
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0004) begin
402
           // simulation putc (l.nop 4)
403
           get_gpr(3, r3);
404
           $write("%c", r3);
405
           $fdisplay(fgeneral, "%t: l.nop putc (%c)", $time, r3);
406
        end
407 397 julius
`ifdef OR1200_MONITOR_SPRS
408
        if (`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
409 6 julius
          $fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
410 397 julius
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
411 348 julius
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_dat_o);
412 397 julius
        if ((|`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_cs) &
413
            !`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
414 6 julius
          $fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
415 348 julius
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
416
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.to_wbmux);
417 397 julius
`endif
418 6 julius
     end
419
 
420 348 julius
 
421 415 julius
`ifdef RAM_WB
422 439 julius
 `define RAM_WB_TOP `DUT_TOP.ram_wb0.ram_wb_b3_0
423 415 julius
   task get_insn_from_wb_ram;
424
      input [31:0] addr;
425
      output [31:0] insn;
426
      begin
427 477 julius
         insn = `RAM_WB_TOP.get_mem32(addr[31:2]);
428 415 julius
      end
429
   endtask // get_insn_from_wb_ram
430
`endif
431
 
432 348 julius
`ifdef VERSATILE_SDRAM
433 415 julius
 `define SDRAM_TOP `TB_TOP.sdram0
434 348 julius
   // Bit selects to define the bank
435
   // 32 MB part with 4 banks
436
 `define SDRAM_BANK_SEL_BITS 24:23
437
 `define SDRAM_WORD_SEL_TOP_BIT 22
438
   // Gets instruction word from correct bank
439
   task get_insn_from_sdram;
440
      input [31:0] addr;
441
      output [31:0] insn;
442
      reg [`SDRAM_WORD_SEL_TOP_BIT-1:0] word_addr;
443 449 julius
 
444 348 julius
      begin
445
         word_addr = addr[`SDRAM_WORD_SEL_TOP_BIT:2];
446
         if (addr[`SDRAM_BANK_SEL_BITS] == 2'b00)
447
           begin
448
 
449
              //$display("%t: get_insn_from_sdram bank0, word 0x%h, (%h and %h in SDRAM)", $time, word_addr, `SDRAM_TOP.Bank0[{word_addr,1'b0}], `SDRAM_TOP.Bank0[{word_addr,1'b1}]);         
450
              insn[15:0] = `SDRAM_TOP.Bank0[{word_addr,1'b1}];
451
              insn[31:16] = `SDRAM_TOP.Bank0[{word_addr,1'b0}];
452
           end
453
      end
454
 
455
   endtask // get_insn_from_sdram
456
`endif //  `ifdef VERSATILE_SDRAM
457
 
458
`ifdef XILINX_DDR2
459 415 julius
 `define DDR2_TOP `TB_TOP.gen_cs[0]
460 348 julius
   // Gets instruction word from correct bank
461
   task get_insn_from_xilinx_ddr2;
462
      input [31:0] addr;
463
      output [31:0] insn;
464 415 julius
      reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2,
465
                     ddr2_array_line3;
466 348 julius
      integer        word_in_line_num;
467
      begin
468 449 julius
         // Get our 4 128-bit chunks (8 half-words in each!! Confused yet?), 
469
         // 16 words total
470 348 julius
         `DDR2_TOP.gen[0].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line0);
471
         `DDR2_TOP.gen[1].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line1);
472
         `DDR2_TOP.gen[2].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line2);
473
         `DDR2_TOP.gen[3].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line3);
474
         case (addr[5:2])
475
           4'h0:
476
             begin
477
                insn[15:0] = ddr2_array_line0[15:0];
478
                insn[31:16] = ddr2_array_line1[15:0];
479
             end
480
           4'h1:
481
             begin
482
                insn[15:0] = ddr2_array_line2[15:0];
483
                insn[31:16] = ddr2_array_line3[15:0];
484
             end
485
           4'h2:
486
             begin
487
                insn[15:0] = ddr2_array_line0[31:16];
488
                insn[31:16] = ddr2_array_line1[31:16];
489
             end
490
           4'h3:
491
             begin
492
                insn[15:0] = ddr2_array_line2[31:16];
493
                insn[31:16] = ddr2_array_line3[31:16];
494
             end
495
           4'h4:
496
             begin
497
                insn[15:0] = ddr2_array_line0[47:32];
498
                insn[31:16] = ddr2_array_line1[47:32];
499
             end
500
           4'h5:
501
             begin
502
                insn[15:0] = ddr2_array_line2[47:32];
503
                insn[31:16] = ddr2_array_line3[47:32];
504
             end
505
           4'h6:
506
             begin
507
                insn[15:0] = ddr2_array_line0[63:48];
508
                insn[31:16] = ddr2_array_line1[63:48];
509
             end
510
           4'h7:
511
             begin
512
                insn[15:0] = ddr2_array_line2[63:48];
513
                insn[31:16] = ddr2_array_line3[63:48];
514
             end
515
           4'h8:
516
             begin
517
                insn[15:0] = ddr2_array_line0[79:64];
518
                insn[31:16] = ddr2_array_line1[79:64];
519
             end
520
           4'h9:
521
             begin
522
                insn[15:0] = ddr2_array_line2[79:64];
523
                insn[31:16] = ddr2_array_line3[79:64];
524
             end
525
           4'ha:
526
             begin
527
                insn[15:0] = ddr2_array_line0[95:80];
528
                insn[31:16] = ddr2_array_line1[95:80];
529
             end
530
           4'hb:
531
             begin
532
                insn[15:0] = ddr2_array_line2[95:80];
533
                insn[31:16] = ddr2_array_line3[95:80];
534
             end
535
           4'hc:
536
             begin
537
                insn[15:0] = ddr2_array_line0[111:96];
538
                insn[31:16] = ddr2_array_line1[111:96];
539
             end
540
           4'hd:
541
             begin
542
                insn[15:0] = ddr2_array_line2[111:96];
543
                insn[31:16] = ddr2_array_line3[111:96];
544
             end
545
           4'he:
546
             begin
547
                insn[15:0] = ddr2_array_line0[127:112];
548
                insn[31:16] = ddr2_array_line1[127:112];
549
             end
550
           4'hf:
551
             begin
552
                insn[15:0] = ddr2_array_line2[127:112];
553
                insn[31:16] = ddr2_array_line3[127:112];
554
             end
555
         endcase // case (addr[5:2])
556
      end
557
   endtask // get_insn_from_xilinx_ddr2
558
`endif
559
 
560
 
561
   task get_insn_from_memory;
562
      input [31:0] id_pc;
563
      output [31:0] insn;
564
      begin
565
         // do a decode of which server we should look in
566
         case (id_pc[31:28])
567
`ifdef VERSATILE_SDRAM
568
           4'h0:
569
             get_insn_from_sdram(id_pc, insn);
570
`endif
571
`ifdef XILINX_DDR2
572
           4'h0:
573
             get_insn_from_xilinx_ddr2(id_pc, insn);
574 415 julius
`endif
575
`ifdef RAM_WB
576
           4'h0:
577
             get_insn_from_wb_ram(id_pc, insn);
578
`endif
579 348 julius
           4'hf:
580
             // Flash isn't stored in a memory, it's an FSM so just skip/ignore
581
             insn = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn;
582
           default:
583
             begin
584
                $fdisplay(fgeneral, "%t: Unknown memory server for address 0x%h", $time,id_pc);
585
                insn = 32'hxxxxxxxx; // Unknown server
586
             end
587
         endcase // case (id_pc[31:28])
588
      end
589
   endtask // get_insn_from_memory
590
 
591
 
592 449 julius
   //
593
   // Look in the iMMU TLB MR for this address' page, if MMUs are on and enabled
594
   //
595
   task check_for_immu_entry;
596
      input [31:0] pc;
597
      output [31:0] physical_pc;
598
      output        mmu_tlb_miss;
599
      integer       w,x;
600
 
601
      reg [31:`OR1200_IMMU_PS] pc_vpn;
602
 
603
      reg [`OR1200_ITLBTRW-1:0] itlb_tr;
604
      reg [`OR1200_ITLBMRW-1:0] itlb_mr;
605
 
606
      integer                   tlb_index;
607
      reg                       mmu_en;
608
 
609
 
610
      begin
611
         mmu_tlb_miss = 0;
612
 
613
`ifdef OR1200_NO_IMMU
614
         physical_pc = pc;
615
`else
616
         mmu_en = `OR1200_TOP.`CPU_immu_top.immu_en;
617
         // If MMU is enabled
618
         if (mmu_en)
619
           begin
620
 
621
              // Look in the iTLB for mapping - get virtual page number
622
              pc_vpn = pc[31:`OR1200_IMMU_PS];
623
 
624
              tlb_index = pc[`OR1200_ITLB_INDX];
625
 
626
              // Look at the ITLB match register
627
              itlb_mr = `OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_mr_ram.mem[tlb_index];
628
 
629
              // Get the translate register here too, in case there's an error, we print it
630
              itlb_tr = `OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_tr_ram.mem[tlb_index];
631
 
632
              if ((itlb_mr[`OR1200_ITLBMR_V_BITS] === 1'b1) & (itlb_mr[`OR1200_ITLBMRW-1:1] === pc[`OR1200_ITLB_TAG]))
633
                begin
634
                   // Page number in match register matches page number of virtual PC, so get the physical
635
                   // address from the translate memory            
636
                   // Now pull the physical page number out of the tranlsate register (it's after bottom 3 bits)
637
                   physical_pc = {itlb_tr[`OR1200_ITLBTRW-1:`OR1200_ITLBTRW-(32-`OR1200_IMMU_PS)],pc[`OR1200_IMMU_PS-1:0]};
638
                   //$display("check_for_immu_entry: found match for virtual PC 0x%h in entry %d of iMMU, mr = 0x%x tr = 0x%x, phys. PC = 0x%h", pc, pc[`OR1200_ITLB_INDX], itlb_mr, itlb_tr, physical_pc);
639
                end // if ((itlb_mr[`OR1200_ITLBMR_V_BITS]) & (itlb_mr[`OR1200_ITLBMRW-1:1] == pc[`OR1200_ITLB_TAG]))
640
              else
641
                begin
642
 
643
                   // Wait a couple of clocks, see if we're doing a miss
644
                   @(posedge `CPU_CORE_CLK);
645
                   @(posedge `CPU_CORE_CLK);
646
                   if (!(`OR1200_TOP.`CPU_immu_top.miss)) // MMU should indicate miss
647
                     begin
648
                        $display("%t: check_for_immu_entry - ERROR - no match found for virtual PC 0x%h in entry %d of iMMU, mr = 0x%x tr = 0x%x, and no miss generated",
649
                                 $time, pc, pc[`OR1200_ITLB_INDX], itlb_mr, itlb_tr);
650
                        #100;
651
                        $finish;
652
                     end
653
                   else
654
                     begin
655
                        mmu_tlb_miss = 1; // Started a miss, so ignore this instruction
656
                     end
657
                end // else: !if((itlb_mr[`OR1200_ITLBMR_V_BITS]) & (itlb_mr[`OR1200_ITLBMRW-1:1] == pc[`OR1200_ITLB_TAG]))
658
 
659
           end // if (`OR1200_TOP.`CPU_immu_top.immu_en === 1'b1)
660
         else
661
           physical_pc = pc;
662
`endif // !`ifdef OR1200_NO_IMMU
663
      end
664
   endtask // check_for_immu_entry
665
 
666
 
667
   /*
668
    Instruction memory coherence checking.
669
 
670
    For new instruction executed in the pipeline - ensure it matches
671
    what is in the main program memory. Perform MMU translations if
672
    it is enabled.
673
    */
674
 
675
   reg [31:0] mem_word;
676 348 julius
   reg [31:0] last_addr = 0;
677
   reg [31:0] last_mem_word;
678 449 julius
   reg [31:0] physical_pc;
679
   reg        tlb_miss;
680
 
681 348 julius
 
682 415 julius
`ifdef MEM_COHERENCE_CHECK
683
 `define MEM_COHERENCE_TRIGGER (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_void === 1'b0)
684
 
685 449 julius
 `define INSN_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn
686
 `define PC_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_except.id_pc
687 348 julius
 
688
   // Check instruction in decode stage is what is in the RAM
689 449 julius
   always @(posedge `CPU_CORE_CLK)
690 348 julius
     begin
691 415 julius
        if (`MEM_COHERENCE_TRIGGER)
692 348 julius
          begin
693 449 julius
 
694
             check_for_immu_entry(`PC_TO_CHECK, physical_pc, tlb_miss);
695
 
696 348 julius
             // Check if it's a new PC - will also get triggered if the
697
             // instruction has changed since we last checked it
698 477 julius
             if (((physical_pc !== last_addr) ||
699
                  (last_mem_word != `INSN_TO_CHECK)) & !tlb_miss)
700 348 julius
               begin
701
                  // Decode stage not void, check instruction
702
                  // get PC
703 449 julius
                  get_insn_from_memory(physical_pc, mem_word);
704 348 julius
 
705
                  if (mem_word !== `INSN_TO_CHECK)
706
                    begin
707 477 julius
                       $fdisplay(fgeneral, "%t: Instruction mismatch for PC 0x%h (phys. 0x%h) - memory had 0x%h, CPU had 0x%h",
708
                                 $time, `PC_TO_CHECK, physical_pc, mem_word,
709
                                 `INSN_TO_CHECK);
710
                       $display("%t: Instruction mismatch for PC 0x%h (phys. 0x%h) - memory had 0x%h, CPU had 0x%h",
711
                                $time, `PC_TO_CHECK, physical_pc, mem_word,
712
                                `INSN_TO_CHECK);
713
                       #200;
714
                       $finish;
715 348 julius
                    end
716 449 julius
                  last_addr = physical_pc;
717
                  last_mem_word = mem_word;
718
 
719
               end // if (((physical_pc !== last_addr) || (last_mem_word != `INSN_TO_CHECK))...      
720
          end // if (`MEM_COHERENCE_TRIGGER)    
721
     end // always @ (posedge `CPU_CORE_CLK)
722
 
723
`endif //  `ifdef MEM_COHERENCE_CHECK
724
 
725
   // Trigger on each instruction that gets into writeback stage properly
726
   reg exception_coming1, exception_coming2, exception_here;
727
   reg will_jump, jumping, jump_dslot, jumped;
728
   reg rfe, except_during_rfe;
729
   reg dslot_expt;
730
 
731
 
732
   // Maintain a copy of GPRS for previous instruction
733
   reg [31:0] current_gprs [0:31];
734
   reg [31:0] current_epcr, current_eear, current_esr, current_sr;
735
   reg [31:0] previous_gprs [0:31];
736
   reg [31:0] previous_epcr;
737
   reg [31:0] previous_eear;
738
   reg [31:0] previous_esr;
739
   reg [31:0] previous_sr;
740
 
741
   task update_current_gprs;
742
      integer j;
743
      begin
744
         for(j=0;j<32;j=j+1)
745
           begin
746
              get_gpr(j,current_gprs[j]);
747
           end
748 491 julius
         current_sr = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr ;
749
         current_esr = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr ;
750
         current_epcr = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr ;
751
         current_eear = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear ;
752 449 julius
      end
753
   endtask
754
 
755
   task update_previous_gprs;
756
      integer j;
757
      begin
758
         for(j=0;j<32;j=j+1)
759
           begin
760
              previous_gprs[j] = current_gprs[j];
761
           end
762
         previous_sr = current_sr;
763
         previous_esr = current_esr;
764
         previous_epcr = current_epcr;
765
         previous_eear = current_eear;
766
      end
767
   endtask // update_previous_gprs
768
 
769
   // Maintain a list of addresses we expect the processor to execute
770
   // Whenever we hit a branch or jump or rfe we add to this list - when we
771
   // execute it then we remove it from the list.
772
   reg [31:0] expected_addresses [0:31];
773
   reg        expected_addresses_waiting [0:31]; // List indicating if address is waiting
774
   reg        duplicate_expected_addresses_waiting [0:31]; // List indicating if a waiting address will be cleared by the single return
775
   integer    expected_address_num;
776
   // Initialise things on reset
777
   always @(`OR1200_TOP.iwb_rst_i)
778
     begin
779
        for (expected_address_num=0;expected_address_num<32;expected_address_num=expected_address_num+1)
780
          begin
781
             expected_addresses_waiting[expected_address_num] = 0;
782
             duplicate_expected_addresses_waiting[expected_address_num] = 0;
783 348 julius
          end
784 449 julius
        expected_address_num = 0;
785
     end
786
 
787
   task add_expected_address;
788
      input [31:0] expected_pc;
789
      begin
790
         if (expected_address_num == 31)
791
           begin
792
              $display("%t: Too many branches not reached",$time);
793
              #100;
794
              $finish;
795
           end
796
         if (expected_addresses_waiting[expected_address_num])
797
           begin
798
              $display("%t: expected_addresses tracker bugged out. expected_address_num = %0d",$time,expected_address_num);
799
              #100;
800
              $finish;
801
           end
802
         else
803
           begin
804
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
805
              // Debugging output...
806
              $display("%t: Adding address 0x%h to expected list index %0d",$time, expected_pc,expected_address_num);
807
`endif
808
              // Put the expected PC in the list, increase the index
809
              expected_addresses[expected_address_num] = expected_pc;
810
              expected_addresses_waiting[expected_address_num] = 1;
811
              expected_address_num = expected_address_num + 1;
812
           end // else: !if(expected_addresses_waiting[expected_address_num])
813
      end
814
   endtask // add_address_to_expect
815
 
816
   // Use this in the case that there's an execption after a jump, in which 
817
   // case we'll have two entries when we finally jump back (the one the 
818
   // original jump put in, and the one put in by the l.rfe or l.jr/ when 
819
   // returning outside of exception handler), so mark this one as OK for 
820
   // removing the duplicate of
821
   task mark_duplicate_expected_address;
822
      begin
823
         // This will always be done on the first instruction of an exception 
824
         // that has occured after a delay slot instruction, so 
825
         // expected_address_num will be one past the entry for the one we will
826
         // get a duplicate return call for
827
         duplicate_expected_addresses_waiting[expected_address_num-1] = 1;
828
      end
829
   endtask // mark_duplicate_expected_address
830
 
831
 
832
   task check_expected_address;
833
      input [31:0] pc;
834
      input        expecting_hit;
835
      integer      i,j;
836
      reg          hit;
837
      reg          duplicates;
838 348 julius
 
839 449 julius
      begin
840
         hit = 0;
841
         //$display("%t: check_expected_addr 0x%h, index %0d",
842
         // $time,pc, expected_address_num);     
843
         if (expected_address_num > 0)
844
           begin
845
              // First check the last jump we did
846
              if (expected_addresses[expected_address_num-1] == pc)
847
                begin
848
                   // Jump address hit
849
                   // Debugging printout:
850
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
851
                   $display("%t: PC address 0x%h was in expected list, index %0d",$time, pc,expected_address_num-1);
852
`endif
853
                   expected_address_num = expected_address_num-1;
854
                   expected_addresses_waiting[expected_address_num] = 0;
855
                   hit = 1;
856
                end
857
              else
858
                begin
859
                   // Check through the list
860
                   for(i=0;i<expected_address_num;i=i+1)
861
                     begin
862
                        if (expected_addresses[i] == pc)
863
                          begin
864
                             // Jump address hit
865
                             // Debugging printout:
866
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
867
                             $display("%t: PC address 0x%h was in expected list, index %0d",$time, pc,i);
868
`endif
869
                             for(j=i;j<expected_address_num;j=j+1)
870
                               begin
871
                                  // Pull all of the ones above us down one
872
                                  expected_addresses_waiting[j]
873
                                    = expected_addresses_waiting[j+1];
874
                                  expected_addresses[j]
875
                                    = expected_addresses[j+1];
876
                                  duplicate_expected_addresses_waiting[j]
877
                                    = duplicate_expected_addresses_waiting[j+1];
878
                               end
879
                             expected_address_num = expected_address_num-1;
880
                             hit = 1;
881
                             // quit out. only allow 1 hit
882
                             i = expected_address_num;
883
                          end
884
                     end
885
                end // else: !if(expected_addresses[expected_ad...
886
           end // if (expected_address_num > 0)
887 348 julius
 
888 449 julius
         // Check for duplicates this way because of the way we've declared
889
         // the array...
890
         duplicates=0;
891
         for(i=0;i<32;i=i+1)
892
           duplicates = duplicates | duplicate_expected_addresses_waiting[i];
893
 
894
         if (hit & duplicates)
895
           begin
896
              // If we got a hit, check for duplicates we're also meant to clear
897
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
898
              $display;
899
`endif
900
              for(i=0;i<expected_address_num;i=i+1)
901
                begin
902
                   if(duplicate_expected_addresses_waiting[i] &
903
                      expected_addresses_waiting[i] &
904
                      expected_addresses[i] == pc)
905
                     begin
906
                        // Found a duplicate call address, clear it
907
                        duplicate_expected_addresses_waiting[i] = 0;
908
                        expected_addresses_waiting[i] = 0;
909
 
910
                        // Now reorder the list - pull all the ones above us
911
                        // down by one
912
                        for(j=i;j<expected_address_num;j=j+1)
913
                          begin
914
                             expected_addresses_waiting[j] = expected_addresses_waiting[j+1];
915
                             expected_addresses[j] = expected_addresses[j+1];
916
                             duplicate_expected_addresses_waiting[j] = duplicate_expected_addresses_waiting[j+1];
917
                          end
918
                        expected_address_num = expected_address_num - 1;
919
                     end
920
                end // for (i=0;i<expected_address_num;i=i+1)
921
           end // if (hit & duplicates)
922
 
923
         if (expecting_hit & !hit)
924
           begin
925
              // Expected this address to be one we're supposed to jump to, but it wasn't!
926
              $display("%t: Failed to find current PC, 0x%h, in expected PCs for branches/jumps",$time,pc);
927
              #100;
928
              $finish;
929
           end
930
 
931
      end
932
   endtask // check_expected_address
933
 
934
   // Task to assert value of GPR
935
   task assert_gpr_val;
936
      input [5:0] regnum;
937
      input [31:0] assert_value;
938
      input [31:0] pc;
939
      reg [31:0]   reg_val;
940
 
941
      begin
942
         get_gpr(regnum, reg_val);
943
         if (reg_val !== assert_value)
944
           begin
945
              $display("%t: Assert r%0d value (0x%h) = 0x%h failed. pc=0x%h",
946
                       $time, regnum, reg_val, assert_value,pc);
947
              #100;
948
              $finish;
949
           end
950
      end
951
   endtask // assert_gpr_val
952
 
953
   // Task to assert something is true
954
   task assert_this;
955
      input assert_result;
956
      input [31:0] pc;
957
      begin
958
         if (!assert_result)
959
           begin
960
              $display("%t: Assert failed for instruction at pc=0x%h",
961
                       $time , pc);
962
              #100;
963
              $finish;
964
           end
965
      end
966
   endtask // assert_gpr_val             
967
 
968
   // The jumping variable doesn't get updated until we do the proper check of
969
   // the current instruction reaching the writeback stage. We need to know
970
   // earlier, eg. in the exception checking part, if this instruction will
971
   // jump. We do that with this task.
972
   task check_for_jump;
973
      input [31:0] insn;
974
      reg [5:0]    opcode;
975
      reg          flag;
976
      begin
977
         opcode = insn[`OR1K_OPCODE_POS];
978
         // Use the flag from the previous instruction, as the decision 
979
         // is made in the execute stage not in te writeback stage, 
980
         // which is where we're getting our instructions.
981
         flag = previous_sr[`OR1200_SR_F];
982
 
983
         case (opcode)
984
           `OR1200_OR32_J,
985
             `OR1200_OR32_JR,
986
             `OR1200_OR32_JAL,
987
             `OR1200_OR32_JALR:
988
               will_jump = 1;
989
           `OR1200_OR32_BNF:
990
             will_jump = !flag;
991
           `OR1200_OR32_BF:
992
             will_jump = flag;
993
           default:
994
             will_jump = 0;
995
         endcase // case (opcode)
996
      end
997
   endtask // check_for_jump   
998
 
999
 
1000
 
1001
   // Detect exceptions from the processor here
1002
   reg [13:0] except_trig_r;
1003
   reg        exception_coming;
1004
 
1005
   always @(posedge `CPU_CORE_CLK)
1006
     if (`OR1200_TOP.iwb_rst_i)
1007
       begin
1008
          except_trig_r = 0;
1009
          exception_coming = 0;
1010
          except_during_rfe = 0;
1011
       end
1012
     else if ((|`OR1200_TOP.`CPU_cpu.`CPU_except.except_trig) && !exception_coming)
1013
       begin
1014
          exception_coming  = 1;
1015
          except_trig_r = `OR1200_TOP.`CPU_cpu.`CPU_except.except_trig;
1016
          except_during_rfe = rfe;
1017
       end
1018
 
1019
   task check_incoming_exceptions;
1020
      begin
1021
 
1022
         // Exception timing  - depends on the trigger.
1023
         // Appears to be: 
1024
         // tick timer - dslot - 1 instruction delay, else 2
1025
         // tlb lookasides - 1 instruction for both
1026
 
1027
         casex (except_trig_r)
1028
           13'b1_xxxx_xxxx_xxxx: begin
1029
              //except_type <= #1 `OR1200_EXCEPT_TICK;
1030
              exception_here = exception_coming2;
1031
              exception_coming2 = jump_dslot ? exception_coming: exception_coming1 ;
1032
              exception_coming1 = jump_dslot ? 0 : exception_coming;
1033
           end
1034
           13'b0_1xxx_xxxx_xxxx: begin
1035
              //except_type <= #1 `OR1200_EXCEPT_INT;
1036
              #1;
1037
           end
1038
           13'b0_01xx_xxxx_xxxx: begin
1039
              //except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
1040
              exception_here = exception_coming2;
1041
              exception_coming2 = jump_dslot ? exception_coming : exception_coming1 ;
1042
              exception_coming1 = jump_dslot ? 0 : exception_coming;
1043
           end
1044
           13'b0_001x_xxxx_xxxx: begin
1045
              //except_type <= #1 `OR1200_EXCEPT_IPF;
1046
              exception_here = exception_coming2;
1047
              exception_coming2 = jump_dslot ? exception_coming : exception_coming1 ;
1048
              exception_coming1 = jump_dslot ? 0 : exception_coming;
1049
           end
1050
           13'b0_0001_xxxx_xxxx: begin
1051
              //except_type <= #1 `OR1200_EXCEPT_BUSERR;
1052
              exception_here = exception_coming;
1053
              exception_coming2 = 0;
1054
              exception_coming1 = 0;
1055
           end
1056
           13'b0_0000_1xxx_xxxx: begin
1057
              //except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
1058
              if (will_jump)
1059
                begin
1060
                   // Writeback stage instruction will jump, and we have an
1061
                   // illegal instruction in the decode/execute stage, which is
1062
                   // the delay slot, so indicate the exception is coming...
1063
                   exception_here = exception_coming2;
1064
                   exception_coming2 = exception_coming;
1065
                   exception_coming1 = 0;
1066
                end
1067
              else
1068
                begin
1069
                   exception_here = jump_dslot ?
1070
                                    exception_coming2 : exception_coming;
1071
                   exception_coming2 = jump_dslot ? exception_coming : 0;
1072
                   exception_coming1 = 0;
1073
                end
1074
           end
1075
           13'b0_0000_01xx_xxxx: begin
1076
              //except_type <= #1 `OR1200_EXCEPT_ALIGN;
1077
              if(will_jump)
1078
                begin
1079
                   exception_here = exception_coming2;
1080
                   exception_coming2 = exception_coming;
1081
                   exception_coming1 = 0;
1082
                end
1083
              else
1084
                begin
1085
                   exception_here =  (rfe) ? exception_coming : exception_coming2;
1086
                   exception_coming2 = (rfe) ? 0 : exception_coming;
1087
                   exception_coming1 = 0;
1088
                end
1089
           end
1090
           13'b0_0000_001x_xxxx: begin
1091
              //except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
1092
              // Looks like except_trig goes high here after we check the
1093
              // instruction before the itlb miss after a delay slot, so we
1094
              // miss the dslot variable (it gets propegated before we call
1095
              // this task) so we use the jumped variable here to see if we
1096
              // are an exception after a delay slot          
1097
              //exception_here = (jumped | rfe) ? exception_coming : exception_coming2 ;
1098
              //exception_coming2 = (jumped | rfe) ? 0 : exception_coming;
1099
 
1100
              exception_here = (jumped | rfe) ? exception_coming : exception_coming2 ;
1101
              exception_coming2 = (jumped | rfe) ? 0 : exception_coming;
1102
 
1103
              exception_coming1 = 0;
1104
           end
1105
           13'b0_0000_0001_xxxx: begin
1106
              //except_type <= #1 `OR1200_EXCEPT_DPF;
1107
              if (jumped) begin // Jumped onto illegal instruction
1108
                 exception_here = exception_coming ;
1109
                 exception_coming2 = 0;
1110
                 exception_coming1 = 0;
1111
              end
1112
              else begin
1113
                 exception_here =  exception_coming2;
1114
                 exception_coming2 = exception_coming;
1115
                 exception_coming1 = 0;
1116
              end
1117
           end
1118
           13'b0_0000_0000_1xxx: begin  // Data Bus Error
1119
              //except_type <= #1 `OR1200_EXCEPT_BUSERR;
1120
              exception_here = exception_coming2 ;
1121
              exception_coming2 = exception_coming;
1122
              exception_coming1 = 0;
1123
           end
1124
           13'b0_0000_0000_01xx: begin
1125
              //except_type <= #1 `OR1200_EXCEPT_RANGE;
1126
              #1;
1127
           end
1128
           13'b0_0000_0000_001x: begin
1129
              // trap         
1130
              #1;
1131
           end
1132
           13'b0_0000_0000_0001: begin
1133
              //except_type <= #1 `OR1200_EXCEPT_SYSCALL;
1134
              exception_here = exception_coming2;
1135
              exception_coming2 = jumped ? exception_coming: exception_coming1 ;
1136
              exception_coming1 = jumped ? 0 : exception_coming;
1137
           end
1138
         endcase // casex (except_trig_r)
1139
 
1140
         exception_coming = 0;
1141
         except_during_rfe = 0;
1142
 
1143
      end
1144
   endtask // check_incoming_exceptions
1145
 
1146
 
1147
 
1148
 
1149 351 julius
   /////////////////////////////////////////////////////////////////////////
1150 449 julius
   // Execution tracking task
1151 351 julius
   /////////////////////////////////////////////////////////////////////////
1152 348 julius
 
1153 449 julius
 
1154
`ifdef OR1200_SYSTEM_CHECKER
1155
   always @(posedge `CPU_CORE_CLK)
1156
     begin
1157
        if (`OR1200_TOP.iwb_rst_i)
1158
          begin
1159
             exception_coming1 = 0;exception_coming2 = 0;exception_here= 0;
1160
             jumping = 0; jump_dslot = 0; jumped = 0;
1161
             rfe = 0;
1162
          end
1163
        if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze) begin
1164
           //#2 ;
1165
           // If instruction isn't a l.nop with bit 16 set (implementation's 
1166
           // filler instruction in pipeline), and do not have an exception 
1167
           // signaled with a dslot instruction in the execute stage
1168
           if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[`OR1K_OPCODE_POS] !=
1169
                 `OR1200_OR32_NOP) || !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
1170
               && !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &&
1171
                    `OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot)) // and not except start
1172
             begin
1173 351 julius
 
1174 449 julius
                // Propegate jump-tracking variables
1175
                // If was exception in delay slot, we didn't actually jump
1176
                // so don't set jumped in this case.
1177
                jumped = exception_here ? 0 : jump_dslot;
1178
                jump_dslot = jumping;
1179
                jumping = 0;
1180
                rfe = 0;
1181
 
1182
                // Now, check if current instruction will jump/branch, this is
1183
                // needed by the exception checking code, sets will_jump=1
1184
                check_for_jump(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
1185
 
1186
                // Now check if it's an exception this instruction
1187
                check_incoming_exceptions;
1188
 
1189
                // Case where we just went to an exception after a jump, so we 
1190
                // mark the address we were meant to jump to as a place which will
1191
                // have duplicate return entries in the expected address list
1192
                if (exception_here & (jumped | jump_dslot))
1193
                  begin
1194
                     $display("%t: marked as jump address with exception (dup)"
1195
                              ,$time);
1196
                     mark_duplicate_expected_address;
1197
                  end
1198
 
1199
                or1200_check_execution(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn,
1200
                                       `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
1201
                                       exception_here);
1202
                //$write("%t: pc:0x%h\t",$time,
1203
                //       `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc);
1204
                // Decode the instruction, print it out
1205
                //or1200_print_op(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn); 
1206
                //$write("\t exc:%0h dsl:%0h\n",exception_here,jump_dslot);
1207
 
1208
 
1209
 
1210
             end
1211
        end // if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze)
1212
     end // always @ (posedge `CPU_CORE_CLK)
1213
`endif
1214
 
1215
 
1216
   task or1200_check_execution;
1217
      input [31:0] insn;
1218
      input [31:0] pc;
1219
      input        exception;
1220
 
1221
      reg [5:0]    opcode;
1222
 
1223
      reg [25:0]   j_imm;
1224
      reg [25:0]   br_imm;
1225
 
1226
      reg [4:0]    rD_num, rA_num, rB_num;
1227
      reg [31:0]   rD_val, rA_val, rB_val;
1228
      reg [15:0]   imm_16bit;
1229
 
1230
      reg [15:0]   mtspr_imm;
1231
 
1232
      reg [3:0]    alu_op;
1233
      reg [1:0]    shrot_op;
1234
 
1235
      reg [5:0]    shroti_imm;
1236
 
1237
      reg [5:0]    sf_op;
1238
 
1239
      reg [5:0]    xsync_op;
1240
 
1241
      reg          flag;
1242
 
1243
      reg [31:0]   br_j_ea; // Branch/jump effective address
1244
 
1245
 
1246
      begin
1247
 
1248
         // Instruction opcode
1249
         opcode = insn[`OR1K_OPCODE_POS];
1250
         // Immediates for jump or branch instructions
1251
         j_imm = insn[`OR1K_J_BR_IMM_POS];
1252
         br_imm = insn[`OR1K_J_BR_IMM_POS];
1253
         // Register numbers (D, A and B)
1254
         rD_num = insn[`OR1K_RD_POS];
1255
         rA_num = insn[`OR1K_RA_POS];
1256
         rB_num = insn[`OR1K_RB_POS];
1257
         // Bottom 16 bits when used as immediates in various instructions
1258
         imm_16bit = insn[15:0];
1259
         // 16-bit immediate for mtspr instructions
1260
         mtspr_imm = {insn[25:21],insn[10:0]};
1261
         // ALU op for ALU instructions
1262
         alu_op = insn[`OR1K_ALU_OP_POS];
1263
         // Shift-rotate op for SHROT ALU instructions
1264
         shrot_op = insn[`OR1K_SHROT_OP_POS];
1265
         shroti_imm = insn[`OR1K_SHROTI_IMM_POS];
1266
 
1267
         // Set flag op
1268
         sf_op = insn[`OR1K_SF_OP];
1269
 
1270
         // Xsync/syscall/trap opcode
1271
         xsync_op = insn[`OR1K_XSYNC_OP_POS];
1272
 
1273
         // Use the flag from the previous instruction, as the decision 
1274
         // is made in the execute stage not in te writeback stage, 
1275
         // which is where we're getting our instructions.
1276
         flag = previous_sr[`OR1200_SR_F];
1277
 
1278
         update_current_gprs;
1279
 
1280
         // Check MSbit of the immediate, sign extend if set
1281
         br_j_ea = j_imm[25] ? pc + {4'hf,j_imm,2'b00} :
1282
                   pc + {4'h0,j_imm,2'b00};
1283
 
1284
         if (exception)
1285
           begin
1286
              $display("%t: exception - at 0x%x",$time, pc);
1287
              // get epcr, put it in the addresses we expect to jump
1288
              // back to
1289
              // Maybe DON'T do this. Because maybe in linux things we 
1290
              // interrupt out of, we don't want to execute them again?
1291
              //add_expected_address(current_epcr);
1292
           end
1293
 
1294
 
1295
         check_expected_address(pc, (jumped & !exception));
1296
 
1297
         rfe = 0;
1298
 
1299
         case (opcode)
1300
           `OR1200_OR32_J:
1301
             begin
1302
                //
1303
                // PC < - exts(Immediate < < 2) + JumpInsnAddr
1304
                //
1305
                //The immediate value is shifted left two bits, sign-extended 
1306
                // to program counter width, and then added to the address of 
1307
                // the jump instruction. The result is the effective address 
1308
                // of the jump. The program unconditionally jumps to EA with 
1309
                // a delay of one instruction.
1310
 
1311
                add_expected_address(br_j_ea);
1312
 
1313
                jumping = 1;
1314
             end
1315
           `OR1200_OR32_JAL:
1316
             begin
1317
                //
1318
                //PC < - exts(Immediate < < 2) + JumpInsnAddr
1319
                //LR < - DelayInsnAddr + 4
1320
                //
1321
                // Link reg is r9, check it is PC+8
1322
                //
1323
                add_expected_address(br_j_ea);
1324
                assert_gpr_val(9, pc+8, pc);
1325
                jumping = 1;    // 
1326
             end
1327
           `OR1200_OR32_BNF:
1328
             begin
1329
                //EA < - exts(Immediate < < 2) + BranchInsnAddr
1330
                //PC < - EA if SR[F] cleared
1331
                if (!flag)
1332
                  begin
1333
                     add_expected_address(br_j_ea);
1334
                     jumping = 1;
1335
                  end
1336
             end
1337
           `OR1200_OR32_BF:
1338
             begin
1339
                //EA < - exts(Immediate < < 2) + BranchInsnAddr
1340
                //PC < - EA if SR[F] set
1341
                if (flag)
1342
                  begin
1343
                     add_expected_address(br_j_ea);
1344
                     jumping = 1;
1345
                  end
1346
             end
1347
           `OR1200_OR32_RFE:
1348
             begin
1349
                add_expected_address(current_epcr);
1350
                // jumping variable keeps track of jumps/branches with delay 
1351
                // slot - there is none for l.rfe
1352
                rfe = 1;
1353
             end
1354
           `OR1200_OR32_JR:
1355
             begin
1356
                //PC < - rB
1357
                get_gpr(rB_num, rB_val);
1358
                add_expected_address(rB_val);
1359
                jumping = 1;
1360
             end
1361
           `OR1200_OR32_JALR:
1362
             begin
1363
                //PC < - rB
1364
                //LR < - DelayInsnAddr + 4
1365
                get_gpr(rB_num, rB_val);
1366
                add_expected_address(rB_val);
1367
                assert_gpr_val(9, pc+8, pc);
1368
                jumping = 1;
1369
             end
1370
           /*
1371
            `OR1200_OR32_LWZ,
1372
            `OR1200_OR32_LBZ,
1373
            `OR1200_OR32_LBS,
1374
            `OR1200_OR32_LHZ,
1375
            `OR1200_OR32_LHS,
1376
            `OR1200_OR32_SW,
1377
            `OR1200_OR32_SB,
1378
            `OR1200_OR32_SH:
1379
            begin
1380
            // Should result in databus access if data cache disabled
1381
            $display("%t: lsu instruction",$time);
1382
end
1383
 
1384
            `OR1200_OR32_MFSPR,
1385
            `OR1200_OR32_MTSPR:
1386
            begin
1387
            // Confirm RF values end up in the correct SPR
1388
            $display("%t: mxspr",$time);
1389
end
1390
 
1391
            `OR1200_OR32_MOVHI,
1392
            `OR1200_OR32_ADDI,
1393
            `OR1200_OR32_ADDIC,
1394
            `OR1200_OR32_ANDI,
1395
            `OR1200_OR32_ORI,
1396
            `OR1200_OR32_XORI,
1397
            `OR1200_OR32_MULI,
1398
            `OR1200_OR32_ALU:
1399
            begin
1400
            // Double check operations done on RF and immediate values
1401
            $display("%t: ALU op",$time);
1402
end
1403
 
1404
            `OR1200_OR32_SH_ROTI:
1405
            begin
1406
            // Rotate according to immediate - maybe should be in ALU ops
1407
            $display("%t: rotate op",$time);
1408
end
1409
 
1410
            `OR1200_OR32_SFXXI,
1411
            `OR1200_OR32_SFXX:
1412
            begin
1413
            // Set flag - do the check oursevles, check flag
1414
            $display("%t: set flag op",$time);
1415
end
1416
 
1417
            `OR1200_OR32_MACI,
1418
            `OR1200_OR32_MACMSB:
1419
            begin
1420
            // Either, multiply signed and accumulate, l.mac
1421
            // or multiply signed and subtract, l.msb
1422
            $display("%t: MAC op",$time);
1423
end
1424
            */
1425
 
1426
           /*default:
1427
            begin
1428
            $display("%t: Unknown opcode 0x%h at pc 0x%x\n",
1429
            $time,opcode, pc);
1430
end
1431
            */
1432
         endcase // case (opcode)
1433
 
1434
         update_previous_gprs;
1435
 
1436
      end
1437
   endtask // or1200_check_execution
1438 348 julius
 
1439 351 julius
 
1440 449 julius
   /////////////////////////////////////////////////////////////////////////
1441
   // Instruction decode task
1442
   /////////////////////////////////////////////////////////////////////////
1443 351 julius
 
1444
   task or1200_print_op;
1445
      input [31:0] insn;
1446
 
1447
      reg [5:0]    opcode;
1448
 
1449
      reg [25:0]   j_imm;
1450
      reg [25:0]   br_imm;
1451
 
1452
      reg [4:0]    rD_num, rA_num, rB_num;
1453
      reg [31:0]   rA_val, rB_val;
1454
      reg [15:0]   imm_16bit;
1455
      reg [10:0]   imm_split16bit;
1456
 
1457
      reg [3:0]    alu_op;
1458
      reg [1:0]    shrot_op;
1459
 
1460
      reg [5:0]    shroti_imm;
1461
 
1462 449 julius
      reg [5:0]    sf_op;
1463 351 julius
 
1464 449 julius
      reg [5:0]    xsync_op;
1465
 
1466 351 julius
      begin
1467
         // Instruction opcode
1468 449 julius
         opcode = insn[`OR1K_OPCODE_POS];
1469 351 julius
         // Immediates for jump or branch instructions
1470 449 julius
         j_imm = insn[`OR1K_J_BR_IMM_POS];
1471
         br_imm = insn[`OR1K_J_BR_IMM_POS];
1472 351 julius
         // Register numbers (D, A and B)
1473 449 julius
         rD_num = insn[`OR1K_RD_POS];
1474
         rA_num = insn[`OR1K_RA_POS];
1475
         rB_num = insn[`OR1K_RB_POS];
1476 351 julius
         // Bottom 16 bits when used as immediates in various instructions
1477
         imm_16bit = insn[15:0];
1478
         // Bottom 11 bits used as immediates for l.sX instructions
1479
 
1480
         // Split 16-bit immediate for l.mtspr/l.sX instructions
1481
         imm_split16bit = {insn[25:21],insn[10:0]};
1482
         // ALU op for ALU instructions
1483 449 julius
         alu_op = insn[`OR1K_ALU_OP_POS];
1484 351 julius
         // Shift-rotate op for SHROT ALU instructions
1485 449 julius
         shrot_op = insn[`OR1K_SHROT_OP_POS];
1486
         shroti_imm = insn[`OR1K_SHROTI_IMM_POS];
1487 351 julius
 
1488
         // Set flag op
1489 449 julius
         sf_op = insn[`OR1K_SF_OP];
1490 351 julius
 
1491 449 julius
         // Xsync/syscall/trap opcode
1492
         xsync_op = insn[`OR1K_XSYNC_OP_POS];
1493
 
1494 351 julius
         case (opcode)
1495
           `OR1200_OR32_J:
1496
             begin
1497 449 julius
                $fwrite(finsn,"l.j 0x%h", {j_imm,2'b00});
1498 351 julius
             end
1499
 
1500
           `OR1200_OR32_JAL:
1501
             begin
1502 449 julius
                $fwrite(finsn,"l.jal 0x%h", {j_imm,2'b00});
1503 351 julius
             end
1504
 
1505
           `OR1200_OR32_BNF:
1506
             begin
1507 449 julius
                $fwrite(finsn,"l.bnf 0x%h", {br_imm,2'b00});
1508 351 julius
             end
1509
 
1510
           `OR1200_OR32_BF:
1511
             begin
1512 449 julius
                $fwrite(finsn,"l.bf 0x%h", {br_imm,2'b00});
1513 351 julius
             end
1514
 
1515
           `OR1200_OR32_RFE:
1516
             begin
1517 449 julius
                $fwrite(finsn,"l.rfe");
1518 351 julius
             end
1519
 
1520
           `OR1200_OR32_JR:
1521
             begin
1522 449 julius
                $fwrite(finsn,"l.jr r%0d",rB_num);
1523 351 julius
             end
1524
 
1525
           `OR1200_OR32_JALR:
1526
             begin
1527 449 julius
                $fwrite(finsn,"l.jalr r%0d",rB_num);
1528 351 julius
             end
1529
 
1530
           `OR1200_OR32_LWZ:
1531
             begin
1532 449 julius
                $fwrite(finsn,"l.lwz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1533 351 julius
             end
1534
 
1535
           `OR1200_OR32_LBZ:
1536
             begin
1537 449 julius
                $fwrite(finsn,"l.lbz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1538 351 julius
             end
1539
 
1540
           `OR1200_OR32_LBS:
1541
             begin
1542 449 julius
                $fwrite(finsn,"l.lbs r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1543 351 julius
             end
1544
 
1545
           `OR1200_OR32_LHZ:
1546
             begin
1547 449 julius
                $fwrite(finsn,"l.lhz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1548 351 julius
             end
1549
 
1550
           `OR1200_OR32_LHS:
1551
             begin
1552 449 julius
                $fwrite(finsn,"l.lhs r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1553 351 julius
             end
1554
 
1555
           `OR1200_OR32_SW:
1556
             begin
1557 449 julius
                $fwrite(finsn,"l.sw 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
1558 351 julius
             end
1559
 
1560
           `OR1200_OR32_SB:
1561
             begin
1562 449 julius
                $fwrite(finsn,"l.sb 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
1563 351 julius
             end
1564
 
1565
           `OR1200_OR32_SH:
1566
             begin
1567 449 julius
                $fwrite(finsn,"l.sh 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
1568 351 julius
             end
1569
 
1570
           `OR1200_OR32_MFSPR:
1571
             begin
1572 449 julius
                $fwrite(finsn,"l.mfspr r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit,);
1573 351 julius
             end
1574
 
1575
           `OR1200_OR32_MTSPR:
1576
             begin
1577 449 julius
                $fwrite(finsn,"l.mtspr r%0d,r%0d,0x%h",rA_num,rB_num,imm_split16bit);
1578 351 julius
             end
1579
 
1580
           `OR1200_OR32_MOVHI:
1581
             begin
1582
                if (!insn[16])
1583 449 julius
                  $fwrite(finsn,"l.movhi r%0d,0x%h",rD_num,imm_16bit);
1584 351 julius
                else
1585 449 julius
                  $fwrite(finsn,"l.macrc r%0d",rD_num);
1586 351 julius
             end
1587
 
1588
           `OR1200_OR32_ADDI:
1589
             begin
1590 449 julius
                $fwrite(finsn,"l.addi r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1591 351 julius
             end
1592
 
1593
           `OR1200_OR32_ADDIC:
1594
             begin
1595 449 julius
                $fwrite(finsn,"l.addic r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1596 351 julius
             end
1597
 
1598
           `OR1200_OR32_ANDI:
1599
             begin
1600 449 julius
                $fwrite(finsn,"l.andi r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1601 351 julius
             end
1602
 
1603
           `OR1200_OR32_ORI:
1604
             begin
1605 449 julius
                $fwrite(finsn,"l.ori r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1606 351 julius
             end
1607
 
1608
           `OR1200_OR32_XORI:
1609
             begin
1610 449 julius
                $fwrite(finsn,"l.xori r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1611 351 julius
             end
1612
 
1613
           `OR1200_OR32_MULI:
1614
             begin
1615 449 julius
                $fwrite(finsn,"l.muli r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1616 351 julius
             end
1617
 
1618
           `OR1200_OR32_ALU:
1619
             begin
1620
                case(alu_op)
1621
                  `OR1200_ALUOP_ADD:
1622 449 julius
                    $fwrite(finsn,"l.add ");
1623 351 julius
                  `OR1200_ALUOP_ADDC:
1624 449 julius
                    $fwrite(finsn,"l.addc ");
1625 351 julius
                  `OR1200_ALUOP_SUB:
1626 449 julius
                    $fwrite(finsn,"l.sub ");
1627 351 julius
                  `OR1200_ALUOP_AND:
1628 449 julius
                    $fwrite(finsn,"l.and ");
1629 351 julius
                  `OR1200_ALUOP_OR:
1630 449 julius
                    $fwrite(finsn,"l.or ");
1631 351 julius
                  `OR1200_ALUOP_XOR:
1632 449 julius
                    $fwrite(finsn,"l.xor ");
1633 351 julius
                  `OR1200_ALUOP_MUL:
1634 449 julius
                    $fwrite(finsn,"l.mul ");
1635 351 julius
                  `OR1200_ALUOP_SHROT:
1636
                    begin
1637
                       case(shrot_op)
1638
                         `OR1200_SHROTOP_SLL:
1639 449 julius
                           $fwrite(finsn,"l.sll ");
1640 351 julius
                         `OR1200_SHROTOP_SRL:
1641 449 julius
                           $fwrite(finsn,"l.srl ");
1642 351 julius
                         `OR1200_SHROTOP_SRA:
1643 449 julius
                           $fwrite(finsn,"l.sra ");
1644 351 julius
                         `OR1200_SHROTOP_ROR:
1645 449 julius
                           $fwrite(finsn,"l.ror ");
1646 351 julius
                       endcase // case (shrot_op)
1647
                    end
1648
                  `OR1200_ALUOP_DIV:
1649 449 julius
                    $fwrite(finsn,"l.div ");
1650 351 julius
                  `OR1200_ALUOP_DIVU:
1651 449 julius
                    $fwrite(finsn,"l.divu ");
1652 351 julius
                  `OR1200_ALUOP_CMOV:
1653 449 julius
                    $fwrite(finsn,"l.cmov ");
1654 351 julius
                endcase // case (alu_op)
1655 449 julius
                $fwrite(finsn,"r%0d,r%0d,r%0d",rD_num,rA_num,rB_num);
1656 351 julius
             end
1657
 
1658
           `OR1200_OR32_SH_ROTI:
1659
             begin
1660
                case(shrot_op)
1661
                  `OR1200_SHROTOP_SLL:
1662 449 julius
                    $fwrite(finsn,"l.slli ");
1663 351 julius
                  `OR1200_SHROTOP_SRL:
1664 449 julius
                    $fwrite(finsn,"l.srli ");
1665 351 julius
                  `OR1200_SHROTOP_SRA:
1666 449 julius
                    $fwrite(finsn,"l.srai ");
1667 351 julius
                  `OR1200_SHROTOP_ROR:
1668 449 julius
                    $fwrite(finsn,"l.rori ");
1669 351 julius
                endcase // case (shrot_op)
1670 449 julius
                $fwrite(finsn,"r%0d,r%0d,0x%h",rD_num,rA_num,shroti_imm);
1671 351 julius
             end
1672
 
1673
           `OR1200_OR32_SFXXI:
1674
             begin
1675
                case(sf_op[2:0])
1676
                  `OR1200_COP_SFEQ:
1677 449 julius
                    $fwrite(finsn,"l.sfeqi ");
1678 351 julius
                  `OR1200_COP_SFNE:
1679 449 julius
                    $fwrite(finsn,"l.sfnei ");
1680 351 julius
                  `OR1200_COP_SFGT:
1681
                    begin
1682
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1683 449 julius
                         $fwrite(finsn,"l.sfgtsi ");
1684 351 julius
                       else
1685 449 julius
                         $fwrite(finsn,"l.sfgtui ");
1686 351 julius
                    end
1687
                  `OR1200_COP_SFGE:
1688
                    begin
1689
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1690 449 julius
                         $fwrite(finsn,"l.sfgesi ");
1691 351 julius
                       else
1692 449 julius
                         $fwrite(finsn,"l.sfgeui ");
1693 351 julius
                    end
1694
                  `OR1200_COP_SFLT:
1695
                    begin
1696
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1697 449 julius
                         $fwrite(finsn,"l.sfltsi ");
1698 351 julius
                       else
1699 449 julius
                         $fwrite(finsn,"l.sfltui ");
1700 351 julius
                    end
1701
                  `OR1200_COP_SFLE:
1702
                    begin
1703
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1704 449 julius
                         $fwrite(finsn,"l.sflesi ");
1705 351 julius
                       else
1706 449 julius
                         $fwrite(finsn,"l.sfleui ");
1707 351 julius
                    end
1708
                endcase // case (sf_op[2:0])
1709
 
1710 449 julius
                $fwrite(finsn,"r%0d,0x%h",rA_num, imm_16bit);
1711 351 julius
 
1712
             end // case: `OR1200_OR32_SFXXI
1713
 
1714
           `OR1200_OR32_SFXX:
1715
             begin
1716
                case(sf_op[2:0])
1717
                  `OR1200_COP_SFEQ:
1718 449 julius
                    $fwrite(finsn,"l.sfeq ");
1719 351 julius
                  `OR1200_COP_SFNE:
1720 449 julius
                    $fwrite(finsn,"l.sfne ");
1721 351 julius
                  `OR1200_COP_SFGT:
1722
                    begin
1723
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1724 449 julius
                         $fwrite(finsn,"l.sfgts ");
1725 351 julius
                       else
1726 449 julius
                         $fwrite(finsn,"l.sfgtu ");
1727 351 julius
                    end
1728
                  `OR1200_COP_SFGE:
1729
                    begin
1730
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1731 449 julius
                         $fwrite(finsn,"l.sfges ");
1732 351 julius
                       else
1733 449 julius
                         $fwrite(finsn,"l.sfgeu ");
1734 351 julius
                    end
1735
                  `OR1200_COP_SFLT:
1736
                    begin
1737
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1738 449 julius
                         $fwrite(finsn,"l.sflts ");
1739 351 julius
                       else
1740 449 julius
                         $fwrite(finsn,"l.sfltu ");
1741 351 julius
                    end
1742
                  `OR1200_COP_SFLE:
1743
                    begin
1744
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1745 449 julius
                         $fwrite(finsn,"l.sfles ");
1746 351 julius
                       else
1747 449 julius
                         $fwrite(finsn,"l.sfleu ");
1748 351 julius
                    end
1749
 
1750
                endcase // case (sf_op[2:0])
1751
 
1752 449 julius
                $fwrite(finsn,"r%0d,r%0d",rA_num, rB_num);
1753 351 julius
 
1754
             end
1755
 
1756
           `OR1200_OR32_MACI:
1757
             begin
1758 449 julius
                $fwrite(finsn,"l.maci r%0d,0x%h",rA_num,imm_16bit);
1759 351 julius
             end
1760
 
1761
           `OR1200_OR32_MACMSB:
1762
             begin
1763
                if(insn[3:0] == 4'h1)
1764 449 julius
                  $fwrite(finsn,"l.mac ");
1765 351 julius
                else if(insn[3:0] == 4'h2)
1766 449 julius
                  $fwrite(finsn,"l.msb ");
1767 351 julius
 
1768 449 julius
                $fwrite(finsn,"r%0d,r%0d",rA_num,rB_num);
1769 351 julius
             end
1770
 
1771
           `OR1200_OR32_NOP:
1772
             begin
1773 449 julius
                $fwrite(finsn,"l.nop 0x%0h",imm_16bit);
1774 351 julius
             end
1775
 
1776
           `OR1200_OR32_XSYNC:
1777
             begin
1778
                case (xsync_op)
1779
                  5'd0:
1780 449 julius
                    $fwrite(finsn,"l.sys 0x%h",imm_16bit);
1781 351 julius
                  5'd8:
1782 449 julius
                    $fwrite(finsn,"l.trap 0x%h",imm_16bit);
1783 351 julius
                  5'd16:
1784 449 julius
                    $fwrite(finsn,"l.msync");
1785 351 julius
                  5'd20:
1786 449 julius
                    $fwrite(finsn,"l.psync");
1787 351 julius
                  5'd24:
1788 449 julius
                    $fwrite(finsn,"l.csync");
1789 351 julius
                  default:
1790
                    begin
1791
                       $display("%t: Instruction with opcode 0x%h has bad specific type information: 0x%h",$time,opcode,insn);
1792 449 julius
                       $fwrite(finsn,"%t: Instruction with opcode 0x%h has has bad specific type information: 0x%h",$time,opcode,insn);
1793 351 julius
                    end
1794
                endcase // case (xsync_op)
1795
             end
1796
 
1797
           default:
1798
             begin
1799
                $display("%t: Unknown opcode 0x%h",$time,opcode);
1800 449 julius
                $fwrite(finsn,"%t: Unknown opcode 0x%h",$time,opcode);
1801 351 julius
             end
1802
 
1803
         endcase // case (opcode)
1804
 
1805
      end
1806
   endtask // or1200_print_op
1807
 
1808
 
1809
 
1810 6 julius
endmodule

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