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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [or1200_monitor.v] - Blame information for rev 867

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1 6 julius 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 449 julius 
////  or1200_monitor.v                                            ////
4 360 julius 
////                                                              ////
5 
////  OR1200 processor monitor module                             ////
6 
////                                                              ////
7 449 julius 
////  Author(s):                                                  ////
8 
////      - Damjan Lampret, lampret@opencores.org                 ////
9 
////      - Julius Baxter, julius@opencores.org                   ////
10 
////                                                              ////
11 360 julius 
//////////////////////////////////////////////////////////////////////
12 
////                                                              ////
13 348 julius 
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
14 6 julius 
////                                                              ////
15 
//// This source file may be used and distributed without         ////
16 
//// restriction provided that this copyright statement is not    ////
17 
//// removed from the file and that any derivative work contains  ////
18 
//// the original copyright notice and the associated disclaimer. ////
19 
////                                                              ////
20 
//// This source file is free software; you can redistribute it   ////
21 
//// and/or modify it under the terms of the GNU Lesser General   ////
22 
//// Public License as published by the Free Software Foundation; ////
23 
//// either version 2.1 of the License, or (at your option) any   ////
24 
//// later version.                                               ////
25 
////                                                              ////
26 
//// This source is distributed in the hope that it will be       ////
27 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
28 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
29 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
30 
//// details.                                                     ////
31 
////                                                              ////
32 
//// You should have received a copy of the GNU Lesser General    ////
33 
//// Public License along with this source; if not, download it   ////
34 
//// from http://www.opencores.org/lgpl.shtml                     ////
35 
////                                                              ////
36 
//////////////////////////////////////////////////////////////////////
37 67 julius 
 
38 55 julius 
`include "timescale.v"
39 6 julius 
`include "or1200_defines.v"
40 485 julius 
`include "or1200_monitor_defines.v"
41 415 julius 
 
42 449 julius 
 
43 6 julius 
module or1200_monitor;
44 
 
45 863 olof 
   parameter TEST_NAME_STRING = "unnamed";
46 
   parameter LOG_DIR          = ".";
47 
 
48 6 julius 
   integer fexe;
49 449 julius 
   integer finsn;
50 860 olof 
 
51 6 julius 
   reg [23:0] ref;
52 860 olof 
`ifdef OR1200_MONITOR_SPRS
53 6 julius 
   integer    fspr;
54 860 olof 
`endif
55 6 julius 
   integer    fgeneral;
56 397 julius 
`ifdef OR1200_MONITOR_LOOKUP
57 6 julius 
   integer    flookup;
58 860 olof 
`endif
59 6 julius 
   integer    r3;
60 
   integer    insns;
61 
 
62 863 olof 
   //Trim \0 characters from str and return a right-adjusted string
63 
   function [128*8-1:0] trim;
64 
      input [128*8-1:0] str;
65 
      integer           wpos;
66 
      integer           rpos;
67 
      begin
68 
         trim = 0;
69 
         wpos = 0;
70 
         for(rpos=0;rpos<=128*8;rpos=rpos+8)
71 
           if(str[rpos+:8] != 0) begin
72 
              trim[wpos+:8] = str[rpos+:8];
73 
              wpos = wpos +8;
74 
           end
75 
      end
76 
   endfunction
77 348 julius 
 
78 6 julius 
   //
79 
   // Initialization
80 
   //
81 863 olof 
   reg [64*8-1:0]  testcase; //Maximum 64 characters
82 
 
83 6 julius 
   initial begin
84 
      ref = 0;
85 863 olof 
      if(!$value$plusargs("testcase=%s", testcase))
86 
        testcase = TEST_NAME_STRING;
87 
 
88 860 olof 
`ifdef OR1200_MONITOR_EXEC_STATE
89 863 olof 
      fexe = $fopen(trim({LOG_DIR, "/", testcase, "-executed.log"}));
90 449 julius 
`endif
91 
`ifdef OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
92 
      finsn = fexe;
93 860 olof 
`endif
94 6 julius 
      $timeformat (-9, 2, " ns", 12);
95 860 olof 
`ifdef OR1200_MONITOR_SPRS
96 863 olof 
      fspr = $fopen(trim({LOG_DIR, "/", testcase, "-sprs.log"}));
97 860 olof 
`endif
98 863 olof 
      fgeneral = $fopen(trim({LOG_DIR, "/", testcase, "-general.log"}));
99 860 olof 
`ifdef OR1200_MONITOR_LOOKUP
100 863 olof 
      flookup = $fopen(trim({LOG_DIR, "/", testcase, "-lookup.log"}));
101 860 olof 
`endif
102 6 julius 
      insns = 0;
103 
 
104 
   end
105 
 
106 
   //
107 
   // Get GPR
108 
   //
109 
   task get_gpr;
110 
      input     [4:0]    gpr_no;
111 
      output [31:0]      gpr;
112 
      integer           j;
113 
      begin
114 348 julius 
 
115 449 julius 
`ifdef OR1200_RFRAM_GENERIC
116 6 julius 
         for(j = 0; j < 32; j = j + 1) begin
117 348 julius 
            gpr[j] = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no*32+j];
118 6 julius 
         end
119 860 olof 
 
120 449 julius 
`else
121 348 julius 
         //gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no];
122 
         gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.get_gpr(gpr_no);
123 860 olof 
 
124 449 julius 
`endif
125 6 julius 
 
126 348 julius 
 
127 
      end
128 
   endtask
129 
 
130 6 julius 
   //
131 
   // Write state of the OR1200 registers into a file
132 
   //
133 
   // Limitation: only a small subset of register file RAMs
134 
   // are supported
135 
   //
136 
   task display_arch_state;
137 864 olof 
      input exception;
138 
 
139 6 julius 
      reg [5:0] i;
140 
      reg [31:0] r;
141 
      integer    j;
142 
      begin
143 397 julius 
`ifdef OR1200_MONITOR_EXEC_STATE
144 6 julius 
         ref = ref + 1;
145 860 olof 
 `ifdef OR1200_MONITOR_LOOKUP
146 6 julius 
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
147 860 olof 
 `endif
148 864 olof 
         if(exception)
149 
           $fwrite(fexe, "\nEXECUTED(%d): %h:  %h  (exception)", insns,
150 
                   `OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc,
151 
                   `OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
152 
         else
153 
           $fwrite(fexe, "\nEXECUTED(%d): %h:  %h", insns,
154 
                   `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
155 
                   `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
156 449 julius 
 `ifdef OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
157 864 olof 
         if(!exception) begin
158 
            $fwrite(fexe,"\t");
159 
            // Decode the instruction, print it out
160 
            or1200_print_op(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
161 
         end
162 860 olof 
 `endif
163 6 julius 
         for(i = 0; i < 32; i = i + 1) begin
164 
            if (i % 4 == 0)
165 
              $fdisplay(fexe);
166 
            get_gpr(i, r);
167 
            $fwrite(fexe, "GPR%d: %h  ", i, r);
168 
         end
169 
         $fdisplay(fexe);
170 348 julius 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
171 6 julius 
         $fwrite(fexe, "SR   : %h  ", r);
172 348 julius 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
173 6 julius 
         $fwrite(fexe, "EPCR0: %h  ", r);
174 348 julius 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
175 6 julius 
         $fwrite(fexe, "EEAR0: %h  ", r);
176 348 julius 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
177 6 julius 
         $fdisplay(fexe, "ESR0 : %h", r);
178 397 julius 
`endif //  `ifdef OR1200_MONITOR_EXEC_STATE
179 348 julius 
         insns = insns + 1;
180 449 julius 
      end
181 6 julius 
   endtask // display_arch_state
182 
 
183 860 olof 
   /* Keep a trace buffer of the last lot of instructions and addresses
184 6 julius 
    * "executed",as read from the writeback stage, and cause a $finish if we hit
185 
    * an instruction that is invalid, such as all zeros.
186 860 olof 
    * Currently, only breaks on an all zero instruction, but should probably be
187 6 julius 
    * made to break for anything with an X in it too. And of course ideally this
188 
    * shouldn't be needed - but is handy if someone changes something and stops
189 
    * the test continuing forever.
190 
    */
191 49 julius 
   integer num_nul_inst;
192 
   initial num_nul_inst = 0;
193 860 olof 
 
194 6 julius 
   task monitor_for_crash;
195 348 julius 
`define OR1200_MONITOR_CRASH_TRACE_SIZE 32
196 
      //Trace buffer of 32 instructions
197 
      reg [31:0] insn_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
198 
      //Trace buffer of the addresses of those instructions
199 860 olof 
      reg [31:0] addr_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
200 449 julius 
      integer    i;
201 860 olof 
 
202 449 julius 
      begin
203 
         if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h00000000)
204 
           num_nul_inst = num_nul_inst + 1;
205 
         else
206 
           num_nul_inst = 0; // Reset it
207 49 julius 
 
208 449 julius 
         if (num_nul_inst == 1000) // Sat a loop a bit too long...
209 
           begin
210 860 olof 
              $fdisplay(fgeneral, "ERROR - no instruction at PC %h",
211 449 julius 
                        `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc);
212 
              $fdisplay(fgeneral, "Crash trace: Last %d instructions: ",
213 
                        `OR1200_MONITOR_CRASH_TRACE_SIZE);
214 6 julius 
 
215 449 julius 
              $fdisplay(fgeneral, "PC\t\tINSTR");
216 
              for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
217 
                 $fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);
218 
              end
219 860 olof 
              $display("*");
220 485 julius 
              $display("* or1200_monitor : OR1200 crash detected (suspected CPU PC corruption)");
221 860 olof 
              $display("*");
222 
 
223 449 julius 
              #100 $finish;
224 
           end
225 
         else
226 
           begin
227 
              for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
228 
                 insn_trace[i] = insn_trace[i-1];
229 
                 addr_trace[i] = addr_trace[i-1];
230 
              end
231 
              insn_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn;
232 
              addr_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc;
233 
           end
234 860 olof 
 
235 449 julius 
      end
236 6 julius 
   endtask // monitor_for_crash
237 
 
238 
   integer iwb_progress;
239 
   reg [31:0] iwb_progress_addr;
240 
   //
241 
   // WISHBONE bus checker
242 
   //
243 
   always @(posedge `OR1200_TOP.iwb_clk_i)
244 
     if (`OR1200_TOP.iwb_rst_i) begin
245 
        iwb_progress = 0;
246 
        iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
247 
     end
248 
     else begin
249 
        if (`OR1200_TOP.iwb_cyc_o && (iwb_progress != 2)) begin
250 
           iwb_progress = 1;
251 
        end
252 
        if (`OR1200_TOP.iwb_stb_o) begin
253 
           if (iwb_progress >= 1) begin
254 
              if (iwb_progress == 1)
255 860 olof 
                iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
256 6 julius 
              iwb_progress = 2;
257 
           end
258 
           else begin
259 
              $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o raised without `OR1200_TOP.iwb_cyc_o, at %t\n", $time);
260 
              #100 $finish;
261 
           end
262 
        end
263 
        if (`OR1200_TOP.iwb_ack_i & `OR1200_TOP.iwb_err_i) begin
264 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i and `OR1200_TOP.iwb_err_i raised at the same time, at %t\n", $time);
265 
        end
266 
        if ((iwb_progress == 2) && (iwb_progress_addr != `OR1200_TOP.iwb_adr_o)) begin
267 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_adr_o changed while waiting for `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
268 
           #100 $finish;
269 
        end
270 
        if (`OR1200_TOP.iwb_ack_i | `OR1200_TOP.iwb_err_i)
271 
          if (iwb_progress == 2) begin
272 
             iwb_progress = 0;
273 
             iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
274 
          end
275 
          else begin
276 
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
277 
             #100 $finish;
278 
          end
279 
        if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
280 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
281 348 julius 
           #100 $finish;
282 6 julius 
        end
283 
     end
284 
 
285 
   integer dwb_progress;
286 449 julius 
   reg [31:0] dwb_progress_addr;
287 
   //
288 
   // WISHBONE bus checker
289 
   //
290 
   always @(posedge `OR1200_TOP.dwb_clk_i)
291 
     if (`OR1200_TOP.dwb_rst_i)
292 
       dwb_progress = 0;
293 
     else begin
294 
        if (`OR1200_TOP.dwb_cyc_o && (dwb_progress != 2))
295 
          dwb_progress = 1;
296 
        if (`OR1200_TOP.dwb_stb_o)
297 
          if (dwb_progress >= 1) begin
298 
             if (dwb_progress == 1)
299 860 olof 
               dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
300 449 julius 
             dwb_progress = 2;
301 
          end
302 
          else begin
303 
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o raised without `OR1200_TOP.dwb_cyc_o, at %t\n", $time);
304 
             #100 $finish;
305 
          end
306 
        if (`OR1200_TOP.dwb_ack_i & `OR1200_TOP.dwb_err_i) begin
307 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i and `OR1200_TOP.dwb_err_i raised at the same time, at %t\n", $time);
308 
        end
309 
        if ((dwb_progress == 2) && (dwb_progress_addr != `OR1200_TOP.dwb_adr_o)) begin
310 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_adr_o changed while waiting for `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
311 
           #100 $finish;
312 
        end
313 
        if (`OR1200_TOP.dwb_ack_i | `OR1200_TOP.dwb_err_i)
314 
          if (dwb_progress == 2) begin
315 
             dwb_progress = 0;
316 
             dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
317 
          end
318 
          else begin
319 
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i/`OR1200_TOP.dwb_err_i raised without `OR1200_TOP.dwb_cyc_i/`OR1200_TOP.dwb_stb_i, at %t\n", $time);
320 
             #100 $finish;
321 
          end
322 
        if ((dwb_progress == 2) && !`OR1200_TOP.dwb_stb_o) begin
323 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o lowered without `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
324 
           #100 $finish;
325 
        end
326 6 julius 
     end
327 
 
328 449 julius 
   //
329 
   // Hooks for:
330 
   // - displaying registers
331 
   // - end of simulation
332 
   // - access to SPRs
333 
   //
334 
   always @(posedge `CPU_CORE_CLK)
335 348 julius 
     if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze) begin
336 449 julius 
        //      #2;
337 348 julius 
        if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP)
338 
             | !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
339 860 olof 
            & !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &
340 348 julius 
                `OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot))
341 6 julius 
          begin
342 864 olof 
             display_arch_state(0);
343 6 julius 
             monitor_for_crash;
344 
          end
345 
        else
346 348 julius 
          if (`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe)
347 864 olof 
            display_arch_state(1);
348 348 julius 
        // small hack to stop simulation (l.nop 1):
349 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
350 6 julius 
           get_gpr(3, r3);
351 
           $fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
352 456 julius 
`ifdef OR1200_MONITOR_VERBOSE_NOPS
353 789 julius 
       // Note that the 'expect' scripts in or1ksim's test suite look for strings
354 
       // like "exit(1)", therefore something like "exit(  1)" would fail.
355 
       $display("exit(%0d)",r3);
356 860 olof 
`endif
357 6 julius 
           $finish;
358 
        end
359 348 julius 
        // debug if test (l.nop 10)
360 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
361 6 julius 
           $fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
362 
        end
363 348 julius 
        // simulation reports (l.nop 2)
364 860 olof 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
365 6 julius 
           get_gpr(3, r3);
366 468 julius 
           $fdisplay(fgeneral, "%t: l.nop report (0x%h)", $time, r3);
367 456 julius 
`ifdef OR1200_MONITOR_VERBOSE_NOPS
368 789 julius 
           // Note that the 'expect' scripts in or1ksim's test suite look for strings
369 
           // like "report(0x7ffffffe);", therefore something like "report (0x7ffffffe);"
370 
           // (note the extra space character) would fail.
371 
           $display("report(0x%h);", r3);
372 456 julius 
`endif
373 348 julius 
        end
374 
        // simulation printfs (l.nop 3)
375 860 olof 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0003) begin
376 348 julius 
           get_gpr(3, r3);
377 6 julius 
           $fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);
378 
        end
379 860 olof 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0004) begin
380 348 julius 
           // simulation putc (l.nop 4)
381 
           get_gpr(3, r3);
382 
           $write("%c", r3);
383 
           $fdisplay(fgeneral, "%t: l.nop putc (%c)", $time, r3);
384 
        end
385 860 olof 
`ifdef OR1200_MONITOR_SPRS
386 397 julius 
        if (`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
387 6 julius 
          $fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
388 397 julius 
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
389 348 julius 
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_dat_o);
390 860 olof 
        if ((|`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_cs) &
391 397 julius 
            !`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
392 6 julius 
          $fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
393 860 olof 
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
394 348 julius 
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.to_wbmux);
395 860 olof 
`endif
396 6 julius 
     end
397 
 
398 348 julius 
 
399 415 julius 
`ifdef RAM_WB
400 439 julius 
 `define RAM_WB_TOP `DUT_TOP.ram_wb0.ram_wb_b3_0
401 415 julius 
   task get_insn_from_wb_ram;
402 
      input [31:0] addr;
403 
      output [31:0] insn;
404 
      begin
405 477 julius 
         insn = `RAM_WB_TOP.get_mem32(addr[31:2]);
406 415 julius 
      end
407 
   endtask // get_insn_from_wb_ram
408 
`endif
409 860 olof 
 
410 348 julius 
`ifdef VERSATILE_SDRAM
411 415 julius 
 `define SDRAM_TOP `TB_TOP.sdram0
412 348 julius 
   // Bit selects to define the bank
413 
   // 32 MB part with 4 banks
414 
 `define SDRAM_BANK_SEL_BITS 24:23
415 
 `define SDRAM_WORD_SEL_TOP_BIT 22
416 
   // Gets instruction word from correct bank
417 
   task get_insn_from_sdram;
418 
      input [31:0] addr;
419 
      output [31:0] insn;
420 
      reg [`SDRAM_WORD_SEL_TOP_BIT-1:0] word_addr;
421 860 olof 
 
422 348 julius 
      begin
423 860 olof 
         word_addr = addr[`SDRAM_WORD_SEL_TOP_BIT:2];
424 348 julius 
         if (addr[`SDRAM_BANK_SEL_BITS] == 2'b00)
425 
           begin
426 860 olof 
 
427 
              //$display("%t: get_insn_from_sdram bank0, word 0x%h, (%h and %h in SDRAM)", $time, word_addr, `SDRAM_TOP.Bank0[{word_addr,1'b0}], `SDRAM_TOP.Bank0[{word_addr,1'b1}]);
428 348 julius 
              insn[15:0] = `SDRAM_TOP.Bank0[{word_addr,1'b1}];
429 
              insn[31:16] = `SDRAM_TOP.Bank0[{word_addr,1'b0}];
430 
           end
431 
      end
432 860 olof 
 
433 348 julius 
   endtask // get_insn_from_sdram
434 
`endif //  `ifdef VERSATILE_SDRAM
435 
 
436 
`ifdef XILINX_DDR2
437 415 julius 
 `define DDR2_TOP `TB_TOP.gen_cs[0]
438 348 julius 
   // Gets instruction word from correct bank
439 
   task get_insn_from_xilinx_ddr2;
440 
      input [31:0] addr;
441 
      output [31:0] insn;
442 415 julius 
      reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2,
443 
                     ddr2_array_line3;
444 860 olof 
      integer        word_in_line_num;
445 348 julius 
      begin
446 860 olof 
         // Get our 4 128-bit chunks (8 half-words in each!! Confused yet?),
447 449 julius 
         // 16 words total
448 348 julius 
         `DDR2_TOP.gen[0].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line0);
449 
         `DDR2_TOP.gen[1].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line1);
450 
         `DDR2_TOP.gen[2].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line2);
451 
         `DDR2_TOP.gen[3].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line3);
452 
         case (addr[5:2])
453 
           4'h0:
454 
             begin
455 
                insn[15:0] = ddr2_array_line0[15:0];
456 
                insn[31:16] = ddr2_array_line1[15:0];
457 
             end
458 
           4'h1:
459 
             begin
460 
                insn[15:0] = ddr2_array_line2[15:0];
461 
                insn[31:16] = ddr2_array_line3[15:0];
462 
             end
463 
           4'h2:
464 
             begin
465 
                insn[15:0] = ddr2_array_line0[31:16];
466 
                insn[31:16] = ddr2_array_line1[31:16];
467 
             end
468 
           4'h3:
469 
             begin
470 
                insn[15:0] = ddr2_array_line2[31:16];
471 
                insn[31:16] = ddr2_array_line3[31:16];
472 
             end
473 
           4'h4:
474 
             begin
475 
                insn[15:0] = ddr2_array_line0[47:32];
476 
                insn[31:16] = ddr2_array_line1[47:32];
477 
             end
478 
           4'h5:
479 
             begin
480 
                insn[15:0] = ddr2_array_line2[47:32];
481 
                insn[31:16] = ddr2_array_line3[47:32];
482 
             end
483 
           4'h6:
484 
             begin
485 
                insn[15:0] = ddr2_array_line0[63:48];
486 
                insn[31:16] = ddr2_array_line1[63:48];
487 
             end
488 
           4'h7:
489 
             begin
490 
                insn[15:0] = ddr2_array_line2[63:48];
491 
                insn[31:16] = ddr2_array_line3[63:48];
492 
             end
493 
           4'h8:
494 
             begin
495 
                insn[15:0] = ddr2_array_line0[79:64];
496 
                insn[31:16] = ddr2_array_line1[79:64];
497 
             end
498 
           4'h9:
499 
             begin
500 
                insn[15:0] = ddr2_array_line2[79:64];
501 
                insn[31:16] = ddr2_array_line3[79:64];
502 
             end
503 
           4'ha:
504 
             begin
505 
                insn[15:0] = ddr2_array_line0[95:80];
506 
                insn[31:16] = ddr2_array_line1[95:80];
507 
             end
508 
           4'hb:
509 
             begin
510 
                insn[15:0] = ddr2_array_line2[95:80];
511 
                insn[31:16] = ddr2_array_line3[95:80];
512 
             end
513 
           4'hc:
514 
             begin
515 
                insn[15:0] = ddr2_array_line0[111:96];
516 
                insn[31:16] = ddr2_array_line1[111:96];
517 
             end
518 
           4'hd:
519 
             begin
520 
                insn[15:0] = ddr2_array_line2[111:96];
521 
                insn[31:16] = ddr2_array_line3[111:96];
522 
             end
523 
           4'he:
524 
             begin
525 
                insn[15:0] = ddr2_array_line0[127:112];
526 
                insn[31:16] = ddr2_array_line1[127:112];
527 
             end
528 
           4'hf:
529 
             begin
530 
                insn[15:0] = ddr2_array_line2[127:112];
531 
                insn[31:16] = ddr2_array_line3[127:112];
532 860 olof 
             end
533 348 julius 
         endcase // case (addr[5:2])
534 
      end
535 
   endtask // get_insn_from_xilinx_ddr2
536 860 olof 
`endif
537 
 
538 
 
539 348 julius 
   task get_insn_from_memory;
540 
      input [31:0] id_pc;
541 
      output [31:0] insn;
542 
      begin
543 
         // do a decode of which server we should look in
544 
         case (id_pc[31:28])
545 
`ifdef VERSATILE_SDRAM
546 
           4'h0:
547 
             get_insn_from_sdram(id_pc, insn);
548 
`endif
549 
`ifdef XILINX_DDR2
550 
           4'h0:
551 
             get_insn_from_xilinx_ddr2(id_pc, insn);
552 415 julius 
`endif
553 
`ifdef RAM_WB
554 
           4'h0:
555 
             get_insn_from_wb_ram(id_pc, insn);
556 860 olof 
`endif
557 348 julius 
           4'hf:
558 
             // Flash isn't stored in a memory, it's an FSM so just skip/ignore
559 
             insn = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn;
560 
           default:
561 
             begin
562 
                $fdisplay(fgeneral, "%t: Unknown memory server for address 0x%h", $time,id_pc);
563 
                insn = 32'hxxxxxxxx; // Unknown server
564 
             end
565 
         endcase // case (id_pc[31:28])
566 
      end
567 
   endtask // get_insn_from_memory
568 
 
569 860 olof 
 
570 449 julius 
   //
571 
   // Look in the iMMU TLB MR for this address' page, if MMUs are on and enabled
572 
   //
573 
   task check_for_immu_entry;
574 
      input [31:0] pc;
575 
      output [31:0] physical_pc;
576 860 olof 
      output        mmu_tlb_miss;
577 449 julius 
      integer       w,x;
578 
 
579 
      reg [31:`OR1200_IMMU_PS] pc_vpn;
580 860 olof 
 
581 449 julius 
      reg [`OR1200_ITLBTRW-1:0] itlb_tr;
582 
      reg [`OR1200_ITLBMRW-1:0] itlb_mr;
583 
 
584 
      integer                   tlb_index;
585 
      reg                       mmu_en;
586 860 olof 
 
587 
 
588 449 julius 
      begin
589 
         mmu_tlb_miss = 0;
590 860 olof 
 
591 449 julius 
`ifdef OR1200_NO_IMMU
592 
         physical_pc = pc;
593 
`else
594 
         mmu_en = `OR1200_TOP.`CPU_immu_top.immu_en;
595 
         // If MMU is enabled
596 
         if (mmu_en)
597 
           begin
598 860 olof 
 
599 449 julius 
              // Look in the iTLB for mapping - get virtual page number
600 
              pc_vpn = pc[31:`OR1200_IMMU_PS];
601 
 
602 860 olof 
              tlb_index = pc[`OR1200_ITLB_INDX];
603 
 
604 449 julius 
              // Look at the ITLB match register
605 
              itlb_mr = `OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_mr_ram.mem[tlb_index];
606 
 
607 
              // Get the translate register here too, in case there's an error, we print it
608 
              itlb_tr = `OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_tr_ram.mem[tlb_index];
609 860 olof 
 
610 449 julius 
              if ((itlb_mr[`OR1200_ITLBMR_V_BITS] === 1'b1) & (itlb_mr[`OR1200_ITLBMRW-1:1] === pc[`OR1200_ITLB_TAG]))
611 
                begin
612 
                   // Page number in match register matches page number of virtual PC, so get the physical
613 860 olof 
                   // address from the translate memory
614 449 julius 
                   // Now pull the physical page number out of the tranlsate register (it's after bottom 3 bits)
615 
                   physical_pc = {itlb_tr[`OR1200_ITLBTRW-1:`OR1200_ITLBTRW-(32-`OR1200_IMMU_PS)],pc[`OR1200_IMMU_PS-1:0]};
616 
                   //$display("check_for_immu_entry: found match for virtual PC 0x%h in entry %d of iMMU, mr = 0x%x tr = 0x%x, phys. PC = 0x%h", pc, pc[`OR1200_ITLB_INDX], itlb_mr, itlb_tr, physical_pc);
617 
                end // if ((itlb_mr[`OR1200_ITLBMR_V_BITS]) & (itlb_mr[`OR1200_ITLBMRW-1:1] == pc[`OR1200_ITLB_TAG]))
618 
              else
619 
                begin
620 
 
621 
                   // Wait a couple of clocks, see if we're doing a miss
622 
                   @(posedge `CPU_CORE_CLK);
623 
                   @(posedge `CPU_CORE_CLK);
624 
                   if (!(`OR1200_TOP.`CPU_immu_top.miss)) // MMU should indicate miss
625 
                     begin
626 
                        $display("%t: check_for_immu_entry - ERROR - no match found for virtual PC 0x%h in entry %d of iMMU, mr = 0x%x tr = 0x%x, and no miss generated",
627 
                                 $time, pc, pc[`OR1200_ITLB_INDX], itlb_mr, itlb_tr);
628 
                        #100;
629 
                        $finish;
630 
                     end
631 
                   else
632 
                     begin
633 
                        mmu_tlb_miss = 1; // Started a miss, so ignore this instruction
634 
                     end
635 
                end // else: !if((itlb_mr[`OR1200_ITLBMR_V_BITS]) & (itlb_mr[`OR1200_ITLBMRW-1:1] == pc[`OR1200_ITLB_TAG]))
636 860 olof 
 
637 449 julius 
           end // if (`OR1200_TOP.`CPU_immu_top.immu_en === 1'b1)
638 
         else
639 
           physical_pc = pc;
640 
`endif // !`ifdef OR1200_NO_IMMU
641 
      end
642 
   endtask // check_for_immu_entry
643 
 
644 860 olof 
 
645 449 julius 
   /*
646 
    Instruction memory coherence checking.
647 860 olof 
 
648 449 julius 
    For new instruction executed in the pipeline - ensure it matches
649 
    what is in the main program memory. Perform MMU translations if
650 
    it is enabled.
651 
    */
652 860 olof 
 
653 449 julius 
   reg [31:0] mem_word;
654 348 julius 
   reg [31:0] last_addr = 0;
655 
   reg [31:0] last_mem_word;
656 449 julius 
   reg [31:0] physical_pc;
657 860 olof 
   reg        tlb_miss;
658 348 julius 
 
659 860 olof 
 
660 415 julius 
`ifdef MEM_COHERENCE_CHECK
661 
 `define MEM_COHERENCE_TRIGGER (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_void === 1'b0)
662 
 
663 449 julius 
 `define INSN_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn
664 
 `define PC_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_except.id_pc
665 860 olof 
 
666 348 julius 
   // Check instruction in decode stage is what is in the RAM
667 449 julius 
   always @(posedge `CPU_CORE_CLK)
668 348 julius 
     begin
669 415 julius 
        if (`MEM_COHERENCE_TRIGGER)
670 348 julius 
          begin
671 860 olof 
 
672 449 julius 
             check_for_immu_entry(`PC_TO_CHECK, physical_pc, tlb_miss);
673 860 olof 
 
674 348 julius 
             // Check if it's a new PC - will also get triggered if the
675 
             // instruction has changed since we last checked it
676 860 olof 
             if (((physical_pc !== last_addr) ||
677 477 julius 
                  (last_mem_word != `INSN_TO_CHECK)) & !tlb_miss)
678 348 julius 
               begin
679 
                  // Decode stage not void, check instruction
680 
                  // get PC
681 449 julius 
                  get_insn_from_memory(physical_pc, mem_word);
682 348 julius 
 
683 
                  if (mem_word !== `INSN_TO_CHECK)
684 
                    begin
685 860 olof 
                       $fdisplay(fgeneral, "%t: Instruction mismatch for PC 0x%h (phys. 0x%h) - memory had 0x%h, CPU had 0x%h",
686 
                                 $time, `PC_TO_CHECK, physical_pc, mem_word,
687 477 julius 
                                 `INSN_TO_CHECK);
688 860 olof 
                       $display("%t: Instruction mismatch for PC 0x%h (phys. 0x%h) - memory had 0x%h, CPU had 0x%h",
689 
                                $time, `PC_TO_CHECK, physical_pc, mem_word,
690 477 julius 
                                `INSN_TO_CHECK);
691 
                       #200;
692 860 olof 
                       $finish;
693 348 julius 
                    end
694 449 julius 
                  last_addr = physical_pc;
695 860 olof 
                  last_mem_word = mem_word;
696 
 
697 
               end // if (((physical_pc !== last_addr) || (last_mem_word != `INSN_TO_CHECK))...
698 
          end // if (`MEM_COHERENCE_TRIGGER)
699 449 julius 
     end // always @ (posedge `CPU_CORE_CLK)
700 860 olof 
 
701 449 julius 
`endif //  `ifdef MEM_COHERENCE_CHECK
702 860 olof 
 
703 449 julius 
   // Trigger on each instruction that gets into writeback stage properly
704 
   reg exception_coming1, exception_coming2, exception_here;
705 
   reg will_jump, jumping, jump_dslot, jumped;
706 
   reg rfe, except_during_rfe;
707 
   reg dslot_expt;
708 
 
709 860 olof 
 
710 449 julius 
   // Maintain a copy of GPRS for previous instruction
711 
   reg [31:0] current_gprs [0:31];
712 860 olof 
   reg [31:0] current_epcr, current_eear, current_esr, current_sr;
713 449 julius 
   reg [31:0] previous_gprs [0:31];
714 
   reg [31:0] previous_epcr;
715 
   reg [31:0] previous_eear;
716 
   reg [31:0] previous_esr;
717 
   reg [31:0] previous_sr;
718 860 olof 
 
719 
   task update_current_gprs;
720 449 julius 
      integer j;
721 
      begin
722 
         for(j=0;j<32;j=j+1)
723 
           begin
724 
              get_gpr(j,current_gprs[j]);
725 
           end
726 491 julius 
         current_sr = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr ;
727 
         current_esr = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr ;
728 
         current_epcr = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr ;
729 
         current_eear = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear ;
730 449 julius 
      end
731 
   endtask
732 860 olof 
 
733 
   task update_previous_gprs;
734 449 julius 
      integer j;
735 
      begin
736 
         for(j=0;j<32;j=j+1)
737 
           begin
738 
              previous_gprs[j] = current_gprs[j];
739 
           end
740 860 olof 
         previous_sr = current_sr;
741 
         previous_esr = current_esr;
742 
         previous_epcr = current_epcr;
743 449 julius 
         previous_eear = current_eear;
744 
      end
745 
   endtask // update_previous_gprs
746 860 olof 
 
747 449 julius 
   // Maintain a list of addresses we expect the processor to execute
748 
   // Whenever we hit a branch or jump or rfe we add to this list - when we
749 
   // execute it then we remove it from the list.
750 
   reg [31:0] expected_addresses [0:31];
751 
   reg        expected_addresses_waiting [0:31]; // List indicating if address is waiting
752 
   reg        duplicate_expected_addresses_waiting [0:31]; // List indicating if a waiting address will be cleared by the single return
753 
   integer    expected_address_num;
754 
   // Initialise things on reset
755 
   always @(`OR1200_TOP.iwb_rst_i)
756 
     begin
757 
        for (expected_address_num=0;expected_address_num<32;expected_address_num=expected_address_num+1)
758 860 olof 
          begin
759 449 julius 
             expected_addresses_waiting[expected_address_num] = 0;
760 
             duplicate_expected_addresses_waiting[expected_address_num] = 0;
761 348 julius 
          end
762 449 julius 
        expected_address_num = 0;
763 
     end
764 860 olof 
 
765 
   task add_expected_address;
766 449 julius 
      input [31:0] expected_pc;
767 
      begin
768 
         if (expected_address_num == 31)
769 
           begin
770 
              $display("%t: Too many branches not reached",$time);
771 860 olof 
              #100;
772 449 julius 
              $finish;
773 
           end
774 
         if (expected_addresses_waiting[expected_address_num])
775 
           begin
776 
              $display("%t: expected_addresses tracker bugged out. expected_address_num = %0d",$time,expected_address_num);
777 860 olof 
              #100;
778 449 julius 
              $finish;
779 
           end
780 
         else
781 
           begin
782 860 olof 
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
783 449 julius 
              // Debugging output...
784 
              $display("%t: Adding address 0x%h to expected list index %0d",$time, expected_pc,expected_address_num);
785 860 olof 
`endif
786 449 julius 
              // Put the expected PC in the list, increase the index
787 
              expected_addresses[expected_address_num] = expected_pc;
788 
              expected_addresses_waiting[expected_address_num] = 1;
789 
              expected_address_num = expected_address_num + 1;
790 
           end // else: !if(expected_addresses_waiting[expected_address_num])
791 
      end
792 
   endtask // add_address_to_expect
793 
 
794 860 olof 
   // Use this in the case that there's an execption after a jump, in which
795 
   // case we'll have two entries when we finally jump back (the one the
796 
   // original jump put in, and the one put in by the l.rfe or l.jr/ when
797 
   // returning outside of exception handler), so mark this one as OK for
798 449 julius 
   // removing the duplicate of
799 
   task mark_duplicate_expected_address;
800 
      begin
801 860 olof 
         // This will always be done on the first instruction of an exception
802 
         // that has occured after a delay slot instruction, so
803 449 julius 
         // expected_address_num will be one past the entry for the one we will
804 
         // get a duplicate return call for
805 
         duplicate_expected_addresses_waiting[expected_address_num-1] = 1;
806 
      end
807 
   endtask // mark_duplicate_expected_address
808 
 
809 860 olof 
 
810 449 julius 
   task check_expected_address;
811 
      input [31:0] pc;
812 
      input        expecting_hit;
813 
      integer      i,j;
814 
      reg          hit;
815 
      reg          duplicates;
816 860 olof 
 
817 449 julius 
      begin
818 
         hit = 0;
819 
         //$display("%t: check_expected_addr 0x%h, index %0d",
820 860 olof 
         // $time,pc, expected_address_num);
821 449 julius 
         if (expected_address_num > 0)
822 
           begin
823 
              // First check the last jump we did
824 
              if (expected_addresses[expected_address_num-1] == pc)
825 
                begin
826 
                   // Jump address hit
827 
                   // Debugging printout:
828 
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
829 
                   $display("%t: PC address 0x%h was in expected list, index %0d",$time, pc,expected_address_num-1);
830 860 olof 
`endif
831 449 julius 
                   expected_address_num = expected_address_num-1;
832 
                   expected_addresses_waiting[expected_address_num] = 0;
833 
                   hit = 1;
834 
                end
835 
              else
836 
                begin
837 
                   // Check through the list
838 
                   for(i=0;i<expected_address_num;i=i+1)
839 
                     begin
840 
                        if (expected_addresses[i] == pc)
841 
                          begin
842 
                             // Jump address hit
843 
                             // Debugging printout:
844 860 olof 
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
845 449 julius 
                             $display("%t: PC address 0x%h was in expected list, index %0d",$time, pc,i);
846 860 olof 
`endif
847 449 julius 
                             for(j=i;j<expected_address_num;j=j+1)
848 
                               begin
849 
                                  // Pull all of the ones above us down one
850 860 olof 
                                  expected_addresses_waiting[j]
851 449 julius 
                                    = expected_addresses_waiting[j+1];
852 860 olof 
                                  expected_addresses[j]
853 449 julius 
                                    = expected_addresses[j+1];
854 860 olof 
                                  duplicate_expected_addresses_waiting[j]
855 449 julius 
                                    = duplicate_expected_addresses_waiting[j+1];
856 
                               end
857 
                             expected_address_num = expected_address_num-1;
858 
                             hit = 1;
859 
                             // quit out. only allow 1 hit
860 
                             i = expected_address_num;
861 
                          end
862 
                     end
863 
                end // else: !if(expected_addresses[expected_ad...
864 
           end // if (expected_address_num > 0)
865 348 julius 
 
866 449 julius 
         // Check for duplicates this way because of the way we've declared
867 
         // the array...
868 860 olof 
         duplicates=0;
869 449 julius 
         for(i=0;i<32;i=i+1)
870 
           duplicates = duplicates | duplicate_expected_addresses_waiting[i];
871 860 olof 
 
872 449 julius 
         if (hit & duplicates)
873 
           begin
874 
              // If we got a hit, check for duplicates we're also meant to clear
875 860 olof 
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
876 449 julius 
              $display;
877 860 olof 
`endif
878 449 julius 
              for(i=0;i<expected_address_num;i=i+1)
879 
                begin
880 860 olof 
                   if(duplicate_expected_addresses_waiting[i] &
881 449 julius 
                      expected_addresses_waiting[i] &
882 
                      expected_addresses[i] == pc)
883 
                     begin
884 
                        // Found a duplicate call address, clear it
885 
                        duplicate_expected_addresses_waiting[i] = 0;
886 
                        expected_addresses_waiting[i] = 0;
887 
 
888 
                        // Now reorder the list - pull all the ones above us
889 
                        // down by one
890 
                        for(j=i;j<expected_address_num;j=j+1)
891 
                          begin
892 
                             expected_addresses_waiting[j] = expected_addresses_waiting[j+1];
893 
                             expected_addresses[j] = expected_addresses[j+1];
894 
                             duplicate_expected_addresses_waiting[j] = duplicate_expected_addresses_waiting[j+1];
895 
                          end
896 
                        expected_address_num = expected_address_num - 1;
897 
                     end
898 
                end // for (i=0;i<expected_address_num;i=i+1)
899 
           end // if (hit & duplicates)
900 860 olof 
 
901 449 julius 
         if (expecting_hit & !hit)
902 
           begin
903 
              // Expected this address to be one we're supposed to jump to, but it wasn't!
904 
              $display("%t: Failed to find current PC, 0x%h, in expected PCs for branches/jumps",$time,pc);
905 860 olof 
              #100;
906 449 julius 
              $finish;
907 
           end
908 860 olof 
 
909 449 julius 
      end
910 
   endtask // check_expected_address
911 
 
912 
   // Task to assert value of GPR
913 
   task assert_gpr_val;
914 
      input [5:0] regnum;
915 860 olof 
      input [31:0] assert_value;
916 449 julius 
      input [31:0] pc;
917 
      reg [31:0]   reg_val;
918 860 olof 
 
919 449 julius 
      begin
920 
         get_gpr(regnum, reg_val);
921 
         if (reg_val !== assert_value)
922 
           begin
923 
              $display("%t: Assert r%0d value (0x%h) = 0x%h failed. pc=0x%h",
924 
                       $time, regnum, reg_val, assert_value,pc);
925 860 olof 
              #100;
926 449 julius 
              $finish;
927 
           end
928 
      end
929 
   endtask // assert_gpr_val
930 860 olof 
 
931 449 julius 
   // Task to assert something is true
932 
   task assert_this;
933 860 olof 
      input assert_result;
934 449 julius 
      input [31:0] pc;
935 
      begin
936 
         if (!assert_result)
937 
           begin
938 
              $display("%t: Assert failed for instruction at pc=0x%h",
939 
                       $time , pc);
940 860 olof 
              #100;
941 449 julius 
              $finish;
942 
           end
943 
      end
944 860 olof 
   endtask // assert_gpr_val
945 449 julius 
 
946 
   // The jumping variable doesn't get updated until we do the proper check of
947 
   // the current instruction reaching the writeback stage. We need to know
948 
   // earlier, eg. in the exception checking part, if this instruction will
949 
   // jump. We do that with this task.
950 
   task check_for_jump;
951 
      input [31:0] insn;
952 860 olof 
      reg [5:0]    opcode;
953 
      reg          flag;
954 449 julius 
      begin
955 
         opcode = insn[`OR1K_OPCODE_POS];
956 860 olof 
         // Use the flag from the previous instruction, as the decision
957 
         // is made in the execute stage not in te writeback stage,
958 449 julius 
         // which is where we're getting our instructions.
959 860 olof 
         flag = previous_sr[`OR1200_SR_F];
960 
 
961 
         case (opcode)
962 449 julius 
           `OR1200_OR32_J,
963 
             `OR1200_OR32_JR,
964 
             `OR1200_OR32_JAL,
965 
             `OR1200_OR32_JALR:
966 
               will_jump = 1;
967 
           `OR1200_OR32_BNF:
968 
             will_jump = !flag;
969 
           `OR1200_OR32_BF:
970 
             will_jump = flag;
971 
           default:
972 
             will_jump = 0;
973 
         endcase // case (opcode)
974 
      end
975 860 olof 
   endtask // check_for_jump
976 449 julius 
 
977 
 
978 860 olof 
 
979 449 julius 
   // Detect exceptions from the processor here
980 860 olof 
   reg [13:0] except_trig_r;
981 449 julius 
   reg        exception_coming;
982 860 olof 
 
983 449 julius 
   always @(posedge `CPU_CORE_CLK)
984 
     if (`OR1200_TOP.iwb_rst_i)
985 
       begin
986 
          except_trig_r = 0;
987 
          exception_coming = 0;
988 860 olof 
          except_during_rfe = 0;
989 449 julius 
       end
990 
     else if ((|`OR1200_TOP.`CPU_cpu.`CPU_except.except_trig) && !exception_coming)
991 
       begin
992 
          exception_coming  = 1;
993 
          except_trig_r = `OR1200_TOP.`CPU_cpu.`CPU_except.except_trig;
994 860 olof 
          except_during_rfe = rfe;
995 449 julius 
       end
996 
 
997 
   task check_incoming_exceptions;
998 
      begin
999 860 olof 
 
1000 449 julius 
         // Exception timing  - depends on the trigger.
1001 860 olof 
         // Appears to be:
1002 449 julius 
         // tick timer - dslot - 1 instruction delay, else 2
1003 
         // tlb lookasides - 1 instruction for both
1004 
 
1005 
         casex (except_trig_r)
1006 
           13'b1_xxxx_xxxx_xxxx: begin
1007 
              //except_type <= #1 `OR1200_EXCEPT_TICK;
1008 
              exception_here = exception_coming2;
1009 
              exception_coming2 = jump_dslot ? exception_coming: exception_coming1 ;
1010 
              exception_coming1 = jump_dslot ? 0 : exception_coming;
1011 
           end
1012 
           13'b0_1xxx_xxxx_xxxx: begin
1013 
              //except_type <= #1 `OR1200_EXCEPT_INT;
1014 860 olof 
              #1;
1015 449 julius 
           end
1016 
           13'b0_01xx_xxxx_xxxx: begin
1017 
              //except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
1018 
              exception_here = exception_coming2;
1019 
              exception_coming2 = jump_dslot ? exception_coming : exception_coming1 ;
1020 
              exception_coming1 = jump_dslot ? 0 : exception_coming;
1021 
           end
1022 
           13'b0_001x_xxxx_xxxx: begin
1023 
              //except_type <= #1 `OR1200_EXCEPT_IPF;
1024 
              exception_here = exception_coming2;
1025 
              exception_coming2 = jump_dslot ? exception_coming : exception_coming1 ;
1026 
              exception_coming1 = jump_dslot ? 0 : exception_coming;
1027 
           end
1028 
           13'b0_0001_xxxx_xxxx: begin
1029 
              //except_type <= #1 `OR1200_EXCEPT_BUSERR;
1030 860 olof 
              exception_here = exception_coming;
1031 
              exception_coming2 = 0;
1032 
              exception_coming1 = 0;
1033 449 julius 
           end
1034 
           13'b0_0000_1xxx_xxxx: begin
1035 
              //except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
1036 
              if (will_jump)
1037 
                begin
1038 
                   // Writeback stage instruction will jump, and we have an
1039 
                   // illegal instruction in the decode/execute stage, which is
1040 
                   // the delay slot, so indicate the exception is coming...
1041 860 olof 
                   exception_here = exception_coming2;
1042 
                   exception_coming2 = exception_coming;
1043 
                   exception_coming1 = 0;
1044 449 julius 
                end
1045 
              else
1046 
                begin
1047 860 olof 
                   exception_here = jump_dslot ?
1048 449 julius 
                                    exception_coming2 : exception_coming;
1049 
                   exception_coming2 = jump_dslot ? exception_coming : 0;
1050 860 olof 
                   exception_coming1 = 0;
1051 449 julius 
                end
1052 
           end
1053 
           13'b0_0000_01xx_xxxx: begin
1054 
              //except_type <= #1 `OR1200_EXCEPT_ALIGN;
1055 
              if(will_jump)
1056 
                begin
1057 860 olof 
                   exception_here = exception_coming2;
1058 
                   exception_coming2 = exception_coming;
1059 
                   exception_coming1 = 0;
1060 449 julius 
                end
1061 
              else
1062 
                begin
1063 
                   exception_here =  (rfe) ? exception_coming : exception_coming2;
1064 
                   exception_coming2 = (rfe) ? 0 : exception_coming;
1065 
                   exception_coming1 = 0;
1066 
                end
1067 
           end
1068 
           13'b0_0000_001x_xxxx: begin
1069 
              //except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
1070 
              // Looks like except_trig goes high here after we check the
1071 
              // instruction before the itlb miss after a delay slot, so we
1072 
              // miss the dslot variable (it gets propegated before we call
1073 
              // this task) so we use the jumped variable here to see if we
1074 860 olof 
              // are an exception after a delay slot
1075 449 julius 
              //exception_here = (jumped | rfe) ? exception_coming : exception_coming2 ;
1076 
              //exception_coming2 = (jumped | rfe) ? 0 : exception_coming;
1077 860 olof 
 
1078 449 julius 
              exception_here = (jumped | rfe) ? exception_coming : exception_coming2 ;
1079 
              exception_coming2 = (jumped | rfe) ? 0 : exception_coming;
1080 
 
1081 
              exception_coming1 = 0;
1082 
           end
1083 
           13'b0_0000_0001_xxxx: begin
1084 
              //except_type <= #1 `OR1200_EXCEPT_DPF;
1085 
              if (jumped) begin // Jumped onto illegal instruction
1086 
                 exception_here = exception_coming ;
1087 
                 exception_coming2 = 0;
1088 
                 exception_coming1 = 0;
1089 
              end
1090 
              else begin
1091 
                 exception_here =  exception_coming2;
1092 
                 exception_coming2 = exception_coming;
1093 
                 exception_coming1 = 0;
1094 
              end
1095 
           end
1096 
           13'b0_0000_0000_1xxx: begin  // Data Bus Error
1097 
              //except_type <= #1 `OR1200_EXCEPT_BUSERR;
1098 
              exception_here = exception_coming2 ;
1099 
              exception_coming2 = exception_coming;
1100 860 olof 
              exception_coming1 = 0;
1101 449 julius 
           end
1102 
           13'b0_0000_0000_01xx: begin
1103 
              //except_type <= #1 `OR1200_EXCEPT_RANGE;
1104 860 olof 
              #1;
1105 449 julius 
           end
1106 
           13'b0_0000_0000_001x: begin
1107 860 olof 
              // trap
1108 
              #1;
1109 449 julius 
           end
1110 
           13'b0_0000_0000_0001: begin
1111 
              //except_type <= #1 `OR1200_EXCEPT_SYSCALL;
1112 860 olof 
              exception_here = exception_coming2;
1113 449 julius 
              exception_coming2 = jumped ? exception_coming: exception_coming1 ;
1114 
              exception_coming1 = jumped ? 0 : exception_coming;
1115 
           end
1116 
         endcase // casex (except_trig_r)
1117 
 
1118 
         exception_coming = 0;
1119 
         except_during_rfe = 0;
1120 860 olof 
 
1121 449 julius 
      end
1122 
   endtask // check_incoming_exceptions
1123 
 
1124 860 olof 
 
1125 
 
1126 
 
1127 351 julius 
   /////////////////////////////////////////////////////////////////////////
1128 449 julius 
   // Execution tracking task
1129 351 julius 
   /////////////////////////////////////////////////////////////////////////
1130 348 julius 
 
1131 860 olof 
 
1132 449 julius 
`ifdef OR1200_SYSTEM_CHECKER
1133 
   always @(posedge `CPU_CORE_CLK)
1134 
     begin
1135 
        if (`OR1200_TOP.iwb_rst_i)
1136 
          begin
1137 
             exception_coming1 = 0;exception_coming2 = 0;exception_here= 0;
1138 
             jumping = 0; jump_dslot = 0; jumped = 0;
1139 
             rfe = 0;
1140 
          end
1141 
        if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze) begin
1142 
           //#2 ;
1143 860 olof 
           // If instruction isn't a l.nop with bit 16 set (implementation's
1144 
           // filler instruction in pipeline), and do not have an exception
1145 449 julius 
           // signaled with a dslot instruction in the execute stage
1146 860 olof 
           if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[`OR1K_OPCODE_POS] !=
1147 449 julius 
                 `OR1200_OR32_NOP) || !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
1148 860 olof 
               && !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &&
1149 449 julius 
                    `OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot)) // and not except start
1150 
             begin
1151 351 julius 
 
1152 449 julius 
                // Propegate jump-tracking variables
1153 
                // If was exception in delay slot, we didn't actually jump
1154 
                // so don't set jumped in this case.
1155 
                jumped = exception_here ? 0 : jump_dslot;
1156 
                jump_dslot = jumping;
1157 
                jumping = 0;
1158 
                rfe = 0;
1159 860 olof 
 
1160 449 julius 
                // Now, check if current instruction will jump/branch, this is
1161 
                // needed by the exception checking code, sets will_jump=1
1162 
                check_for_jump(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
1163 
 
1164 
                // Now check if it's an exception this instruction
1165 
                check_incoming_exceptions;
1166 
 
1167 860 olof 
                // Case where we just went to an exception after a jump, so we
1168 449 julius 
                // mark the address we were meant to jump to as a place which will
1169 
                // have duplicate return entries in the expected address list
1170 
                if (exception_here & (jumped | jump_dslot))
1171 
                  begin
1172 
                     $display("%t: marked as jump address with exception (dup)"
1173 
                              ,$time);
1174 
                     mark_duplicate_expected_address;
1175 
                  end
1176 860 olof 
 
1177 449 julius 
                or1200_check_execution(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn,
1178 860 olof 
                                       `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
1179 
                                       exception_here);
1180 449 julius 
                //$write("%t: pc:0x%h\t",$time,
1181 
                //       `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc);
1182 
                // Decode the instruction, print it out
1183 860 olof 
                //or1200_print_op(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
1184 449 julius 
                //$write("\t exc:%0h dsl:%0h\n",exception_here,jump_dslot);
1185 
 
1186 860 olof 
 
1187 
 
1188 449 julius 
             end
1189 
        end // if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze)
1190 
     end // always @ (posedge `CPU_CORE_CLK)
1191 860 olof 
`endif
1192 449 julius 
 
1193 860 olof 
 
1194 449 julius 
   task or1200_check_execution;
1195 
      input [31:0] insn;
1196 
      input [31:0] pc;
1197 
      input        exception;
1198 860 olof 
 
1199 449 julius 
      reg [5:0]    opcode;
1200 
 
1201 
      reg [25:0]   j_imm;
1202 
      reg [25:0]   br_imm;
1203 860 olof 
 
1204 449 julius 
      reg [4:0]    rD_num, rA_num, rB_num;
1205 
      reg [31:0]   rD_val, rA_val, rB_val;
1206 
      reg [15:0]   imm_16bit;
1207 860 olof 
 
1208 449 julius 
      reg [15:0]   mtspr_imm;
1209 860 olof 
 
1210 449 julius 
      reg [3:0]    alu_op;
1211 
      reg [1:0]    shrot_op;
1212 
 
1213 
      reg [5:0]    shroti_imm;
1214 860 olof 
 
1215 449 julius 
      reg [5:0]    sf_op;
1216 
 
1217 860 olof 
      reg [5:0]    xsync_op;
1218 
 
1219 449 julius 
      reg          flag;
1220 
 
1221 
      reg [31:0]   br_j_ea; // Branch/jump effective address
1222 860 olof 
 
1223 
 
1224 449 julius 
      begin
1225 860 olof 
 
1226 449 julius 
         // Instruction opcode
1227 
         opcode = insn[`OR1K_OPCODE_POS];
1228 
         // Immediates for jump or branch instructions
1229 
         j_imm = insn[`OR1K_J_BR_IMM_POS];
1230 
         br_imm = insn[`OR1K_J_BR_IMM_POS];
1231 
         // Register numbers (D, A and B)
1232 
         rD_num = insn[`OR1K_RD_POS];
1233 860 olof 
         rA_num = insn[`OR1K_RA_POS];
1234 449 julius 
         rB_num = insn[`OR1K_RB_POS];
1235 
         // Bottom 16 bits when used as immediates in various instructions
1236 
         imm_16bit = insn[15:0];
1237 
         // 16-bit immediate for mtspr instructions
1238 
         mtspr_imm = {insn[25:21],insn[10:0]};
1239 
         // ALU op for ALU instructions
1240 
         alu_op = insn[`OR1K_ALU_OP_POS];
1241 
         // Shift-rotate op for SHROT ALU instructions
1242 
         shrot_op = insn[`OR1K_SHROT_OP_POS];
1243 
         shroti_imm = insn[`OR1K_SHROTI_IMM_POS];
1244 
 
1245 
         // Set flag op
1246 
         sf_op = insn[`OR1K_SF_OP];
1247 860 olof 
 
1248 449 julius 
         // Xsync/syscall/trap opcode
1249 
         xsync_op = insn[`OR1K_XSYNC_OP_POS];
1250 
 
1251 860 olof 
         // Use the flag from the previous instruction, as the decision
1252 
         // is made in the execute stage not in te writeback stage,
1253 449 julius 
         // which is where we're getting our instructions.
1254 
         flag = previous_sr[`OR1200_SR_F];
1255 
 
1256 
         update_current_gprs;
1257 
 
1258 
         // Check MSbit of the immediate, sign extend if set
1259 860 olof 
         br_j_ea = j_imm[25] ? pc + {4'hf,j_imm,2'b00} :
1260 449 julius 
                   pc + {4'h0,j_imm,2'b00};
1261 
 
1262 
         if (exception)
1263 
           begin
1264 
              $display("%t: exception - at 0x%x",$time, pc);
1265 
              // get epcr, put it in the addresses we expect to jump
1266 
              // back to
1267 860 olof 
              // Maybe DON'T do this. Because maybe in linux things we
1268 449 julius 
              // interrupt out of, we don't want to execute them again?
1269 
              //add_expected_address(current_epcr);
1270 
           end
1271 
 
1272 860 olof 
 
1273 449 julius 
         check_expected_address(pc, (jumped & !exception));
1274 
 
1275 
         rfe = 0;
1276 860 olof 
 
1277 
         case (opcode)
1278 449 julius 
           `OR1200_OR32_J:
1279 
             begin
1280 
                //
1281 
                // PC < - exts(Immediate < < 2) + JumpInsnAddr
1282 
                //
1283 860 olof 
                //The immediate value is shifted left two bits, sign-extended
1284 
                // to program counter width, and then added to the address of
1285 
                // the jump instruction. The result is the effective address
1286 
                // of the jump. The program unconditionally jumps to EA with
1287 449 julius 
                // a delay of one instruction.
1288 860 olof 
 
1289 449 julius 
                add_expected_address(br_j_ea);
1290 
 
1291 
                jumping = 1;
1292 
             end
1293 
           `OR1200_OR32_JAL:
1294 
             begin
1295 
                //
1296 
                //PC < - exts(Immediate < < 2) + JumpInsnAddr
1297 
                //LR < - DelayInsnAddr + 4
1298 
                //
1299 
                // Link reg is r9, check it is PC+8
1300 
                //
1301 
                add_expected_address(br_j_ea);
1302 
                assert_gpr_val(9, pc+8, pc);
1303 860 olof 
                jumping = 1;    //
1304 449 julius 
             end
1305 
           `OR1200_OR32_BNF:
1306 
             begin
1307 
                //EA < - exts(Immediate < < 2) + BranchInsnAddr
1308 
                //PC < - EA if SR[F] cleared
1309 
                if (!flag)
1310 
                  begin
1311 
                     add_expected_address(br_j_ea);
1312 
                     jumping = 1;
1313 
                  end
1314 
             end
1315 
           `OR1200_OR32_BF:
1316 
             begin
1317 
                //EA < - exts(Immediate < < 2) + BranchInsnAddr
1318 
                //PC < - EA if SR[F] set
1319 
                if (flag)
1320 
                  begin
1321 
                     add_expected_address(br_j_ea);
1322 
                     jumping = 1;
1323 
                  end
1324 
             end
1325 
           `OR1200_OR32_RFE:
1326 
             begin
1327 
                add_expected_address(current_epcr);
1328 860 olof 
                // jumping variable keeps track of jumps/branches with delay
1329 449 julius 
                // slot - there is none for l.rfe
1330 860 olof 
                rfe = 1;
1331 449 julius 
             end
1332 
           `OR1200_OR32_JR:
1333 
             begin
1334 
                //PC < - rB
1335 
                get_gpr(rB_num, rB_val);
1336 
                add_expected_address(rB_val);
1337 
                jumping = 1;
1338 
             end
1339 
           `OR1200_OR32_JALR:
1340 
             begin
1341 
                //PC < - rB
1342 
                //LR < - DelayInsnAddr + 4
1343 
                get_gpr(rB_num, rB_val);
1344 
                add_expected_address(rB_val);
1345 
                assert_gpr_val(9, pc+8, pc);
1346 
                jumping = 1;
1347 
             end
1348 
           /*
1349 
            `OR1200_OR32_LWZ,
1350 
            `OR1200_OR32_LBZ,
1351 
            `OR1200_OR32_LBS,
1352 
            `OR1200_OR32_LHZ,
1353 
            `OR1200_OR32_LHS,
1354 
            `OR1200_OR32_SW,
1355 
            `OR1200_OR32_SB,
1356 
            `OR1200_OR32_SH:
1357 
            begin
1358 
            // Should result in databus access if data cache disabled
1359 
            $display("%t: lsu instruction",$time);
1360 
end
1361 
 
1362 
            `OR1200_OR32_MFSPR,
1363 
            `OR1200_OR32_MTSPR:
1364 
            begin
1365 
            // Confirm RF values end up in the correct SPR
1366 
            $display("%t: mxspr",$time);
1367 
end
1368 
 
1369 
            `OR1200_OR32_MOVHI,
1370 
            `OR1200_OR32_ADDI,
1371 
            `OR1200_OR32_ADDIC,
1372 
            `OR1200_OR32_ANDI,
1373 
            `OR1200_OR32_ORI,
1374 
            `OR1200_OR32_XORI,
1375 
            `OR1200_OR32_MULI,
1376 
            `OR1200_OR32_ALU:
1377 
            begin
1378 
            // Double check operations done on RF and immediate values
1379 
            $display("%t: ALU op",$time);
1380 
end
1381 860 olof 
 
1382 449 julius 
            `OR1200_OR32_SH_ROTI:
1383 
            begin
1384 
            // Rotate according to immediate - maybe should be in ALU ops
1385 
            $display("%t: rotate op",$time);
1386 
end
1387 860 olof 
 
1388 449 julius 
            `OR1200_OR32_SFXXI,
1389 
            `OR1200_OR32_SFXX:
1390 
            begin
1391 
            // Set flag - do the check oursevles, check flag
1392 
            $display("%t: set flag op",$time);
1393 
end
1394 860 olof 
 
1395 449 julius 
            `OR1200_OR32_MACI,
1396 
            `OR1200_OR32_MACMSB:
1397 
            begin
1398 
            // Either, multiply signed and accumulate, l.mac
1399 
            // or multiply signed and subtract, l.msb
1400 
            $display("%t: MAC op",$time);
1401 
end
1402 
            */
1403 860 olof 
 
1404 449 julius 
           /*default:
1405 
            begin
1406 
            $display("%t: Unknown opcode 0x%h at pc 0x%x\n",
1407 
            $time,opcode, pc);
1408 
end
1409 
            */
1410 
         endcase // case (opcode)
1411 
 
1412 860 olof 
         update_previous_gprs;
1413 
 
1414 449 julius 
      end
1415 
   endtask // or1200_check_execution
1416 860 olof 
 
1417 
 
1418 449 julius 
   /////////////////////////////////////////////////////////////////////////
1419 
   // Instruction decode task
1420 
   /////////////////////////////////////////////////////////////////////////
1421 351 julius 
 
1422 
   task or1200_print_op;
1423 
      input [31:0] insn;
1424 
 
1425 
      reg [5:0]    opcode;
1426 860 olof 
 
1427 351 julius 
      reg [25:0]   j_imm;
1428 
      reg [25:0]   br_imm;
1429 860 olof 
 
1430 351 julius 
      reg [4:0]    rD_num, rA_num, rB_num;
1431 
      reg [31:0]   rA_val, rB_val;
1432 
      reg [15:0]   imm_16bit;
1433 860 olof 
      reg [10:0]   imm_split16bit;
1434 
 
1435 351 julius 
      reg [3:0]    alu_op;
1436 
      reg [1:0]    shrot_op;
1437 
 
1438 
      reg [5:0]    shroti_imm;
1439 
 
1440 449 julius 
      reg [5:0]    sf_op;
1441 860 olof 
 
1442 
      reg [5:0]    xsync_op;
1443 
 
1444 351 julius 
      begin
1445 
         // Instruction opcode
1446 449 julius 
         opcode = insn[`OR1K_OPCODE_POS];
1447 351 julius 
         // Immediates for jump or branch instructions
1448 449 julius 
         j_imm = insn[`OR1K_J_BR_IMM_POS];
1449 
         br_imm = insn[`OR1K_J_BR_IMM_POS];
1450 351 julius 
         // Register numbers (D, A and B)
1451 449 julius 
         rD_num = insn[`OR1K_RD_POS];
1452 860 olof 
         rA_num = insn[`OR1K_RA_POS];
1453 449 julius 
         rB_num = insn[`OR1K_RB_POS];
1454 351 julius 
         // Bottom 16 bits when used as immediates in various instructions
1455 
         imm_16bit = insn[15:0];
1456 
         // Bottom 11 bits used as immediates for l.sX instructions
1457 
 
1458 
         // Split 16-bit immediate for l.mtspr/l.sX instructions
1459 
         imm_split16bit = {insn[25:21],insn[10:0]};
1460 
         // ALU op for ALU instructions
1461 449 julius 
         alu_op = insn[`OR1K_ALU_OP_POS];
1462 351 julius 
         // Shift-rotate op for SHROT ALU instructions
1463 449 julius 
         shrot_op = insn[`OR1K_SHROT_OP_POS];
1464 
         shroti_imm = insn[`OR1K_SHROTI_IMM_POS];
1465 351 julius 
 
1466 
         // Set flag op
1467 449 julius 
         sf_op = insn[`OR1K_SF_OP];
1468 860 olof 
 
1469 449 julius 
         // Xsync/syscall/trap opcode
1470 
         xsync_op = insn[`OR1K_XSYNC_OP_POS];
1471 860 olof 
 
1472 351 julius 
         case (opcode)
1473 
           `OR1200_OR32_J:
1474 860 olof 
             begin
1475 
                $fwrite(finsn,"l.j 0x%h", {j_imm,2'b00});
1476 351 julius 
             end
1477 860 olof 
 
1478 351 julius 
           `OR1200_OR32_JAL:
1479 
             begin
1480 449 julius 
                $fwrite(finsn,"l.jal 0x%h", {j_imm,2'b00});
1481 351 julius 
             end
1482 
 
1483 
           `OR1200_OR32_BNF:
1484 
             begin
1485 860 olof 
                $fwrite(finsn,"l.bnf 0x%h", {br_imm,2'b00});
1486 351 julius 
             end
1487 860 olof 
 
1488 351 julius 
           `OR1200_OR32_BF:
1489 
             begin
1490 449 julius 
                $fwrite(finsn,"l.bf 0x%h", {br_imm,2'b00});
1491 351 julius 
             end
1492 860 olof 
 
1493 351 julius 
           `OR1200_OR32_RFE:
1494 
             begin
1495 860 olof 
                $fwrite(finsn,"l.rfe");
1496 351 julius 
             end
1497 860 olof 
 
1498 351 julius 
           `OR1200_OR32_JR:
1499 
             begin
1500 449 julius 
                $fwrite(finsn,"l.jr r%0d",rB_num);
1501 351 julius 
             end
1502 860 olof 
 
1503 351 julius 
           `OR1200_OR32_JALR:
1504 
             begin
1505 449 julius 
                $fwrite(finsn,"l.jalr r%0d",rB_num);
1506 351 julius 
             end
1507 860 olof 
 
1508 351 julius 
           `OR1200_OR32_LWZ:
1509 
             begin
1510 449 julius 
                $fwrite(finsn,"l.lwz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1511 351 julius 
             end
1512 860 olof 
 
1513 351 julius 
           `OR1200_OR32_LBZ:
1514 
             begin
1515 449 julius 
                $fwrite(finsn,"l.lbz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1516 351 julius 
             end
1517 860 olof 
 
1518 351 julius 
           `OR1200_OR32_LBS:
1519 
             begin
1520 449 julius 
                $fwrite(finsn,"l.lbs r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1521 351 julius 
             end
1522 860 olof 
 
1523 351 julius 
           `OR1200_OR32_LHZ:
1524 
             begin
1525 449 julius 
                $fwrite(finsn,"l.lhz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1526 351 julius 
             end
1527 860 olof 
 
1528 351 julius 
           `OR1200_OR32_LHS:
1529 
             begin
1530 449 julius 
                $fwrite(finsn,"l.lhs r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1531 351 julius 
             end
1532 860 olof 
 
1533 351 julius 
           `OR1200_OR32_SW:
1534 
             begin
1535 449 julius 
                $fwrite(finsn,"l.sw 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
1536 351 julius 
             end
1537 860 olof 
 
1538 351 julius 
           `OR1200_OR32_SB:
1539 
             begin
1540 449 julius 
                $fwrite(finsn,"l.sb 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
1541 351 julius 
             end
1542 860 olof 
 
1543 351 julius 
           `OR1200_OR32_SH:
1544 
             begin
1545 860 olof 
                $fwrite(finsn,"l.sh 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
1546 351 julius 
             end
1547 860 olof 
 
1548 351 julius 
           `OR1200_OR32_MFSPR:
1549 
             begin
1550 860 olof 
                $fwrite(finsn,"l.mfspr r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit,);
1551 
             end
1552 351 julius 
 
1553 
           `OR1200_OR32_MTSPR:
1554 
             begin
1555 860 olof 
                $fwrite(finsn,"l.mtspr r%0d,r%0d,0x%h",rA_num,rB_num,imm_split16bit);
1556 351 julius 
             end
1557 860 olof 
 
1558 351 julius 
           `OR1200_OR32_MOVHI:
1559 
             begin
1560 
                if (!insn[16])
1561 449 julius 
                  $fwrite(finsn,"l.movhi r%0d,0x%h",rD_num,imm_16bit);
1562 351 julius 
                else
1563 449 julius 
                  $fwrite(finsn,"l.macrc r%0d",rD_num);
1564 351 julius 
             end
1565 860 olof 
 
1566 351 julius 
           `OR1200_OR32_ADDI:
1567 
             begin
1568 449 julius 
                $fwrite(finsn,"l.addi r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1569 351 julius 
             end
1570 860 olof 
 
1571 351 julius 
           `OR1200_OR32_ADDIC:
1572 
             begin
1573 449 julius 
                $fwrite(finsn,"l.addic r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1574 351 julius 
             end
1575 860 olof 
 
1576 351 julius 
           `OR1200_OR32_ANDI:
1577 
             begin
1578 449 julius 
                $fwrite(finsn,"l.andi r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1579 860 olof 
             end
1580 
 
1581 351 julius 
           `OR1200_OR32_ORI:
1582 
             begin
1583 449 julius 
                $fwrite(finsn,"l.ori r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1584 860 olof 
             end
1585 351 julius 
 
1586 
           `OR1200_OR32_XORI:
1587 
             begin
1588 449 julius 
                $fwrite(finsn,"l.xori r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1589 860 olof 
             end
1590 351 julius 
 
1591 
           `OR1200_OR32_MULI:
1592 
             begin
1593 449 julius 
                $fwrite(finsn,"l.muli r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1594 351 julius 
             end
1595 860 olof 
 
1596 351 julius 
           `OR1200_OR32_ALU:
1597 
             begin
1598 
                case(alu_op)
1599 
                  `OR1200_ALUOP_ADD:
1600 860 olof 
                    $fwrite(finsn,"l.add ");
1601 351 julius 
                  `OR1200_ALUOP_ADDC:
1602 860 olof 
                    $fwrite(finsn,"l.addc ");
1603 351 julius 
                  `OR1200_ALUOP_SUB:
1604 860 olof 
                    $fwrite(finsn,"l.sub ");
1605 351 julius 
                  `OR1200_ALUOP_AND:
1606 860 olof 
                    $fwrite(finsn,"l.and ");
1607 351 julius 
                  `OR1200_ALUOP_OR:
1608 860 olof 
                    $fwrite(finsn,"l.or ");
1609 351 julius 
                  `OR1200_ALUOP_XOR:
1610 860 olof 
                    $fwrite(finsn,"l.xor ");
1611 351 julius 
                  `OR1200_ALUOP_MUL:
1612 860 olof 
                    $fwrite(finsn,"l.mul ");
1613 351 julius 
                  `OR1200_ALUOP_SHROT:
1614 
                    begin
1615 
                       case(shrot_op)
1616 
                         `OR1200_SHROTOP_SLL:
1617 449 julius 
                           $fwrite(finsn,"l.sll ");
1618 351 julius 
                         `OR1200_SHROTOP_SRL:
1619 449 julius 
                           $fwrite(finsn,"l.srl ");
1620 351 julius 
                         `OR1200_SHROTOP_SRA:
1621 449 julius 
                           $fwrite(finsn,"l.sra ");
1622 351 julius 
                         `OR1200_SHROTOP_ROR:
1623 449 julius 
                           $fwrite(finsn,"l.ror ");
1624 351 julius 
                       endcase // case (shrot_op)
1625 
                    end
1626 
                  `OR1200_ALUOP_DIV:
1627 860 olof 
                    $fwrite(finsn,"l.div ");
1628 351 julius 
                  `OR1200_ALUOP_DIVU:
1629 860 olof 
                    $fwrite(finsn,"l.divu ");
1630 351 julius 
                  `OR1200_ALUOP_CMOV:
1631 860 olof 
                    $fwrite(finsn,"l.cmov ");
1632 351 julius 
                endcase // case (alu_op)
1633 449 julius 
                $fwrite(finsn,"r%0d,r%0d,r%0d",rD_num,rA_num,rB_num);
1634 351 julius 
             end
1635 860 olof 
 
1636 351 julius 
           `OR1200_OR32_SH_ROTI:
1637 
             begin
1638 
                case(shrot_op)
1639 
                  `OR1200_SHROTOP_SLL:
1640 449 julius 
                    $fwrite(finsn,"l.slli ");
1641 351 julius 
                  `OR1200_SHROTOP_SRL:
1642 449 julius 
                    $fwrite(finsn,"l.srli ");
1643 351 julius 
                  `OR1200_SHROTOP_SRA:
1644 449 julius 
                    $fwrite(finsn,"l.srai ");
1645 351 julius 
                  `OR1200_SHROTOP_ROR:
1646 449 julius 
                    $fwrite(finsn,"l.rori ");
1647 351 julius 
                endcase // case (shrot_op)
1648 860 olof 
                $fwrite(finsn,"r%0d,r%0d,0x%h",rD_num,rA_num,shroti_imm);
1649 351 julius 
             end
1650 860 olof 
 
1651 351 julius 
           `OR1200_OR32_SFXXI:
1652 
             begin
1653 
                case(sf_op[2:0])
1654 
                  `OR1200_COP_SFEQ:
1655 449 julius 
                    $fwrite(finsn,"l.sfeqi ");
1656 351 julius 
                  `OR1200_COP_SFNE:
1657 449 julius 
                    $fwrite(finsn,"l.sfnei ");
1658 351 julius 
                  `OR1200_COP_SFGT:
1659 
                    begin
1660 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1661 449 julius 
                         $fwrite(finsn,"l.sfgtsi ");
1662 351 julius 
                       else
1663 449 julius 
                         $fwrite(finsn,"l.sfgtui ");
1664 351 julius 
                    end
1665 
                  `OR1200_COP_SFGE:
1666 
                    begin
1667 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1668 449 julius 
                         $fwrite(finsn,"l.sfgesi ");
1669 351 julius 
                       else
1670 449 julius 
                         $fwrite(finsn,"l.sfgeui ");
1671 351 julius 
                    end
1672 
                  `OR1200_COP_SFLT:
1673 
                    begin
1674 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1675 449 julius 
                         $fwrite(finsn,"l.sfltsi ");
1676 351 julius 
                       else
1677 449 julius 
                         $fwrite(finsn,"l.sfltui ");
1678 351 julius 
                    end
1679 
                  `OR1200_COP_SFLE:
1680 
                    begin
1681 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1682 449 julius 
                         $fwrite(finsn,"l.sflesi ");
1683 351 julius 
                       else
1684 449 julius 
                         $fwrite(finsn,"l.sfleui ");
1685 860 olof 
                    end
1686 351 julius 
                endcase // case (sf_op[2:0])
1687 860 olof 
 
1688 449 julius 
                $fwrite(finsn,"r%0d,0x%h",rA_num, imm_16bit);
1689 860 olof 
 
1690 351 julius 
             end // case: `OR1200_OR32_SFXXI
1691 
 
1692 
           `OR1200_OR32_SFXX:
1693 
             begin
1694 
                case(sf_op[2:0])
1695 
                  `OR1200_COP_SFEQ:
1696 449 julius 
                    $fwrite(finsn,"l.sfeq ");
1697 351 julius 
                  `OR1200_COP_SFNE:
1698 449 julius 
                    $fwrite(finsn,"l.sfne ");
1699 351 julius 
                  `OR1200_COP_SFGT:
1700 
                    begin
1701 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1702 449 julius 
                         $fwrite(finsn,"l.sfgts ");
1703 351 julius 
                       else
1704 449 julius 
                         $fwrite(finsn,"l.sfgtu ");
1705 351 julius 
                    end
1706 
                  `OR1200_COP_SFGE:
1707 
                    begin
1708 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1709 449 julius 
                         $fwrite(finsn,"l.sfges ");
1710 351 julius 
                       else
1711 449 julius 
                         $fwrite(finsn,"l.sfgeu ");
1712 351 julius 
                    end
1713 
                  `OR1200_COP_SFLT:
1714 
                    begin
1715 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1716 449 julius 
                         $fwrite(finsn,"l.sflts ");
1717 351 julius 
                       else
1718 449 julius 
                         $fwrite(finsn,"l.sfltu ");
1719 351 julius 
                    end
1720 
                  `OR1200_COP_SFLE:
1721 
                    begin
1722 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1723 449 julius 
                         $fwrite(finsn,"l.sfles ");
1724 351 julius 
                       else
1725 449 julius 
                         $fwrite(finsn,"l.sfleu ");
1726 351 julius 
                    end
1727 860 olof 
 
1728 351 julius 
                endcase // case (sf_op[2:0])
1729 860 olof 
 
1730 449 julius 
                $fwrite(finsn,"r%0d,r%0d",rA_num, rB_num);
1731 860 olof 
 
1732 351 julius 
             end
1733 860 olof 
 
1734 351 julius 
           `OR1200_OR32_MACI:
1735 
             begin
1736 449 julius 
                $fwrite(finsn,"l.maci r%0d,0x%h",rA_num,imm_16bit);
1737 351 julius 
             end
1738 
 
1739 
           `OR1200_OR32_MACMSB:
1740 
             begin
1741 
                if(insn[3:0] == 4'h1)
1742 860 olof 
                  $fwrite(finsn,"l.mac ");
1743 351 julius 
                else if(insn[3:0] == 4'h2)
1744 449 julius 
                  $fwrite(finsn,"l.msb ");
1745 860 olof 
 
1746 449 julius 
                $fwrite(finsn,"r%0d,r%0d",rA_num,rB_num);
1747 351 julius 
             end
1748 
 
1749 
           `OR1200_OR32_NOP:
1750 
             begin
1751 449 julius 
                $fwrite(finsn,"l.nop 0x%0h",imm_16bit);
1752 351 julius 
             end
1753 860 olof 
 
1754 351 julius 
           `OR1200_OR32_XSYNC:
1755 
             begin
1756 
                case (xsync_op)
1757 
                  5'd0:
1758 449 julius 
                    $fwrite(finsn,"l.sys 0x%h",imm_16bit);
1759 351 julius 
                  5'd8:
1760 449 julius 
                    $fwrite(finsn,"l.trap 0x%h",imm_16bit);
1761 351 julius 
                  5'd16:
1762 449 julius 
                    $fwrite(finsn,"l.msync");
1763 351 julius 
                  5'd20:
1764 449 julius 
                    $fwrite(finsn,"l.psync");
1765 351 julius 
                  5'd24:
1766 449 julius 
                    $fwrite(finsn,"l.csync");
1767 351 julius 
                  default:
1768 
                    begin
1769 
                       $display("%t: Instruction with opcode 0x%h has bad specific type information: 0x%h",$time,opcode,insn);
1770 449 julius 
                       $fwrite(finsn,"%t: Instruction with opcode 0x%h has has bad specific type information: 0x%h",$time,opcode,insn);
1771 351 julius 
                    end
1772 
                endcase // case (xsync_op)
1773 
             end
1774 860 olof 
 
1775 351 julius 
           default:
1776 
             begin
1777 
                $display("%t: Unknown opcode 0x%h",$time,opcode);
1778 449 julius 
                $fwrite(finsn,"%t: Unknown opcode 0x%h",$time,opcode);
1779 351 julius 
             end
1780 860 olof 
 
1781 351 julius 
         endcase // case (opcode)
1782 860 olof 
 
1783 351 julius 
      end
1784 
   endtask // or1200_print_op
1785 
 
1786 
 
1787 860 olof 
 
1788 6 julius 
endmodule

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