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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [or1200_monitor.v] - Blame information for rev 477

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1 6 julius 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 449 julius 
////  or1200_monitor.v                                            ////
4 360 julius 
////                                                              ////
5 
////  OR1200 processor monitor module                             ////
6 
////                                                              ////
7 449 julius 
////  Author(s):                                                  ////
8 
////      - Damjan Lampret, lampret@opencores.org                 ////
9 
////      - Julius Baxter, julius@opencores.org                   ////
10 
////                                                              ////
11 360 julius 
//////////////////////////////////////////////////////////////////////
12 
////                                                              ////
13 348 julius 
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
14 6 julius 
////                                                              ////
15 
//// This source file may be used and distributed without         ////
16 
//// restriction provided that this copyright statement is not    ////
17 
//// removed from the file and that any derivative work contains  ////
18 
//// the original copyright notice and the associated disclaimer. ////
19 
////                                                              ////
20 
//// This source file is free software; you can redistribute it   ////
21 
//// and/or modify it under the terms of the GNU Lesser General   ////
22 
//// Public License as published by the Free Software Foundation; ////
23 
//// either version 2.1 of the License, or (at your option) any   ////
24 
//// later version.                                               ////
25 
////                                                              ////
26 
//// This source is distributed in the hope that it will be       ////
27 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
28 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
29 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
30 
//// details.                                                     ////
31 
////                                                              ////
32 
//// You should have received a copy of the GNU Lesser General    ////
33 
//// Public License along with this source; if not, download it   ////
34 
//// from http://www.opencores.org/lgpl.shtml                     ////
35 
////                                                              ////
36 
//////////////////////////////////////////////////////////////////////
37 67 julius 
 
38 55 julius 
`include "timescale.v"
39 6 julius 
`include "or1200_defines.v"
40 360 julius 
`include "orpsoc-testbench-defines.v"
41 
`include "test-defines.v"
42 415 julius 
 
43 6 julius 
//
44 415 julius 
// Top of TB
45 
//
46 
`define TB_TOP orpsoc_testbench
47 449 julius 
 
48 415 julius 
//
49 
// Top of DUT
50 
//
51 
`define DUT_TOP `TB_TOP.dut
52 449 julius 
 
53 415 julius 
//
54 6 julius 
// Top of OR1200 inside test bench
55 
//
56 415 julius 
`define OR1200_TOP `DUT_TOP.or1200_top0
57 360 julius 
 
58 397 julius 
//
59 
// Define to enable lookup file generation
60 
//
61 
//`define OR1200_MONITOR_LOOKUP
62 360 julius 
 
63 6 julius 
//
64 397 julius 
// Define to enable SPR access log file generation
65 6 julius 
//
66 397 julius 
//`define OR1200_MONITOR_SPRS
67 6 julius 
 
68 348 julius 
//
69 397 julius 
// Enable logging of state during execution
70 351 julius 
//
71 397 julius 
//`define OR1200_MONITOR_EXEC_STATE
72 
 
73 
//
74 
// Enable disassembly of instructions in execution state log
75 
//
76 449 julius 
//`define OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
77 351 julius 
 
78 449 julius 
//
79 456 julius 
// Enable verbose report l.nops (to both general log file and stdout)
80 
//
81 
`define OR1200_MONITOR_VERBOSE_NOPS
82 
 
83 
//
84 449 julius 
// Enable monitoring of control and execution flow (experimental)
85 
//
86 
//`define OR1200_SYSTEM_CHECKER
87 
 
88 397 julius 
// Can either individually enable things above, or usually have the scripts
89 
// running the simulation pass the PROCESSOR_MONITOR_ENABLE_LOGS define to
90 
// enable them all.
91 351 julius 
 
92 397 julius 
`ifdef PROCESSOR_MONITOR_ENABLE_LOGS
93 
 `define OR1200_MONITOR_EXEC_STATE
94 
 `define OR1200_MONITOR_SPRS
95 
 `define OR1200_MONITOR_LOOKUP
96 
`endif
97 
 
98 351 julius 
//
99 415 julius 
// Memory coherence checking (double check instruction in fetch stage against
100 477 julius 
// what is in memory.) Useful for cache controller development.
101 415 julius 
//
102 
//`define MEM_COHERENCE_CHECK
103 
 
104 
//
105 348 julius 
// Top of OR1200 inside test bench
106 
//
107 
`define CPU or1200
108 
`define CPU_cpu or1200_cpu
109 
`define CPU_rf or1200_rf
110 
`define CPU_except or1200_except
111 
`define CPU_ctrl or1200_ctrl
112 
`define CPU_sprs or1200_sprs
113 449 julius 
`define CPU_immu_top or1200_immu_top
114 
`define CPU_immu_tlb or1200_immu_tlb
115 
`define CPU_CORE_CLK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.clk
116 348 julius 
 
117 449 julius 
 
118 
`define OR1K_OPCODE_POS 31:26
119 
`define OR1K_J_BR_IMM_POS 25:0
120 
`define OR1K_RD_POS 25:21
121 
`define OR1K_RA_POS 20:16
122 
`define OR1K_RB_POS 15:11
123 
`define OR1K_ALU_OP_POS 3:0
124 
 
125 
`define OR1K_SHROT_OP_POS 7:6
126 
`define OR1K_SHROTI_IMM_POS 5:0
127 
`define OR1K_SF_OP 25:21
128 
 
129 
`define OR1K_XSYNC_OP_POS 25:21
130 
 
131 
 
132 6 julius 
module or1200_monitor;
133 
 
134 
   integer fexe;
135 449 julius 
   integer finsn;
136 
 
137 6 julius 
   reg [23:0] ref;
138 397 julius 
`ifdef OR1200_MONITOR_SPRS
139 6 julius 
   integer    fspr;
140 397 julius 
`endif
141 6 julius 
   integer    fgeneral;
142 397 julius 
`ifdef OR1200_MONITOR_LOOKUP
143 6 julius 
   integer    flookup;
144 397 julius 
`endif
145 6 julius 
   integer    r3;
146 
   integer    insns;
147 
 
148 348 julius 
 
149 6 julius 
   //
150 
   // Initialization
151 
   //
152 
   initial begin
153 
      ref = 0;
154 397 julius 
`ifdef OR1200_MONITOR_EXEC_STATE
155 360 julius 
      fexe = $fopen({"../out/",`TEST_NAME_STRING,"-executed.log"});
156 449 julius 
`endif
157 
`ifdef OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
158 
      finsn = fexe;
159 397 julius 
`endif
160 6 julius 
      $timeformat (-9, 2, " ns", 12);
161 397 julius 
`ifdef OR1200_MONITOR_SPRS
162 360 julius 
      fspr = $fopen({"../out/",`TEST_NAME_STRING,"-sprs.log"});
163 397 julius 
`endif
164 360 julius 
      fgeneral = $fopen({"../out/",`TEST_NAME_STRING,"-general.log"});
165 397 julius 
`ifdef OR1200_MONITOR_LOOKUP
166 360 julius 
      flookup = $fopen({"../out/",`TEST_NAME_STRING,"-lookup.log"});
167 397 julius 
`endif
168 6 julius 
      insns = 0;
169 
 
170 
   end
171 
 
172 
   //
173 
   // Get GPR
174 
   //
175 
   task get_gpr;
176 
      input     [4:0]    gpr_no;
177 
      output [31:0]      gpr;
178 
      integer           j;
179 
      begin
180 348 julius 
 
181 449 julius 
`ifdef OR1200_RFRAM_GENERIC
182 6 julius 
         for(j = 0; j < 32; j = j + 1) begin
183 348 julius 
            gpr[j] = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no*32+j];
184 6 julius 
         end
185 348 julius 
 
186 449 julius 
`else
187 348 julius 
         //gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.mem[gpr_no];
188 
         gpr = `OR1200_TOP.`CPU_cpu.`CPU_rf.rf_a.get_gpr(gpr_no);
189 
 
190 449 julius 
`endif
191 6 julius 
 
192 348 julius 
 
193 
      end
194 
   endtask
195 
 
196 6 julius 
   //
197 
   // Write state of the OR1200 registers into a file
198 
   //
199 
   // Limitation: only a small subset of register file RAMs
200 
   // are supported
201 
   //
202 
   task display_arch_state;
203 
      reg [5:0] i;
204 
      reg [31:0] r;
205 
      integer    j;
206 
      begin
207 397 julius 
`ifdef OR1200_MONITOR_EXEC_STATE
208 6 julius 
         ref = ref + 1;
209 397 julius 
 `ifdef OR1200_MONITOR_LOOKUP
210 6 julius 
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
211 397 julius 
 `endif
212 351 julius 
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h", insns,
213 
                 `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
214 
                 `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
215 449 julius 
 `ifdef OR1200_MONITOR_EXEC_LOG_DISASSEMBLY
216 351 julius 
         $fwrite(fexe,"\t");
217 
         // Decode the instruction, print it out
218 
         or1200_print_op(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
219 
 `endif
220 6 julius 
         for(i = 0; i < 32; i = i + 1) begin
221 
            if (i % 4 == 0)
222 
              $fdisplay(fexe);
223 
            get_gpr(i, r);
224 
            $fwrite(fexe, "GPR%d: %h  ", i, r);
225 
         end
226 
         $fdisplay(fexe);
227 348 julius 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
228 6 julius 
         $fwrite(fexe, "SR   : %h  ", r);
229 348 julius 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
230 6 julius 
         $fwrite(fexe, "EPCR0: %h  ", r);
231 348 julius 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
232 6 julius 
         $fwrite(fexe, "EEAR0: %h  ", r);
233 348 julius 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
234 6 julius 
         $fdisplay(fexe, "ESR0 : %h", r);
235 397 julius 
`endif //  `ifdef OR1200_MONITOR_EXEC_STATE
236 348 julius 
`ifdef OR1200_DISPLAY_EXECUTED
237 
         ref = ref + 1;
238 397 julius 
 `ifdef OR1200_MONITOR_LOOKUP
239 348 julius 
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
240 397 julius 
 `endif
241 348 julius 
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
242 6 julius 
`endif
243 348 julius 
         insns = insns + 1;
244 449 julius 
      end
245 6 julius 
   endtask // display_arch_state
246 
 
247 
   /* Keep a trace buffer of the last lot of instructions and addresses
248 
    * "executed",as read from the writeback stage, and cause a $finish if we hit
249 
    * an instruction that is invalid, such as all zeros.
250 
    * Currently, only breaks on an all zero instruction, but should probably be
251 
    * made to break for anything with an X in it too. And of course ideally this
252 
    * shouldn't be needed - but is handy if someone changes something and stops
253 
    * the test continuing forever.
254 
    */
255 49 julius 
   integer num_nul_inst;
256 
   initial num_nul_inst = 0;
257 449 julius 
 
258 6 julius 
   task monitor_for_crash;
259 348 julius 
`define OR1200_MONITOR_CRASH_TRACE_SIZE 32
260 
      //Trace buffer of 32 instructions
261 
      reg [31:0] insn_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
262 
      //Trace buffer of the addresses of those instructions
263 
      reg [31:0] addr_trace [0:`OR1200_MONITOR_CRASH_TRACE_SIZE-1];
264 449 julius 
      integer    i;
265 6 julius 
 
266 449 julius 
      begin
267 
         if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h00000000)
268 
           num_nul_inst = num_nul_inst + 1;
269 
         else
270 
           num_nul_inst = 0; // Reset it
271 49 julius 
 
272 449 julius 
         if (num_nul_inst == 1000) // Sat a loop a bit too long...
273 
           begin
274 
              $fdisplay(fgeneral, "ERROR - no instruction at PC %h",
275 
                        `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc);
276 
              $fdisplay(fgeneral, "Crash trace: Last %d instructions: ",
277 
                        `OR1200_MONITOR_CRASH_TRACE_SIZE);
278 6 julius 
 
279 449 julius 
              $fdisplay(fgeneral, "PC\t\tINSTR");
280 
              for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>=0;i=i-1) begin
281 
                 $fdisplay(fgeneral, "%h\t%h",addr_trace[i], insn_trace[i]);
282 
              end
283 
              #100 $finish;
284 
           end
285 
         else
286 
           begin
287 
              for(i=`OR1200_MONITOR_CRASH_TRACE_SIZE-1;i>0;i=i-1) begin
288 
                 insn_trace[i] = insn_trace[i-1];
289 
                 addr_trace[i] = addr_trace[i-1];
290 
              end
291 
              insn_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn;
292 
              addr_trace[0] = `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc;
293 
           end
294 
 
295 
      end
296 6 julius 
   endtask // monitor_for_crash
297 348 julius 
 
298 6 julius 
 
299 348 julius 
   //
300 
   // Write state of the OR1200 registers into a file; version for exception
301 
   //
302 
   task display_arch_state_except;
303 
      reg [5:0] i;
304 
      reg [31:0] r;
305 
      integer    j;
306 
      begin
307 397 julius 
`ifdef OR1200_MONITOR_EXEC_STATE
308 348 julius 
         ref = ref + 1;
309 397 julius 
 `ifdef OR1200_MONITOR_LOOKUP
310 348 julius 
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
311 397 julius 
 `endif
312 348 julius 
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h  (exception)", insns, `OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc, `OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
313 
         for(i = 0; i < 32; i = i + 1) begin
314 
            if (i % 4 == 0)
315 
              $fdisplay(fexe);
316 
            get_gpr(i, r);
317 
            $fwrite(fexe, "GPR%d: %h  ", i, r);
318 
         end
319 
         $fdisplay(fexe);
320 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.sr;
321 
         $fwrite(fexe, "SR   : %h  ", r);
322 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.epcr;
323 
         $fwrite(fexe, "EPCR0: %h  ", r);
324 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.eear;
325 
         $fwrite(fexe, "EEAR0: %h  ", r);
326 
         r = `OR1200_TOP.`CPU_cpu.`CPU_sprs.esr;
327 
         $fdisplay(fexe, "ESR0 : %h", r);
328 
         insns = insns + 1;
329 397 julius 
`endif //  `ifdef OR1200_MONITOR_EXEC_STATE
330 348 julius 
`ifdef OR1200_DISPLAY_EXECUTED
331 
         ref = ref + 1;
332 397 julius 
 `ifdef OR1200_MONITOR_LOOKUP
333 348 julius 
         $fdisplay(flookup, "Instruction %d: %t", insns, $time);
334 397 julius 
 `endif
335 348 julius 
         $fwrite(fexe, "\nEXECUTED(%d): %h:  %h  (exception)", insns,
336 
                 `OR1200_TOP.`CPU_cpu.`CPU_except.ex_pc,
337 
                 `OR1200_TOP.`CPU_cpu.`CPU_ctrl.ex_insn);
338 
         insns = insns + 1;
339 
`endif
340 
 
341 449 julius 
      end
342 348 julius 
   endtask
343 
 
344 6 julius 
   integer iwb_progress;
345 
   reg [31:0] iwb_progress_addr;
346 
   //
347 
   // WISHBONE bus checker
348 
   //
349 
   always @(posedge `OR1200_TOP.iwb_clk_i)
350 
     if (`OR1200_TOP.iwb_rst_i) begin
351 
        iwb_progress = 0;
352 
        iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
353 
     end
354 
     else begin
355 
        if (`OR1200_TOP.iwb_cyc_o && (iwb_progress != 2)) begin
356 
           iwb_progress = 1;
357 
        end
358 
        if (`OR1200_TOP.iwb_stb_o) begin
359 
           if (iwb_progress >= 1) begin
360 
              if (iwb_progress == 1)
361 
                iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
362 
              iwb_progress = 2;
363 
           end
364 
           else begin
365 
              $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o raised without `OR1200_TOP.iwb_cyc_o, at %t\n", $time);
366 
              #100 $finish;
367 
           end
368 
        end
369 
        if (`OR1200_TOP.iwb_ack_i & `OR1200_TOP.iwb_err_i) begin
370 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i and `OR1200_TOP.iwb_err_i raised at the same time, at %t\n", $time);
371 
        end
372 
        if ((iwb_progress == 2) && (iwb_progress_addr != `OR1200_TOP.iwb_adr_o)) begin
373 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_adr_o changed while waiting for `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
374 
           #100 $finish;
375 
        end
376 
        if (`OR1200_TOP.iwb_ack_i | `OR1200_TOP.iwb_err_i)
377 
          if (iwb_progress == 2) begin
378 
             iwb_progress = 0;
379 
             iwb_progress_addr = `OR1200_TOP.iwb_adr_o;
380 
          end
381 
          else begin
382 
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_ack_i/`OR1200_TOP.iwb_err_i raised without `OR1200_TOP.iwb_cyc_i/`OR1200_TOP.iwb_stb_i, at %t\n", $time);
383 
             #100 $finish;
384 
          end
385 
        if ((iwb_progress == 2) && !`OR1200_TOP.iwb_stb_o) begin
386 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.iwb_stb_o lowered without `OR1200_TOP.iwb_err_i/`OR1200_TOP.iwb_ack_i, at %t\n", $time);
387 348 julius 
           #100 $finish;
388 6 julius 
        end
389 
     end
390 
 
391 
   integer dwb_progress;
392 449 julius 
   reg [31:0] dwb_progress_addr;
393 
   //
394 
   // WISHBONE bus checker
395 
   //
396 
   always @(posedge `OR1200_TOP.dwb_clk_i)
397 
     if (`OR1200_TOP.dwb_rst_i)
398 
       dwb_progress = 0;
399 
     else begin
400 
        if (`OR1200_TOP.dwb_cyc_o && (dwb_progress != 2))
401 
          dwb_progress = 1;
402 
        if (`OR1200_TOP.dwb_stb_o)
403 
          if (dwb_progress >= 1) begin
404 
             if (dwb_progress == 1)
405 
               dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
406 
             dwb_progress = 2;
407 
          end
408 
          else begin
409 
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o raised without `OR1200_TOP.dwb_cyc_o, at %t\n", $time);
410 
             #100 $finish;
411 
          end
412 
        if (`OR1200_TOP.dwb_ack_i & `OR1200_TOP.dwb_err_i) begin
413 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i and `OR1200_TOP.dwb_err_i raised at the same time, at %t\n", $time);
414 
        end
415 
        if ((dwb_progress == 2) && (dwb_progress_addr != `OR1200_TOP.dwb_adr_o)) begin
416 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_adr_o changed while waiting for `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
417 
           #100 $finish;
418 
        end
419 
        if (`OR1200_TOP.dwb_ack_i | `OR1200_TOP.dwb_err_i)
420 
          if (dwb_progress == 2) begin
421 
             dwb_progress = 0;
422 
             dwb_progress_addr = `OR1200_TOP.dwb_adr_o;
423 
          end
424 
          else begin
425 
             $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_ack_i/`OR1200_TOP.dwb_err_i raised without `OR1200_TOP.dwb_cyc_i/`OR1200_TOP.dwb_stb_i, at %t\n", $time);
426 
             #100 $finish;
427 
          end
428 
        if ((dwb_progress == 2) && !`OR1200_TOP.dwb_stb_o) begin
429 
           $fdisplay(fgeneral, "WISHBONE protocol violation: `OR1200_TOP.dwb_stb_o lowered without `OR1200_TOP.dwb_err_i/`OR1200_TOP.dwb_ack_i, at %t\n", $time);
430 
           #100 $finish;
431 
        end
432 6 julius 
     end
433 
 
434 449 julius 
   //
435 
   // Hooks for:
436 
   // - displaying registers
437 
   // - end of simulation
438 
   // - access to SPRs
439 
   //
440 
   always @(posedge `CPU_CORE_CLK)
441 348 julius 
     if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze) begin
442 449 julius 
        //      #2;
443 348 julius 
        if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[31:26] != `OR1200_OR32_NOP)
444 
             | !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
445 
            & !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &
446 
                `OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot))
447 6 julius 
          begin
448 
             display_arch_state;
449 
             monitor_for_crash;
450 
          end
451 
        else
452 348 julius 
          if (`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe)
453 6 julius 
            display_arch_state_except;
454 348 julius 
        // small hack to stop simulation (l.nop 1):
455 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0001) begin
456 6 julius 
           get_gpr(3, r3);
457 
           $fdisplay(fgeneral, "%t: l.nop exit (%h)", $time, r3);
458 456 julius 
`ifdef OR1200_MONITOR_VERBOSE_NOPS
459 468 julius 
           $display("exit(%h)",r3);
460 456 julius 
`endif
461 6 julius 
           $finish;
462 
        end
463 348 julius 
        // debug if test (l.nop 10)
464 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_000a) begin
465 6 julius 
           $fdisplay(fgeneral, "%t: l.nop dbg_if_test", $time);
466 
        end
467 348 julius 
        // simulation reports (l.nop 2)
468 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0002) begin
469 6 julius 
           get_gpr(3, r3);
470 468 julius 
           $fdisplay(fgeneral, "%t: l.nop report (0x%h)", $time, r3);
471 456 julius 
`ifdef OR1200_MONITOR_VERBOSE_NOPS
472 468 julius 
           $display("report (0x%h);", r3);
473 456 julius 
`endif
474 348 julius 
        end
475 
        // simulation printfs (l.nop 3)
476 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0003) begin
477 
           get_gpr(3, r3);
478 6 julius 
           $fdisplay(fgeneral, "%t: l.nop printf (%h)", $time, r3);
479 
        end
480 348 julius 
        if (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn == 32'h1500_0004) begin
481 
           // simulation putc (l.nop 4)
482 
           get_gpr(3, r3);
483 
           $write("%c", r3);
484 
           $fdisplay(fgeneral, "%t: l.nop putc (%c)", $time, r3);
485 
        end
486 397 julius 
`ifdef OR1200_MONITOR_SPRS
487 
        if (`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
488 6 julius 
          $fdisplay(fspr, "%t: Write to SPR : [%h] <- %h", $time,
489 397 julius 
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
490 348 julius 
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_dat_o);
491 397 julius 
        if ((|`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_cs) &
492 
            !`OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_we)
493 6 julius 
          $fdisplay(fspr, "%t: Read from SPR: [%h] -> %h", $time,
494 348 julius 
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.spr_addr,
495 
                    `OR1200_TOP.`CPU_cpu.`CPU_sprs.to_wbmux);
496 397 julius 
`endif
497 6 julius 
     end
498 
 
499 348 julius 
 
500 415 julius 
`ifdef RAM_WB
501 439 julius 
 `define RAM_WB_TOP `DUT_TOP.ram_wb0.ram_wb_b3_0
502 415 julius 
   task get_insn_from_wb_ram;
503 
      input [31:0] addr;
504 
      output [31:0] insn;
505 
      begin
506 477 julius 
         insn = `RAM_WB_TOP.get_mem32(addr[31:2]);
507 415 julius 
      end
508 
   endtask // get_insn_from_wb_ram
509 
`endif
510 
 
511 348 julius 
`ifdef VERSATILE_SDRAM
512 415 julius 
 `define SDRAM_TOP `TB_TOP.sdram0
513 348 julius 
   // Bit selects to define the bank
514 
   // 32 MB part with 4 banks
515 
 `define SDRAM_BANK_SEL_BITS 24:23
516 
 `define SDRAM_WORD_SEL_TOP_BIT 22
517 
   // Gets instruction word from correct bank
518 
   task get_insn_from_sdram;
519 
      input [31:0] addr;
520 
      output [31:0] insn;
521 
      reg [`SDRAM_WORD_SEL_TOP_BIT-1:0] word_addr;
522 449 julius 
 
523 348 julius 
      begin
524 
         word_addr = addr[`SDRAM_WORD_SEL_TOP_BIT:2];
525 
         if (addr[`SDRAM_BANK_SEL_BITS] == 2'b00)
526 
           begin
527 
 
528 
              //$display("%t: get_insn_from_sdram bank0, word 0x%h, (%h and %h in SDRAM)", $time, word_addr, `SDRAM_TOP.Bank0[{word_addr,1'b0}], `SDRAM_TOP.Bank0[{word_addr,1'b1}]);
529 
              insn[15:0] = `SDRAM_TOP.Bank0[{word_addr,1'b1}];
530 
              insn[31:16] = `SDRAM_TOP.Bank0[{word_addr,1'b0}];
531 
           end
532 
      end
533 
 
534 
   endtask // get_insn_from_sdram
535 
`endif //  `ifdef VERSATILE_SDRAM
536 
 
537 
`ifdef XILINX_DDR2
538 415 julius 
 `define DDR2_TOP `TB_TOP.gen_cs[0]
539 348 julius 
   // Gets instruction word from correct bank
540 
   task get_insn_from_xilinx_ddr2;
541 
      input [31:0] addr;
542 
      output [31:0] insn;
543 415 julius 
      reg [16*8-1:0] ddr2_array_line0,ddr2_array_line1,ddr2_array_line2,
544 
                     ddr2_array_line3;
545 348 julius 
      integer        word_in_line_num;
546 
      begin
547 449 julius 
         // Get our 4 128-bit chunks (8 half-words in each!! Confused yet?),
548 
         // 16 words total
549 348 julius 
         `DDR2_TOP.gen[0].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line0);
550 
         `DDR2_TOP.gen[1].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line1);
551 
         `DDR2_TOP.gen[2].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line2);
552 
         `DDR2_TOP.gen[3].u_mem0.memory_read(addr[28:27],addr[26:13],{addr[12:6],3'd0},ddr2_array_line3);
553 
         case (addr[5:2])
554 
           4'h0:
555 
             begin
556 
                insn[15:0] = ddr2_array_line0[15:0];
557 
                insn[31:16] = ddr2_array_line1[15:0];
558 
             end
559 
           4'h1:
560 
             begin
561 
                insn[15:0] = ddr2_array_line2[15:0];
562 
                insn[31:16] = ddr2_array_line3[15:0];
563 
             end
564 
           4'h2:
565 
             begin
566 
                insn[15:0] = ddr2_array_line0[31:16];
567 
                insn[31:16] = ddr2_array_line1[31:16];
568 
             end
569 
           4'h3:
570 
             begin
571 
                insn[15:0] = ddr2_array_line2[31:16];
572 
                insn[31:16] = ddr2_array_line3[31:16];
573 
             end
574 
           4'h4:
575 
             begin
576 
                insn[15:0] = ddr2_array_line0[47:32];
577 
                insn[31:16] = ddr2_array_line1[47:32];
578 
             end
579 
           4'h5:
580 
             begin
581 
                insn[15:0] = ddr2_array_line2[47:32];
582 
                insn[31:16] = ddr2_array_line3[47:32];
583 
             end
584 
           4'h6:
585 
             begin
586 
                insn[15:0] = ddr2_array_line0[63:48];
587 
                insn[31:16] = ddr2_array_line1[63:48];
588 
             end
589 
           4'h7:
590 
             begin
591 
                insn[15:0] = ddr2_array_line2[63:48];
592 
                insn[31:16] = ddr2_array_line3[63:48];
593 
             end
594 
           4'h8:
595 
             begin
596 
                insn[15:0] = ddr2_array_line0[79:64];
597 
                insn[31:16] = ddr2_array_line1[79:64];
598 
             end
599 
           4'h9:
600 
             begin
601 
                insn[15:0] = ddr2_array_line2[79:64];
602 
                insn[31:16] = ddr2_array_line3[79:64];
603 
             end
604 
           4'ha:
605 
             begin
606 
                insn[15:0] = ddr2_array_line0[95:80];
607 
                insn[31:16] = ddr2_array_line1[95:80];
608 
             end
609 
           4'hb:
610 
             begin
611 
                insn[15:0] = ddr2_array_line2[95:80];
612 
                insn[31:16] = ddr2_array_line3[95:80];
613 
             end
614 
           4'hc:
615 
             begin
616 
                insn[15:0] = ddr2_array_line0[111:96];
617 
                insn[31:16] = ddr2_array_line1[111:96];
618 
             end
619 
           4'hd:
620 
             begin
621 
                insn[15:0] = ddr2_array_line2[111:96];
622 
                insn[31:16] = ddr2_array_line3[111:96];
623 
             end
624 
           4'he:
625 
             begin
626 
                insn[15:0] = ddr2_array_line0[127:112];
627 
                insn[31:16] = ddr2_array_line1[127:112];
628 
             end
629 
           4'hf:
630 
             begin
631 
                insn[15:0] = ddr2_array_line2[127:112];
632 
                insn[31:16] = ddr2_array_line3[127:112];
633 
             end
634 
         endcase // case (addr[5:2])
635 
      end
636 
   endtask // get_insn_from_xilinx_ddr2
637 
`endif
638 
 
639 
 
640 
   task get_insn_from_memory;
641 
      input [31:0] id_pc;
642 
      output [31:0] insn;
643 
      begin
644 
         // do a decode of which server we should look in
645 
         case (id_pc[31:28])
646 
`ifdef VERSATILE_SDRAM
647 
           4'h0:
648 
             get_insn_from_sdram(id_pc, insn);
649 
`endif
650 
`ifdef XILINX_DDR2
651 
           4'h0:
652 
             get_insn_from_xilinx_ddr2(id_pc, insn);
653 415 julius 
`endif
654 
`ifdef RAM_WB
655 
           4'h0:
656 
             get_insn_from_wb_ram(id_pc, insn);
657 
`endif
658 348 julius 
           4'hf:
659 
             // Flash isn't stored in a memory, it's an FSM so just skip/ignore
660 
             insn = `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn;
661 
           default:
662 
             begin
663 
                $fdisplay(fgeneral, "%t: Unknown memory server for address 0x%h", $time,id_pc);
664 
                insn = 32'hxxxxxxxx; // Unknown server
665 
             end
666 
         endcase // case (id_pc[31:28])
667 
      end
668 
   endtask // get_insn_from_memory
669 
 
670 
 
671 449 julius 
   //
672 
   // Look in the iMMU TLB MR for this address' page, if MMUs are on and enabled
673 
   //
674 
   task check_for_immu_entry;
675 
      input [31:0] pc;
676 
      output [31:0] physical_pc;
677 
      output        mmu_tlb_miss;
678 
      integer       w,x;
679 
 
680 
      reg [31:`OR1200_IMMU_PS] pc_vpn;
681 
 
682 
      reg [`OR1200_ITLBTRW-1:0] itlb_tr;
683 
      reg [`OR1200_ITLBMRW-1:0] itlb_mr;
684 
 
685 
      integer                   tlb_index;
686 
      reg                       mmu_en;
687 
 
688 
 
689 
      begin
690 
         mmu_tlb_miss = 0;
691 
 
692 
`ifdef OR1200_NO_IMMU
693 
         physical_pc = pc;
694 
`else
695 
         mmu_en = `OR1200_TOP.`CPU_immu_top.immu_en;
696 
         // If MMU is enabled
697 
         if (mmu_en)
698 
           begin
699 
 
700 
              // Look in the iTLB for mapping - get virtual page number
701 
              pc_vpn = pc[31:`OR1200_IMMU_PS];
702 
 
703 
              tlb_index = pc[`OR1200_ITLB_INDX];
704 
 
705 
              // Look at the ITLB match register
706 
              itlb_mr = `OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_mr_ram.mem[tlb_index];
707 
 
708 
              // Get the translate register here too, in case there's an error, we print it
709 
              itlb_tr = `OR1200_TOP.`CPU_immu_top.`CPU_immu_tlb.itlb_tr_ram.mem[tlb_index];
710 
 
711 
              if ((itlb_mr[`OR1200_ITLBMR_V_BITS] === 1'b1) & (itlb_mr[`OR1200_ITLBMRW-1:1] === pc[`OR1200_ITLB_TAG]))
712 
                begin
713 
                   // Page number in match register matches page number of virtual PC, so get the physical
714 
                   // address from the translate memory
715 
                   // Now pull the physical page number out of the tranlsate register (it's after bottom 3 bits)
716 
                   physical_pc = {itlb_tr[`OR1200_ITLBTRW-1:`OR1200_ITLBTRW-(32-`OR1200_IMMU_PS)],pc[`OR1200_IMMU_PS-1:0]};
717 
                   //$display("check_for_immu_entry: found match for virtual PC 0x%h in entry %d of iMMU, mr = 0x%x tr = 0x%x, phys. PC = 0x%h", pc, pc[`OR1200_ITLB_INDX], itlb_mr, itlb_tr, physical_pc);
718 
                end // if ((itlb_mr[`OR1200_ITLBMR_V_BITS]) & (itlb_mr[`OR1200_ITLBMRW-1:1] == pc[`OR1200_ITLB_TAG]))
719 
              else
720 
                begin
721 
 
722 
                   // Wait a couple of clocks, see if we're doing a miss
723 
                   @(posedge `CPU_CORE_CLK);
724 
                   @(posedge `CPU_CORE_CLK);
725 
                   if (!(`OR1200_TOP.`CPU_immu_top.miss)) // MMU should indicate miss
726 
                     begin
727 
                        $display("%t: check_for_immu_entry - ERROR - no match found for virtual PC 0x%h in entry %d of iMMU, mr = 0x%x tr = 0x%x, and no miss generated",
728 
                                 $time, pc, pc[`OR1200_ITLB_INDX], itlb_mr, itlb_tr);
729 
                        #100;
730 
                        $finish;
731 
                     end
732 
                   else
733 
                     begin
734 
                        mmu_tlb_miss = 1; // Started a miss, so ignore this instruction
735 
                     end
736 
                end // else: !if((itlb_mr[`OR1200_ITLBMR_V_BITS]) & (itlb_mr[`OR1200_ITLBMRW-1:1] == pc[`OR1200_ITLB_TAG]))
737 
 
738 
           end // if (`OR1200_TOP.`CPU_immu_top.immu_en === 1'b1)
739 
         else
740 
           physical_pc = pc;
741 
`endif // !`ifdef OR1200_NO_IMMU
742 
      end
743 
   endtask // check_for_immu_entry
744 
 
745 
 
746 
   /*
747 
    Instruction memory coherence checking.
748 
 
749 
    For new instruction executed in the pipeline - ensure it matches
750 
    what is in the main program memory. Perform MMU translations if
751 
    it is enabled.
752 
    */
753 
 
754 
   reg [31:0] mem_word;
755 348 julius 
   reg [31:0] last_addr = 0;
756 
   reg [31:0] last_mem_word;
757 449 julius 
   reg [31:0] physical_pc;
758 
   reg        tlb_miss;
759 
 
760 348 julius 
 
761 415 julius 
`ifdef MEM_COHERENCE_CHECK
762 
 `define MEM_COHERENCE_TRIGGER (`OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_void === 1'b0)
763 
 
764 449 julius 
 `define INSN_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_ctrl.id_insn
765 
 `define PC_TO_CHECK `OR1200_TOP.`CPU_cpu.`CPU_except.id_pc
766 348 julius 
 
767 
   // Check instruction in decode stage is what is in the RAM
768 449 julius 
   always @(posedge `CPU_CORE_CLK)
769 348 julius 
     begin
770 415 julius 
        if (`MEM_COHERENCE_TRIGGER)
771 348 julius 
          begin
772 449 julius 
 
773 
             check_for_immu_entry(`PC_TO_CHECK, physical_pc, tlb_miss);
774 
 
775 348 julius 
             // Check if it's a new PC - will also get triggered if the
776 
             // instruction has changed since we last checked it
777 477 julius 
             if (((physical_pc !== last_addr) ||
778 
                  (last_mem_word != `INSN_TO_CHECK)) & !tlb_miss)
779 348 julius 
               begin
780 
                  // Decode stage not void, check instruction
781 
                  // get PC
782 449 julius 
                  get_insn_from_memory(physical_pc, mem_word);
783 348 julius 
 
784 
                  if (mem_word !== `INSN_TO_CHECK)
785 
                    begin
786 477 julius 
                       $fdisplay(fgeneral, "%t: Instruction mismatch for PC 0x%h (phys. 0x%h) - memory had 0x%h, CPU had 0x%h",
787 
                                 $time, `PC_TO_CHECK, physical_pc, mem_word,
788 
                                 `INSN_TO_CHECK);
789 
                       $display("%t: Instruction mismatch for PC 0x%h (phys. 0x%h) - memory had 0x%h, CPU had 0x%h",
790 
                                $time, `PC_TO_CHECK, physical_pc, mem_word,
791 
                                `INSN_TO_CHECK);
792 
                       #200;
793 
                       $finish;
794 348 julius 
                    end
795 449 julius 
                  last_addr = physical_pc;
796 
                  last_mem_word = mem_word;
797 
 
798 
               end // if (((physical_pc !== last_addr) || (last_mem_word != `INSN_TO_CHECK))...
799 
          end // if (`MEM_COHERENCE_TRIGGER)
800 
     end // always @ (posedge `CPU_CORE_CLK)
801 
 
802 
`endif //  `ifdef MEM_COHERENCE_CHECK
803 
 
804 
   // Trigger on each instruction that gets into writeback stage properly
805 
   reg exception_coming1, exception_coming2, exception_here;
806 
   reg will_jump, jumping, jump_dslot, jumped;
807 
   reg rfe, except_during_rfe;
808 
   reg dslot_expt;
809 
 
810 
 
811 
   // Maintain a copy of GPRS for previous instruction
812 
   reg [31:0] current_gprs [0:31];
813 
   reg [31:0] current_epcr, current_eear, current_esr, current_sr;
814 
   reg [31:0] previous_gprs [0:31];
815 
   reg [31:0] previous_epcr;
816 
   reg [31:0] previous_eear;
817 
   reg [31:0] previous_esr;
818 
   reg [31:0] previous_sr;
819 
 
820 
   task update_current_gprs;
821 
      integer j;
822 
      begin
823 
         for(j=0;j<32;j=j+1)
824 
           begin
825 
              get_gpr(j,current_gprs[j]);
826 
           end
827 
         current_sr = `OR1200_TOP.`CPU_cpu.or1200_sprs.sr ;
828 
         current_esr = `OR1200_TOP.`CPU_cpu.or1200_sprs.epcr ;
829 
         current_epcr = `OR1200_TOP.`CPU_cpu.or1200_sprs.epcr ;
830 
         current_eear = `OR1200_TOP.`CPU_cpu.or1200_sprs.eear ;
831 
      end
832 
   endtask
833 
 
834 
   task update_previous_gprs;
835 
      integer j;
836 
      begin
837 
         for(j=0;j<32;j=j+1)
838 
           begin
839 
              previous_gprs[j] = current_gprs[j];
840 
           end
841 
         previous_sr = current_sr;
842 
         previous_esr = current_esr;
843 
         previous_epcr = current_epcr;
844 
         previous_eear = current_eear;
845 
      end
846 
   endtask // update_previous_gprs
847 
 
848 
   // Maintain a list of addresses we expect the processor to execute
849 
   // Whenever we hit a branch or jump or rfe we add to this list - when we
850 
   // execute it then we remove it from the list.
851 
   reg [31:0] expected_addresses [0:31];
852 
   reg        expected_addresses_waiting [0:31]; // List indicating if address is waiting
853 
   reg        duplicate_expected_addresses_waiting [0:31]; // List indicating if a waiting address will be cleared by the single return
854 
   integer    expected_address_num;
855 
   // Initialise things on reset
856 
   always @(`OR1200_TOP.iwb_rst_i)
857 
     begin
858 
        for (expected_address_num=0;expected_address_num<32;expected_address_num=expected_address_num+1)
859 
          begin
860 
             expected_addresses_waiting[expected_address_num] = 0;
861 
             duplicate_expected_addresses_waiting[expected_address_num] = 0;
862 348 julius 
          end
863 449 julius 
        expected_address_num = 0;
864 
     end
865 
 
866 
   task add_expected_address;
867 
      input [31:0] expected_pc;
868 
      begin
869 
         if (expected_address_num == 31)
870 
           begin
871 
              $display("%t: Too many branches not reached",$time);
872 
              #100;
873 
              $finish;
874 
           end
875 
         if (expected_addresses_waiting[expected_address_num])
876 
           begin
877 
              $display("%t: expected_addresses tracker bugged out. expected_address_num = %0d",$time,expected_address_num);
878 
              #100;
879 
              $finish;
880 
           end
881 
         else
882 
           begin
883 
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
884 
              // Debugging output...
885 
              $display("%t: Adding address 0x%h to expected list index %0d",$time, expected_pc,expected_address_num);
886 
`endif
887 
              // Put the expected PC in the list, increase the index
888 
              expected_addresses[expected_address_num] = expected_pc;
889 
              expected_addresses_waiting[expected_address_num] = 1;
890 
              expected_address_num = expected_address_num + 1;
891 
           end // else: !if(expected_addresses_waiting[expected_address_num])
892 
      end
893 
   endtask // add_address_to_expect
894 
 
895 
   // Use this in the case that there's an execption after a jump, in which
896 
   // case we'll have two entries when we finally jump back (the one the
897 
   // original jump put in, and the one put in by the l.rfe or l.jr/ when
898 
   // returning outside of exception handler), so mark this one as OK for
899 
   // removing the duplicate of
900 
   task mark_duplicate_expected_address;
901 
      begin
902 
         // This will always be done on the first instruction of an exception
903 
         // that has occured after a delay slot instruction, so
904 
         // expected_address_num will be one past the entry for the one we will
905 
         // get a duplicate return call for
906 
         duplicate_expected_addresses_waiting[expected_address_num-1] = 1;
907 
      end
908 
   endtask // mark_duplicate_expected_address
909 
 
910 
 
911 
   task check_expected_address;
912 
      input [31:0] pc;
913 
      input        expecting_hit;
914 
      integer      i,j;
915 
      reg          hit;
916 
      reg          duplicates;
917 348 julius 
 
918 449 julius 
      begin
919 
         hit = 0;
920 
         //$display("%t: check_expected_addr 0x%h, index %0d",
921 
         // $time,pc, expected_address_num);
922 
         if (expected_address_num > 0)
923 
           begin
924 
              // First check the last jump we did
925 
              if (expected_addresses[expected_address_num-1] == pc)
926 
                begin
927 
                   // Jump address hit
928 
                   // Debugging printout:
929 
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
930 
                   $display("%t: PC address 0x%h was in expected list, index %0d",$time, pc,expected_address_num-1);
931 
`endif
932 
                   expected_address_num = expected_address_num-1;
933 
                   expected_addresses_waiting[expected_address_num] = 0;
934 
                   hit = 1;
935 
                end
936 
              else
937 
                begin
938 
                   // Check through the list
939 
                   for(i=0;i<expected_address_num;i=i+1)
940 
                     begin
941 
                        if (expected_addresses[i] == pc)
942 
                          begin
943 
                             // Jump address hit
944 
                             // Debugging printout:
945 
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
946 
                             $display("%t: PC address 0x%h was in expected list, index %0d",$time, pc,i);
947 
`endif
948 
                             for(j=i;j<expected_address_num;j=j+1)
949 
                               begin
950 
                                  // Pull all of the ones above us down one
951 
                                  expected_addresses_waiting[j]
952 
                                    = expected_addresses_waiting[j+1];
953 
                                  expected_addresses[j]
954 
                                    = expected_addresses[j+1];
955 
                                  duplicate_expected_addresses_waiting[j]
956 
                                    = duplicate_expected_addresses_waiting[j+1];
957 
                               end
958 
                             expected_address_num = expected_address_num-1;
959 
                             hit = 1;
960 
                             // quit out. only allow 1 hit
961 
                             i = expected_address_num;
962 
                          end
963 
                     end
964 
                end // else: !if(expected_addresses[expected_ad...
965 
           end // if (expected_address_num > 0)
966 348 julius 
 
967 449 julius 
         // Check for duplicates this way because of the way we've declared
968 
         // the array...
969 
         duplicates=0;
970 
         for(i=0;i<32;i=i+1)
971 
           duplicates = duplicates | duplicate_expected_addresses_waiting[i];
972 
 
973 
         if (hit & duplicates)
974 
           begin
975 
              // If we got a hit, check for duplicates we're also meant to clear
976 
`ifdef OR1200_MONITOR_JUMPTRACK_DEBUG_OUTPUT
977 
              $display;
978 
`endif
979 
              for(i=0;i<expected_address_num;i=i+1)
980 
                begin
981 
                   if(duplicate_expected_addresses_waiting[i] &
982 
                      expected_addresses_waiting[i] &
983 
                      expected_addresses[i] == pc)
984 
                     begin
985 
                        // Found a duplicate call address, clear it
986 
                        duplicate_expected_addresses_waiting[i] = 0;
987 
                        expected_addresses_waiting[i] = 0;
988 
 
989 
                        // Now reorder the list - pull all the ones above us
990 
                        // down by one
991 
                        for(j=i;j<expected_address_num;j=j+1)
992 
                          begin
993 
                             expected_addresses_waiting[j] = expected_addresses_waiting[j+1];
994 
                             expected_addresses[j] = expected_addresses[j+1];
995 
                             duplicate_expected_addresses_waiting[j] = duplicate_expected_addresses_waiting[j+1];
996 
                          end
997 
                        expected_address_num = expected_address_num - 1;
998 
                     end
999 
                end // for (i=0;i<expected_address_num;i=i+1)
1000 
           end // if (hit & duplicates)
1001 
 
1002 
         if (expecting_hit & !hit)
1003 
           begin
1004 
              // Expected this address to be one we're supposed to jump to, but it wasn't!
1005 
              $display("%t: Failed to find current PC, 0x%h, in expected PCs for branches/jumps",$time,pc);
1006 
              #100;
1007 
              $finish;
1008 
           end
1009 
 
1010 
      end
1011 
   endtask // check_expected_address
1012 
 
1013 
   // Task to assert value of GPR
1014 
   task assert_gpr_val;
1015 
      input [5:0] regnum;
1016 
      input [31:0] assert_value;
1017 
      input [31:0] pc;
1018 
      reg [31:0]   reg_val;
1019 
 
1020 
      begin
1021 
         get_gpr(regnum, reg_val);
1022 
         if (reg_val !== assert_value)
1023 
           begin
1024 
              $display("%t: Assert r%0d value (0x%h) = 0x%h failed. pc=0x%h",
1025 
                       $time, regnum, reg_val, assert_value,pc);
1026 
              #100;
1027 
              $finish;
1028 
           end
1029 
      end
1030 
   endtask // assert_gpr_val
1031 
 
1032 
   // Task to assert something is true
1033 
   task assert_this;
1034 
      input assert_result;
1035 
      input [31:0] pc;
1036 
      begin
1037 
         if (!assert_result)
1038 
           begin
1039 
              $display("%t: Assert failed for instruction at pc=0x%h",
1040 
                       $time , pc);
1041 
              #100;
1042 
              $finish;
1043 
           end
1044 
      end
1045 
   endtask // assert_gpr_val
1046 
 
1047 
   // The jumping variable doesn't get updated until we do the proper check of
1048 
   // the current instruction reaching the writeback stage. We need to know
1049 
   // earlier, eg. in the exception checking part, if this instruction will
1050 
   // jump. We do that with this task.
1051 
   task check_for_jump;
1052 
      input [31:0] insn;
1053 
      reg [5:0]    opcode;
1054 
      reg          flag;
1055 
      begin
1056 
         opcode = insn[`OR1K_OPCODE_POS];
1057 
         // Use the flag from the previous instruction, as the decision
1058 
         // is made in the execute stage not in te writeback stage,
1059 
         // which is where we're getting our instructions.
1060 
         flag = previous_sr[`OR1200_SR_F];
1061 
 
1062 
         case (opcode)
1063 
           `OR1200_OR32_J,
1064 
             `OR1200_OR32_JR,
1065 
             `OR1200_OR32_JAL,
1066 
             `OR1200_OR32_JALR:
1067 
               will_jump = 1;
1068 
           `OR1200_OR32_BNF:
1069 
             will_jump = !flag;
1070 
           `OR1200_OR32_BF:
1071 
             will_jump = flag;
1072 
           default:
1073 
             will_jump = 0;
1074 
         endcase // case (opcode)
1075 
      end
1076 
   endtask // check_for_jump
1077 
 
1078 
 
1079 
 
1080 
   // Detect exceptions from the processor here
1081 
   reg [13:0] except_trig_r;
1082 
   reg        exception_coming;
1083 
 
1084 
   always @(posedge `CPU_CORE_CLK)
1085 
     if (`OR1200_TOP.iwb_rst_i)
1086 
       begin
1087 
          except_trig_r = 0;
1088 
          exception_coming = 0;
1089 
          except_during_rfe = 0;
1090 
       end
1091 
     else if ((|`OR1200_TOP.`CPU_cpu.`CPU_except.except_trig) && !exception_coming)
1092 
       begin
1093 
          exception_coming  = 1;
1094 
          except_trig_r = `OR1200_TOP.`CPU_cpu.`CPU_except.except_trig;
1095 
          except_during_rfe = rfe;
1096 
       end
1097 
 
1098 
   task check_incoming_exceptions;
1099 
      begin
1100 
 
1101 
         // Exception timing  - depends on the trigger.
1102 
         // Appears to be:
1103 
         // tick timer - dslot - 1 instruction delay, else 2
1104 
         // tlb lookasides - 1 instruction for both
1105 
 
1106 
         casex (except_trig_r)
1107 
           13'b1_xxxx_xxxx_xxxx: begin
1108 
              //except_type <= #1 `OR1200_EXCEPT_TICK;
1109 
              exception_here = exception_coming2;
1110 
              exception_coming2 = jump_dslot ? exception_coming: exception_coming1 ;
1111 
              exception_coming1 = jump_dslot ? 0 : exception_coming;
1112 
           end
1113 
           13'b0_1xxx_xxxx_xxxx: begin
1114 
              //except_type <= #1 `OR1200_EXCEPT_INT;
1115 
              #1;
1116 
           end
1117 
           13'b0_01xx_xxxx_xxxx: begin
1118 
              //except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
1119 
              exception_here = exception_coming2;
1120 
              exception_coming2 = jump_dslot ? exception_coming : exception_coming1 ;
1121 
              exception_coming1 = jump_dslot ? 0 : exception_coming;
1122 
           end
1123 
           13'b0_001x_xxxx_xxxx: begin
1124 
              //except_type <= #1 `OR1200_EXCEPT_IPF;
1125 
              exception_here = exception_coming2;
1126 
              exception_coming2 = jump_dslot ? exception_coming : exception_coming1 ;
1127 
              exception_coming1 = jump_dslot ? 0 : exception_coming;
1128 
           end
1129 
           13'b0_0001_xxxx_xxxx: begin
1130 
              //except_type <= #1 `OR1200_EXCEPT_BUSERR;
1131 
              exception_here = exception_coming;
1132 
              exception_coming2 = 0;
1133 
              exception_coming1 = 0;
1134 
           end
1135 
           13'b0_0000_1xxx_xxxx: begin
1136 
              //except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
1137 
              if (will_jump)
1138 
                begin
1139 
                   // Writeback stage instruction will jump, and we have an
1140 
                   // illegal instruction in the decode/execute stage, which is
1141 
                   // the delay slot, so indicate the exception is coming...
1142 
                   exception_here = exception_coming2;
1143 
                   exception_coming2 = exception_coming;
1144 
                   exception_coming1 = 0;
1145 
                end
1146 
              else
1147 
                begin
1148 
                   exception_here = jump_dslot ?
1149 
                                    exception_coming2 : exception_coming;
1150 
                   exception_coming2 = jump_dslot ? exception_coming : 0;
1151 
                   exception_coming1 = 0;
1152 
                end
1153 
           end
1154 
           13'b0_0000_01xx_xxxx: begin
1155 
              //except_type <= #1 `OR1200_EXCEPT_ALIGN;
1156 
              if(will_jump)
1157 
                begin
1158 
                   exception_here = exception_coming2;
1159 
                   exception_coming2 = exception_coming;
1160 
                   exception_coming1 = 0;
1161 
                end
1162 
              else
1163 
                begin
1164 
                   exception_here =  (rfe) ? exception_coming : exception_coming2;
1165 
                   exception_coming2 = (rfe) ? 0 : exception_coming;
1166 
                   exception_coming1 = 0;
1167 
                end
1168 
           end
1169 
           13'b0_0000_001x_xxxx: begin
1170 
              //except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
1171 
              // Looks like except_trig goes high here after we check the
1172 
              // instruction before the itlb miss after a delay slot, so we
1173 
              // miss the dslot variable (it gets propegated before we call
1174 
              // this task) so we use the jumped variable here to see if we
1175 
              // are an exception after a delay slot
1176 
              //exception_here = (jumped | rfe) ? exception_coming : exception_coming2 ;
1177 
              //exception_coming2 = (jumped | rfe) ? 0 : exception_coming;
1178 
 
1179 
              exception_here = (jumped | rfe) ? exception_coming : exception_coming2 ;
1180 
              exception_coming2 = (jumped | rfe) ? 0 : exception_coming;
1181 
 
1182 
              exception_coming1 = 0;
1183 
           end
1184 
           13'b0_0000_0001_xxxx: begin
1185 
              //except_type <= #1 `OR1200_EXCEPT_DPF;
1186 
              if (jumped) begin // Jumped onto illegal instruction
1187 
                 exception_here = exception_coming ;
1188 
                 exception_coming2 = 0;
1189 
                 exception_coming1 = 0;
1190 
              end
1191 
              else begin
1192 
                 exception_here =  exception_coming2;
1193 
                 exception_coming2 = exception_coming;
1194 
                 exception_coming1 = 0;
1195 
              end
1196 
           end
1197 
           13'b0_0000_0000_1xxx: begin  // Data Bus Error
1198 
              //except_type <= #1 `OR1200_EXCEPT_BUSERR;
1199 
              exception_here = exception_coming2 ;
1200 
              exception_coming2 = exception_coming;
1201 
              exception_coming1 = 0;
1202 
           end
1203 
           13'b0_0000_0000_01xx: begin
1204 
              //except_type <= #1 `OR1200_EXCEPT_RANGE;
1205 
              #1;
1206 
           end
1207 
           13'b0_0000_0000_001x: begin
1208 
              // trap
1209 
              #1;
1210 
           end
1211 
           13'b0_0000_0000_0001: begin
1212 
              //except_type <= #1 `OR1200_EXCEPT_SYSCALL;
1213 
              exception_here = exception_coming2;
1214 
              exception_coming2 = jumped ? exception_coming: exception_coming1 ;
1215 
              exception_coming1 = jumped ? 0 : exception_coming;
1216 
           end
1217 
         endcase // casex (except_trig_r)
1218 
 
1219 
         exception_coming = 0;
1220 
         except_during_rfe = 0;
1221 
 
1222 
      end
1223 
   endtask // check_incoming_exceptions
1224 
 
1225 
 
1226 
 
1227 
 
1228 351 julius 
   /////////////////////////////////////////////////////////////////////////
1229 449 julius 
   // Execution tracking task
1230 351 julius 
   /////////////////////////////////////////////////////////////////////////
1231 348 julius 
 
1232 449 julius 
 
1233 
`ifdef OR1200_SYSTEM_CHECKER
1234 
   always @(posedge `CPU_CORE_CLK)
1235 
     begin
1236 
        if (`OR1200_TOP.iwb_rst_i)
1237 
          begin
1238 
             exception_coming1 = 0;exception_coming2 = 0;exception_here= 0;
1239 
             jumping = 0; jump_dslot = 0; jumped = 0;
1240 
             rfe = 0;
1241 
          end
1242 
        if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze) begin
1243 
           //#2 ;
1244 
           // If instruction isn't a l.nop with bit 16 set (implementation's
1245 
           // filler instruction in pipeline), and do not have an exception
1246 
           // signaled with a dslot instruction in the execute stage
1247 
           if (((`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[`OR1K_OPCODE_POS] !=
1248 
                 `OR1200_OR32_NOP) || !`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn[16])
1249 
               && !(`OR1200_TOP.`CPU_cpu.`CPU_except.except_flushpipe &&
1250 
                    `OR1200_TOP.`CPU_cpu.`CPU_except.ex_dslot)) // and not except start
1251 
             begin
1252 351 julius 
 
1253 449 julius 
                // Propegate jump-tracking variables
1254 
                // If was exception in delay slot, we didn't actually jump
1255 
                // so don't set jumped in this case.
1256 
                jumped = exception_here ? 0 : jump_dslot;
1257 
                jump_dslot = jumping;
1258 
                jumping = 0;
1259 
                rfe = 0;
1260 
 
1261 
                // Now, check if current instruction will jump/branch, this is
1262 
                // needed by the exception checking code, sets will_jump=1
1263 
                check_for_jump(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
1264 
 
1265 
                // Now check if it's an exception this instruction
1266 
                check_incoming_exceptions;
1267 
 
1268 
                // Case where we just went to an exception after a jump, so we
1269 
                // mark the address we were meant to jump to as a place which will
1270 
                // have duplicate return entries in the expected address list
1271 
                if (exception_here & (jumped | jump_dslot))
1272 
                  begin
1273 
                     $display("%t: marked as jump address with exception (dup)"
1274 
                              ,$time);
1275 
                     mark_duplicate_expected_address;
1276 
                  end
1277 
 
1278 
                or1200_check_execution(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn,
1279 
                                       `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc,
1280 
                                       exception_here);
1281 
                //$write("%t: pc:0x%h\t",$time,
1282 
                //       `OR1200_TOP.`CPU_cpu.`CPU_except.wb_pc);
1283 
                // Decode the instruction, print it out
1284 
                //or1200_print_op(`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_insn);
1285 
                //$write("\t exc:%0h dsl:%0h\n",exception_here,jump_dslot);
1286 
 
1287 
 
1288 
 
1289 
             end
1290 
        end // if (!`OR1200_TOP.`CPU_cpu.`CPU_ctrl.wb_freeze)
1291 
     end // always @ (posedge `CPU_CORE_CLK)
1292 
`endif
1293 
 
1294 
 
1295 
   task or1200_check_execution;
1296 
      input [31:0] insn;
1297 
      input [31:0] pc;
1298 
      input        exception;
1299 
 
1300 
      reg [5:0]    opcode;
1301 
 
1302 
      reg [25:0]   j_imm;
1303 
      reg [25:0]   br_imm;
1304 
 
1305 
      reg [4:0]    rD_num, rA_num, rB_num;
1306 
      reg [31:0]   rD_val, rA_val, rB_val;
1307 
      reg [15:0]   imm_16bit;
1308 
 
1309 
      reg [15:0]   mtspr_imm;
1310 
 
1311 
      reg [3:0]    alu_op;
1312 
      reg [1:0]    shrot_op;
1313 
 
1314 
      reg [5:0]    shroti_imm;
1315 
 
1316 
      reg [5:0]    sf_op;
1317 
 
1318 
      reg [5:0]    xsync_op;
1319 
 
1320 
      reg          flag;
1321 
 
1322 
      reg [31:0]   br_j_ea; // Branch/jump effective address
1323 
 
1324 
 
1325 
      begin
1326 
 
1327 
         // Instruction opcode
1328 
         opcode = insn[`OR1K_OPCODE_POS];
1329 
         // Immediates for jump or branch instructions
1330 
         j_imm = insn[`OR1K_J_BR_IMM_POS];
1331 
         br_imm = insn[`OR1K_J_BR_IMM_POS];
1332 
         // Register numbers (D, A and B)
1333 
         rD_num = insn[`OR1K_RD_POS];
1334 
         rA_num = insn[`OR1K_RA_POS];
1335 
         rB_num = insn[`OR1K_RB_POS];
1336 
         // Bottom 16 bits when used as immediates in various instructions
1337 
         imm_16bit = insn[15:0];
1338 
         // 16-bit immediate for mtspr instructions
1339 
         mtspr_imm = {insn[25:21],insn[10:0]};
1340 
         // ALU op for ALU instructions
1341 
         alu_op = insn[`OR1K_ALU_OP_POS];
1342 
         // Shift-rotate op for SHROT ALU instructions
1343 
         shrot_op = insn[`OR1K_SHROT_OP_POS];
1344 
         shroti_imm = insn[`OR1K_SHROTI_IMM_POS];
1345 
 
1346 
         // Set flag op
1347 
         sf_op = insn[`OR1K_SF_OP];
1348 
 
1349 
         // Xsync/syscall/trap opcode
1350 
         xsync_op = insn[`OR1K_XSYNC_OP_POS];
1351 
 
1352 
         // Use the flag from the previous instruction, as the decision
1353 
         // is made in the execute stage not in te writeback stage,
1354 
         // which is where we're getting our instructions.
1355 
         flag = previous_sr[`OR1200_SR_F];
1356 
 
1357 
         update_current_gprs;
1358 
 
1359 
         // Check MSbit of the immediate, sign extend if set
1360 
         br_j_ea = j_imm[25] ? pc + {4'hf,j_imm,2'b00} :
1361 
                   pc + {4'h0,j_imm,2'b00};
1362 
 
1363 
         if (exception)
1364 
           begin
1365 
              $display("%t: exception - at 0x%x",$time, pc);
1366 
              // get epcr, put it in the addresses we expect to jump
1367 
              // back to
1368 
              // Maybe DON'T do this. Because maybe in linux things we
1369 
              // interrupt out of, we don't want to execute them again?
1370 
              //add_expected_address(current_epcr);
1371 
           end
1372 
 
1373 
 
1374 
         check_expected_address(pc, (jumped & !exception));
1375 
 
1376 
         rfe = 0;
1377 
 
1378 
         case (opcode)
1379 
           `OR1200_OR32_J:
1380 
             begin
1381 
                //
1382 
                // PC < - exts(Immediate < < 2) + JumpInsnAddr
1383 
                //
1384 
                //The immediate value is shifted left two bits, sign-extended
1385 
                // to program counter width, and then added to the address of
1386 
                // the jump instruction. The result is the effective address
1387 
                // of the jump. The program unconditionally jumps to EA with
1388 
                // a delay of one instruction.
1389 
 
1390 
                add_expected_address(br_j_ea);
1391 
 
1392 
                jumping = 1;
1393 
             end
1394 
           `OR1200_OR32_JAL:
1395 
             begin
1396 
                //
1397 
                //PC < - exts(Immediate < < 2) + JumpInsnAddr
1398 
                //LR < - DelayInsnAddr + 4
1399 
                //
1400 
                // Link reg is r9, check it is PC+8
1401 
                //
1402 
                add_expected_address(br_j_ea);
1403 
                assert_gpr_val(9, pc+8, pc);
1404 
                jumping = 1;    //
1405 
             end
1406 
           `OR1200_OR32_BNF:
1407 
             begin
1408 
                //EA < - exts(Immediate < < 2) + BranchInsnAddr
1409 
                //PC < - EA if SR[F] cleared
1410 
                if (!flag)
1411 
                  begin
1412 
                     add_expected_address(br_j_ea);
1413 
                     jumping = 1;
1414 
                  end
1415 
             end
1416 
           `OR1200_OR32_BF:
1417 
             begin
1418 
                //EA < - exts(Immediate < < 2) + BranchInsnAddr
1419 
                //PC < - EA if SR[F] set
1420 
                if (flag)
1421 
                  begin
1422 
                     add_expected_address(br_j_ea);
1423 
                     jumping = 1;
1424 
                  end
1425 
             end
1426 
           `OR1200_OR32_RFE:
1427 
             begin
1428 
                add_expected_address(current_epcr);
1429 
                // jumping variable keeps track of jumps/branches with delay
1430 
                // slot - there is none for l.rfe
1431 
                rfe = 1;
1432 
             end
1433 
           `OR1200_OR32_JR:
1434 
             begin
1435 
                //PC < - rB
1436 
                get_gpr(rB_num, rB_val);
1437 
                add_expected_address(rB_val);
1438 
                jumping = 1;
1439 
             end
1440 
           `OR1200_OR32_JALR:
1441 
             begin
1442 
                //PC < - rB
1443 
                //LR < - DelayInsnAddr + 4
1444 
                get_gpr(rB_num, rB_val);
1445 
                add_expected_address(rB_val);
1446 
                assert_gpr_val(9, pc+8, pc);
1447 
                jumping = 1;
1448 
             end
1449 
           /*
1450 
            `OR1200_OR32_LWZ,
1451 
            `OR1200_OR32_LBZ,
1452 
            `OR1200_OR32_LBS,
1453 
            `OR1200_OR32_LHZ,
1454 
            `OR1200_OR32_LHS,
1455 
            `OR1200_OR32_SW,
1456 
            `OR1200_OR32_SB,
1457 
            `OR1200_OR32_SH:
1458 
            begin
1459 
            // Should result in databus access if data cache disabled
1460 
            $display("%t: lsu instruction",$time);
1461 
end
1462 
 
1463 
            `OR1200_OR32_MFSPR,
1464 
            `OR1200_OR32_MTSPR:
1465 
            begin
1466 
            // Confirm RF values end up in the correct SPR
1467 
            $display("%t: mxspr",$time);
1468 
end
1469 
 
1470 
            `OR1200_OR32_MOVHI,
1471 
            `OR1200_OR32_ADDI,
1472 
            `OR1200_OR32_ADDIC,
1473 
            `OR1200_OR32_ANDI,
1474 
            `OR1200_OR32_ORI,
1475 
            `OR1200_OR32_XORI,
1476 
            `OR1200_OR32_MULI,
1477 
            `OR1200_OR32_ALU:
1478 
            begin
1479 
            // Double check operations done on RF and immediate values
1480 
            $display("%t: ALU op",$time);
1481 
end
1482 
 
1483 
            `OR1200_OR32_SH_ROTI:
1484 
            begin
1485 
            // Rotate according to immediate - maybe should be in ALU ops
1486 
            $display("%t: rotate op",$time);
1487 
end
1488 
 
1489 
            `OR1200_OR32_SFXXI,
1490 
            `OR1200_OR32_SFXX:
1491 
            begin
1492 
            // Set flag - do the check oursevles, check flag
1493 
            $display("%t: set flag op",$time);
1494 
end
1495 
 
1496 
            `OR1200_OR32_MACI,
1497 
            `OR1200_OR32_MACMSB:
1498 
            begin
1499 
            // Either, multiply signed and accumulate, l.mac
1500 
            // or multiply signed and subtract, l.msb
1501 
            $display("%t: MAC op",$time);
1502 
end
1503 
            */
1504 
 
1505 
           /*default:
1506 
            begin
1507 
            $display("%t: Unknown opcode 0x%h at pc 0x%x\n",
1508 
            $time,opcode, pc);
1509 
end
1510 
            */
1511 
         endcase // case (opcode)
1512 
 
1513 
         update_previous_gprs;
1514 
 
1515 
      end
1516 
   endtask // or1200_check_execution
1517 348 julius 
 
1518 351 julius 
 
1519 449 julius 
   /////////////////////////////////////////////////////////////////////////
1520 
   // Instruction decode task
1521 
   /////////////////////////////////////////////////////////////////////////
1522 351 julius 
 
1523 
   task or1200_print_op;
1524 
      input [31:0] insn;
1525 
 
1526 
      reg [5:0]    opcode;
1527 
 
1528 
      reg [25:0]   j_imm;
1529 
      reg [25:0]   br_imm;
1530 
 
1531 
      reg [4:0]    rD_num, rA_num, rB_num;
1532 
      reg [31:0]   rA_val, rB_val;
1533 
      reg [15:0]   imm_16bit;
1534 
      reg [10:0]   imm_split16bit;
1535 
 
1536 
      reg [3:0]    alu_op;
1537 
      reg [1:0]    shrot_op;
1538 
 
1539 
      reg [5:0]    shroti_imm;
1540 
 
1541 449 julius 
      reg [5:0]    sf_op;
1542 351 julius 
 
1543 449 julius 
      reg [5:0]    xsync_op;
1544 
 
1545 351 julius 
      begin
1546 
         // Instruction opcode
1547 449 julius 
         opcode = insn[`OR1K_OPCODE_POS];
1548 351 julius 
         // Immediates for jump or branch instructions
1549 449 julius 
         j_imm = insn[`OR1K_J_BR_IMM_POS];
1550 
         br_imm = insn[`OR1K_J_BR_IMM_POS];
1551 351 julius 
         // Register numbers (D, A and B)
1552 449 julius 
         rD_num = insn[`OR1K_RD_POS];
1553 
         rA_num = insn[`OR1K_RA_POS];
1554 
         rB_num = insn[`OR1K_RB_POS];
1555 351 julius 
         // Bottom 16 bits when used as immediates in various instructions
1556 
         imm_16bit = insn[15:0];
1557 
         // Bottom 11 bits used as immediates for l.sX instructions
1558 
 
1559 
         // Split 16-bit immediate for l.mtspr/l.sX instructions
1560 
         imm_split16bit = {insn[25:21],insn[10:0]};
1561 
         // ALU op for ALU instructions
1562 449 julius 
         alu_op = insn[`OR1K_ALU_OP_POS];
1563 351 julius 
         // Shift-rotate op for SHROT ALU instructions
1564 449 julius 
         shrot_op = insn[`OR1K_SHROT_OP_POS];
1565 
         shroti_imm = insn[`OR1K_SHROTI_IMM_POS];
1566 351 julius 
 
1567 
         // Set flag op
1568 449 julius 
         sf_op = insn[`OR1K_SF_OP];
1569 351 julius 
 
1570 449 julius 
         // Xsync/syscall/trap opcode
1571 
         xsync_op = insn[`OR1K_XSYNC_OP_POS];
1572 
 
1573 351 julius 
         case (opcode)
1574 
           `OR1200_OR32_J:
1575 
             begin
1576 449 julius 
                $fwrite(finsn,"l.j 0x%h", {j_imm,2'b00});
1577 351 julius 
             end
1578 
 
1579 
           `OR1200_OR32_JAL:
1580 
             begin
1581 449 julius 
                $fwrite(finsn,"l.jal 0x%h", {j_imm,2'b00});
1582 351 julius 
             end
1583 
 
1584 
           `OR1200_OR32_BNF:
1585 
             begin
1586 449 julius 
                $fwrite(finsn,"l.bnf 0x%h", {br_imm,2'b00});
1587 351 julius 
             end
1588 
 
1589 
           `OR1200_OR32_BF:
1590 
             begin
1591 449 julius 
                $fwrite(finsn,"l.bf 0x%h", {br_imm,2'b00});
1592 351 julius 
             end
1593 
 
1594 
           `OR1200_OR32_RFE:
1595 
             begin
1596 449 julius 
                $fwrite(finsn,"l.rfe");
1597 351 julius 
             end
1598 
 
1599 
           `OR1200_OR32_JR:
1600 
             begin
1601 449 julius 
                $fwrite(finsn,"l.jr r%0d",rB_num);
1602 351 julius 
             end
1603 
 
1604 
           `OR1200_OR32_JALR:
1605 
             begin
1606 449 julius 
                $fwrite(finsn,"l.jalr r%0d",rB_num);
1607 351 julius 
             end
1608 
 
1609 
           `OR1200_OR32_LWZ:
1610 
             begin
1611 449 julius 
                $fwrite(finsn,"l.lwz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1612 351 julius 
             end
1613 
 
1614 
           `OR1200_OR32_LBZ:
1615 
             begin
1616 449 julius 
                $fwrite(finsn,"l.lbz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1617 351 julius 
             end
1618 
 
1619 
           `OR1200_OR32_LBS:
1620 
             begin
1621 449 julius 
                $fwrite(finsn,"l.lbs r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1622 351 julius 
             end
1623 
 
1624 
           `OR1200_OR32_LHZ:
1625 
             begin
1626 449 julius 
                $fwrite(finsn,"l.lhz r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1627 351 julius 
             end
1628 
 
1629 
           `OR1200_OR32_LHS:
1630 
             begin
1631 449 julius 
                $fwrite(finsn,"l.lhs r%0d,0x%0h(r%0d)",rD_num,imm_16bit,rA_num);
1632 351 julius 
             end
1633 
 
1634 
           `OR1200_OR32_SW:
1635 
             begin
1636 449 julius 
                $fwrite(finsn,"l.sw 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
1637 351 julius 
             end
1638 
 
1639 
           `OR1200_OR32_SB:
1640 
             begin
1641 449 julius 
                $fwrite(finsn,"l.sb 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
1642 351 julius 
             end
1643 
 
1644 
           `OR1200_OR32_SH:
1645 
             begin
1646 449 julius 
                $fwrite(finsn,"l.sh 0x%0h(r%0d),r%0d",imm_split16bit,rA_num,rB_num);
1647 351 julius 
             end
1648 
 
1649 
           `OR1200_OR32_MFSPR:
1650 
             begin
1651 449 julius 
                $fwrite(finsn,"l.mfspr r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit,);
1652 351 julius 
             end
1653 
 
1654 
           `OR1200_OR32_MTSPR:
1655 
             begin
1656 449 julius 
                $fwrite(finsn,"l.mtspr r%0d,r%0d,0x%h",rA_num,rB_num,imm_split16bit);
1657 351 julius 
             end
1658 
 
1659 
           `OR1200_OR32_MOVHI:
1660 
             begin
1661 
                if (!insn[16])
1662 449 julius 
                  $fwrite(finsn,"l.movhi r%0d,0x%h",rD_num,imm_16bit);
1663 351 julius 
                else
1664 449 julius 
                  $fwrite(finsn,"l.macrc r%0d",rD_num);
1665 351 julius 
             end
1666 
 
1667 
           `OR1200_OR32_ADDI:
1668 
             begin
1669 449 julius 
                $fwrite(finsn,"l.addi r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1670 351 julius 
             end
1671 
 
1672 
           `OR1200_OR32_ADDIC:
1673 
             begin
1674 449 julius 
                $fwrite(finsn,"l.addic r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1675 351 julius 
             end
1676 
 
1677 
           `OR1200_OR32_ANDI:
1678 
             begin
1679 449 julius 
                $fwrite(finsn,"l.andi r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1680 351 julius 
             end
1681 
 
1682 
           `OR1200_OR32_ORI:
1683 
             begin
1684 449 julius 
                $fwrite(finsn,"l.ori r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1685 351 julius 
             end
1686 
 
1687 
           `OR1200_OR32_XORI:
1688 
             begin
1689 449 julius 
                $fwrite(finsn,"l.xori r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1690 351 julius 
             end
1691 
 
1692 
           `OR1200_OR32_MULI:
1693 
             begin
1694 449 julius 
                $fwrite(finsn,"l.muli r%0d,r%0d,0x%h",rD_num,rA_num,imm_16bit);
1695 351 julius 
             end
1696 
 
1697 
           `OR1200_OR32_ALU:
1698 
             begin
1699 
                case(alu_op)
1700 
                  `OR1200_ALUOP_ADD:
1701 449 julius 
                    $fwrite(finsn,"l.add ");
1702 351 julius 
                  `OR1200_ALUOP_ADDC:
1703 449 julius 
                    $fwrite(finsn,"l.addc ");
1704 351 julius 
                  `OR1200_ALUOP_SUB:
1705 449 julius 
                    $fwrite(finsn,"l.sub ");
1706 351 julius 
                  `OR1200_ALUOP_AND:
1707 449 julius 
                    $fwrite(finsn,"l.and ");
1708 351 julius 
                  `OR1200_ALUOP_OR:
1709 449 julius 
                    $fwrite(finsn,"l.or ");
1710 351 julius 
                  `OR1200_ALUOP_XOR:
1711 449 julius 
                    $fwrite(finsn,"l.xor ");
1712 351 julius 
                  `OR1200_ALUOP_MUL:
1713 449 julius 
                    $fwrite(finsn,"l.mul ");
1714 351 julius 
                  `OR1200_ALUOP_SHROT:
1715 
                    begin
1716 
                       case(shrot_op)
1717 
                         `OR1200_SHROTOP_SLL:
1718 449 julius 
                           $fwrite(finsn,"l.sll ");
1719 351 julius 
                         `OR1200_SHROTOP_SRL:
1720 449 julius 
                           $fwrite(finsn,"l.srl ");
1721 351 julius 
                         `OR1200_SHROTOP_SRA:
1722 449 julius 
                           $fwrite(finsn,"l.sra ");
1723 351 julius 
                         `OR1200_SHROTOP_ROR:
1724 449 julius 
                           $fwrite(finsn,"l.ror ");
1725 351 julius 
                       endcase // case (shrot_op)
1726 
                    end
1727 
                  `OR1200_ALUOP_DIV:
1728 449 julius 
                    $fwrite(finsn,"l.div ");
1729 351 julius 
                  `OR1200_ALUOP_DIVU:
1730 449 julius 
                    $fwrite(finsn,"l.divu ");
1731 351 julius 
                  `OR1200_ALUOP_CMOV:
1732 449 julius 
                    $fwrite(finsn,"l.cmov ");
1733 351 julius 
                endcase // case (alu_op)
1734 449 julius 
                $fwrite(finsn,"r%0d,r%0d,r%0d",rD_num,rA_num,rB_num);
1735 351 julius 
             end
1736 
 
1737 
           `OR1200_OR32_SH_ROTI:
1738 
             begin
1739 
                case(shrot_op)
1740 
                  `OR1200_SHROTOP_SLL:
1741 449 julius 
                    $fwrite(finsn,"l.slli ");
1742 351 julius 
                  `OR1200_SHROTOP_SRL:
1743 449 julius 
                    $fwrite(finsn,"l.srli ");
1744 351 julius 
                  `OR1200_SHROTOP_SRA:
1745 449 julius 
                    $fwrite(finsn,"l.srai ");
1746 351 julius 
                  `OR1200_SHROTOP_ROR:
1747 449 julius 
                    $fwrite(finsn,"l.rori ");
1748 351 julius 
                endcase // case (shrot_op)
1749 449 julius 
                $fwrite(finsn,"r%0d,r%0d,0x%h",rD_num,rA_num,shroti_imm);
1750 351 julius 
             end
1751 
 
1752 
           `OR1200_OR32_SFXXI:
1753 
             begin
1754 
                case(sf_op[2:0])
1755 
                  `OR1200_COP_SFEQ:
1756 449 julius 
                    $fwrite(finsn,"l.sfeqi ");
1757 351 julius 
                  `OR1200_COP_SFNE:
1758 449 julius 
                    $fwrite(finsn,"l.sfnei ");
1759 351 julius 
                  `OR1200_COP_SFGT:
1760 
                    begin
1761 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1762 449 julius 
                         $fwrite(finsn,"l.sfgtsi ");
1763 351 julius 
                       else
1764 449 julius 
                         $fwrite(finsn,"l.sfgtui ");
1765 351 julius 
                    end
1766 
                  `OR1200_COP_SFGE:
1767 
                    begin
1768 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1769 449 julius 
                         $fwrite(finsn,"l.sfgesi ");
1770 351 julius 
                       else
1771 449 julius 
                         $fwrite(finsn,"l.sfgeui ");
1772 351 julius 
                    end
1773 
                  `OR1200_COP_SFLT:
1774 
                    begin
1775 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1776 449 julius 
                         $fwrite(finsn,"l.sfltsi ");
1777 351 julius 
                       else
1778 449 julius 
                         $fwrite(finsn,"l.sfltui ");
1779 351 julius 
                    end
1780 
                  `OR1200_COP_SFLE:
1781 
                    begin
1782 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1783 449 julius 
                         $fwrite(finsn,"l.sflesi ");
1784 351 julius 
                       else
1785 449 julius 
                         $fwrite(finsn,"l.sfleui ");
1786 351 julius 
                    end
1787 
                endcase // case (sf_op[2:0])
1788 
 
1789 449 julius 
                $fwrite(finsn,"r%0d,0x%h",rA_num, imm_16bit);
1790 351 julius 
 
1791 
             end // case: `OR1200_OR32_SFXXI
1792 
 
1793 
           `OR1200_OR32_SFXX:
1794 
             begin
1795 
                case(sf_op[2:0])
1796 
                  `OR1200_COP_SFEQ:
1797 449 julius 
                    $fwrite(finsn,"l.sfeq ");
1798 351 julius 
                  `OR1200_COP_SFNE:
1799 449 julius 
                    $fwrite(finsn,"l.sfne ");
1800 351 julius 
                  `OR1200_COP_SFGT:
1801 
                    begin
1802 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1803 449 julius 
                         $fwrite(finsn,"l.sfgts ");
1804 351 julius 
                       else
1805 449 julius 
                         $fwrite(finsn,"l.sfgtu ");
1806 351 julius 
                    end
1807 
                  `OR1200_COP_SFGE:
1808 
                    begin
1809 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1810 449 julius 
                         $fwrite(finsn,"l.sfges ");
1811 351 julius 
                       else
1812 449 julius 
                         $fwrite(finsn,"l.sfgeu ");
1813 351 julius 
                    end
1814 
                  `OR1200_COP_SFLT:
1815 
                    begin
1816 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1817 449 julius 
                         $fwrite(finsn,"l.sflts ");
1818 351 julius 
                       else
1819 449 julius 
                         $fwrite(finsn,"l.sfltu ");
1820 351 julius 
                    end
1821 
                  `OR1200_COP_SFLE:
1822 
                    begin
1823 
                       if (sf_op[`OR1200_SIGNED_COMPARE])
1824 449 julius 
                         $fwrite(finsn,"l.sfles ");
1825 351 julius 
                       else
1826 449 julius 
                         $fwrite(finsn,"l.sfleu ");
1827 351 julius 
                    end
1828 
 
1829 
                endcase // case (sf_op[2:0])
1830 
 
1831 449 julius 
                $fwrite(finsn,"r%0d,r%0d",rA_num, rB_num);
1832 351 julius 
 
1833 
             end
1834 
 
1835 
           `OR1200_OR32_MACI:
1836 
             begin
1837 449 julius 
                $fwrite(finsn,"l.maci r%0d,0x%h",rA_num,imm_16bit);
1838 351 julius 
             end
1839 
 
1840 
           `OR1200_OR32_MACMSB:
1841 
             begin
1842 
                if(insn[3:0] == 4'h1)
1843 449 julius 
                  $fwrite(finsn,"l.mac ");
1844 351 julius 
                else if(insn[3:0] == 4'h2)
1845 449 julius 
                  $fwrite(finsn,"l.msb ");
1846 351 julius 
 
1847 449 julius 
                $fwrite(finsn,"r%0d,r%0d",rA_num,rB_num);
1848 351 julius 
             end
1849 
 
1850 
           `OR1200_OR32_NOP:
1851 
             begin
1852 449 julius 
                $fwrite(finsn,"l.nop 0x%0h",imm_16bit);
1853 351 julius 
             end
1854 
 
1855 
           `OR1200_OR32_XSYNC:
1856 
             begin
1857 
                case (xsync_op)
1858 
                  5'd0:
1859 449 julius 
                    $fwrite(finsn,"l.sys 0x%h",imm_16bit);
1860 351 julius 
                  5'd8:
1861 449 julius 
                    $fwrite(finsn,"l.trap 0x%h",imm_16bit);
1862 351 julius 
                  5'd16:
1863 449 julius 
                    $fwrite(finsn,"l.msync");
1864 351 julius 
                  5'd20:
1865 449 julius 
                    $fwrite(finsn,"l.psync");
1866 351 julius 
                  5'd24:
1867 449 julius 
                    $fwrite(finsn,"l.csync");
1868 351 julius 
                  default:
1869 
                    begin
1870 
                       $display("%t: Instruction with opcode 0x%h has bad specific type information: 0x%h",$time,opcode,insn);
1871 449 julius 
                       $fwrite(finsn,"%t: Instruction with opcode 0x%h has has bad specific type information: 0x%h",$time,opcode,insn);
1872 351 julius 
                    end
1873 
                endcase // case (xsync_op)
1874 
             end
1875 
 
1876 
           default:
1877 
             begin
1878 
                $display("%t: Unknown opcode 0x%h",$time,opcode);
1879 449 julius 
                $fwrite(finsn,"%t: Unknown opcode 0x%h",$time,opcode);
1880 351 julius 
             end
1881 
 
1882 
         endcase // case (opcode)
1883 
 
1884 
      end
1885 
   endtask // or1200_print_op
1886 
 
1887 
 
1888 
 
1889 6 julius 
endmodule

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