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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [orpsoc_testbench.v] - Blame information for rev 40

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1 6 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  ORPSoC Testbench                                            ////
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////                                                              ////
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////  Description                                                 ////
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////  ORPSoC Testbench file                                       ////
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////                                                              ////
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////  To Do:                                                      ////
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////                                                              ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - jb, jb@orsoc.se                                       ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "orpsoc_testbench_defines.v"
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module orpsoc_testbench();
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   reg clk;
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   reg rst;
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   // Setup global clock. Period defined in orpsoc_testbench_defines.v
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   initial
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     begin
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        clk <= 0;
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        rst <= 1;
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     end
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   always
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     begin
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        #((`CLOCK_PERIOD)/2) clk <= ~clk;
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     end
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   // Assert rst and then bring it low again
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   initial
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     begin
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        repeat (2) @(negedge clk);
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        rst <= 0;
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        repeat (16) @(negedge clk);
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        rst <= 1;
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     end
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   // Wires for the dut
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   wire spi_sd_sclk_o;
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   wire spi_sd_ss_o;
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   wire spi_sd_miso_i;
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   wire spi_sd_mosi_o;
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`ifdef USE_SDRAM
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   wire [15:0] mem_dat_io;
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   wire [12:0] mem_adr_o;
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   wire [1:0]  mem_dqm_o;
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   wire [1:0]  mem_ba_o;
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   wire        mem_cs_o;
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   wire        mem_ras_o;
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   wire        mem_cas_o;
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   wire        mem_we_o;
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   wire        mem_cke_o;
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   wire        spi_flash_sclk_o;
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   wire        spi_flash_ss_o;
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   wire        spi_flash_miso_i;
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   wire        spi_flash_mosi_o;
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   wire        spi_flash_w_n_o;
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   wire        spi_flash_hold_n_o;
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`endif //  `ifdef USE_SDRAM
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`ifdef USE_ETHERNET
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   wire [1:1]  eth_sync_o;
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   wire [1:1] eth_tx_o;
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   wire [1:1] eth_rx_i;
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   wire       eth_clk_i;
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   wire [1:1] eth_md_io;
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   wire [1:1] eth_mdc_o;
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`endif
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   wire       spi1_mosi_o;
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   wire       spi1_miso_i;
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   wire       spi1_ss_o;
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   wire       spi1_sclk_o;
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   wire [8-1:0] gpio_a_io;
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   wire         uart0_srx_i;
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   wire         uart0_stx_o;
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   wire         dbg_tdi_i;
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   wire         dbg_tck_i;
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   wire         dbg_tms_i;
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   wire         dbg_tdo_o;
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   wire         rst_i;
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   wire         rst_o;
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   wire         clk_i;
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   assign clk_i = clk;
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   assign rst_i = rst;
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   // Tie off some inputs   
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   assign spi1_miso_i = 0;
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   assign uart0_srx_i = 1;
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   orpsoc_top dut
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     (
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      // Outputs
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      .spi_sd_sclk_pad_o                        (spi_sd_sclk_o),
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      .spi_sd_ss_pad_o                  (spi_sd_ss_o),
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      .spi_sd_mosi_pad_o                        (spi_sd_mosi_o),
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      .spi1_mosi_pad_o                  (spi1_mosi_o),
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      .spi1_ss_pad_o                    (spi1_ss_o),
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      .spi1_sclk_pad_o                  (spi1_sclk_o),
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      .uart0_stx_pad_o                  (uart0_stx_o),
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      .dbg_tdo_pad_o                    (dbg_tdo_o),
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      .rst_pad_o                                (rst_o),
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      .gpio_a_pad_io                    (gpio_a_io[8-1:0]),
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      // Inputs
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      .spi_sd_miso_pad_i                        (spi_sd_miso_i),
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      .spi1_miso_pad_i                  (spi1_miso_i),
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      .uart0_srx_pad_i                  (uart0_srx_i),
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      .dbg_tdi_pad_i                    (dbg_tdi_i),
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      .dbg_tck_pad_i                    (dbg_tck_i),
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      .dbg_tms_pad_i                    (dbg_tms_i),
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`ifdef USE_ETHERNET
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      // Ethernet ports
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      .eth_md_pad_io                    (eth_md_io[1:1]),
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      .eth_sync_pad_o                   (eth_sync_o[1:1]),
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      .eth_tx_pad_o                     (eth_tx_o[1:1]),
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      .eth_mdc_pad_o                    (eth_mdc_o[1:1]),
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      .eth_rx_pad_i                     (eth_rx_i[1:1]),
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      .eth_clk_pad_i                    (eth_clk_i),
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`endif  //  `ifdef USE_ETHERNET      
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      // SDRAM and flash memory ports
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`ifdef USE_SDRAM
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      .mem_dat_pad_io                   (mem_dat_io[15:0]),
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      .mem_adr_pad_o                    (mem_adr_o[12:0]),
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      .mem_dqm_pad_o                    (mem_dqm_o[1:0]),
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      .mem_ba_pad_o                     (mem_ba_o[1:0]),
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      .mem_cs_pad_o                     (mem_cs_o),
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      .mem_ras_pad_o                    (mem_ras_o),
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      .mem_cas_pad_o                    (mem_cas_o),
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      .mem_we_pad_o                     (mem_we_o),
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      .mem_cke_pad_o                    (mem_cke_o),
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      .spi_flash_sclk_pad_o             (spi_flash_sclk_o),
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      .spi_flash_ss_pad_o                       (spi_flash_ss_o),
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      .spi_flash_mosi_pad_o             (spi_flash_mosi_o),
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      .spi_flash_w_n_pad_o                      (spi_flash_w_n_o),
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      .spi_flash_hold_n_pad_o           (spi_flash_hold_n_o),
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      .spi_flash_miso_pad_i             (spi_flash_miso_i),
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`endif
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      .rst_pad_i                                (rst_i),
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      .clk_pad_i                                (clk_i));
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179 40 julius
`ifdef VPI_DEBUG_ENABLE
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   // Debugging interface
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   vpi_debug_module vpi_dbg(
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                            .tms(dbg_tms_i),
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                            .tck(dbg_tck_i),
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                            .tdi(dbg_tdi_i),
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                            .tdo(dbg_tdo_o));
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`else
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   // If no VPI debugging, tie off JTAG inputs
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   assign dbg_tdi_i = 1;
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   assign dbg_tck_i = 0;
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   assign dbg_tms_i = 1;
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`endif
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195 6 julius
   // External memories, if enabled
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`ifdef USE_SDRAM
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   // SPI Flash
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   AT26DFxxx spi_flash
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     (
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      // Outputs
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      .SO                                       (spi_flash_miso_i),
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      // Inputs
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      .CSB                                      (spi_flash_ss_o),
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      .SCK                                      (spi_flash_sclk_o),
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      .SI                                       (spi_flash_mosi_o),
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      .WPB                                      (spi_flash_w_n_o)
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      //.HOLDB                          (spi_flash_hold_n_o)
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      );
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   // SDRAM
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   mt48lc16m16a2 sdram
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     (
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      // Inouts
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      .Dq                                       (mem_dat_io),
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      // Inputs
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      .Addr                             (mem_adr_o),
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      .Ba                                       (mem_ba_o),
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      .Clk                                      (clk_i),
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      .Cke                                      (mem_cke_o),
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      .Cs_n                             (mem_cs_o),
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      .Ras_n                            (mem_ras_o),
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      .Cas_n                            (mem_cas_o),
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      .We_n                             (mem_we_o),
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      .Dqm                                      (mem_dqm_o));
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`endif // !`ifdef USE_SDRAM
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initial
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  begin
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     $display("\nStarting RTL simulation of %s test\n", `TEST_NAME_STRING);
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`ifdef USE_SDRAM
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     $display("Using SDRAM - loading application from SPI flash memory\n");
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`endif
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`ifdef VCD
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     $display("VCD in %s\n", {`TEST_RESULTS_DIR,`TEST_NAME_STRING,".vcd"});
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     $dumpfile({`TEST_RESULTS_DIR,`TEST_NAME_STRING,".vcd"});
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     $dumpvars(0);
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`endif
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  end
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   // Instantiate the monitor
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   or1200_monitor monitor();
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   // If we're using UART for printf output, include the
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   // UART decoder
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`ifdef UART_PRINTF
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   // Define the UART's txt line for it to listen to
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 `define UART_TX_LINE uart0_stx_o
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 `define UART_BAUDRATE 115200
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 `include "uart_decoder.v"
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`endif
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endmodule // orpsoc_testbench
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// Local Variables:
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// verilog-library-files:("../../rtl/verilog/orp_soc.v")
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// verilog-library-directories:("." "../../rtl/verilog")
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// End:

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