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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [orpsoc_testbench.v] - Blame information for rev 856

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//////////////////////////////////////////////////////////////////////
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///                                                               //// 
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/// ORPSoC testbench                                              ////
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///                                                               ////
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/// Instantiate ORPSoC, monitors, provide stimulus                ////
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///                                                               ////
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/// Julius Baxter, julius@opencores.org                           ////
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///                                                               ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "orpsoc-defines.v"
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`include "orpsoc-testbench-defines.v"
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`include "test-defines.v"
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`include "timescale.v"
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module orpsoc_testbench;
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   reg clk = 0;
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   reg rst_n = 1; // Active LOW
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   always
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     #((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk;
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   // Reset, ACTIVE LOW
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   initial
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     begin
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        #1;
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        repeat (32) @(negedge clk)
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          rst_n <= 1;
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        repeat (32) @(negedge clk)
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          rst_n <= 0;
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        repeat (32) @(negedge clk)
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          rst_n <= 1;
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     end
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`include "orpsoc-params.v"
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`ifdef JTAG_DEBUG
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   wire                      tdo_pad_o;
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   wire                      tck_pad_i;
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   wire                      tms_pad_i;
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   wire                      tdi_pad_i;
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`endif
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`ifdef UART0
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   wire                      uart0_stx_pad_o;
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   wire                      uart0_srx_pad_i;
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`endif
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   orpsoc_top dut
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     (
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      .clk_pad_i                        (clk),
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`ifdef JTAG_DEBUG
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      .tms_pad_i                        (tms_pad_i),
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      .tck_pad_i                        (tck_pad_i),
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      .tdi_pad_i                        (tdi_pad_i),
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      .tdo_pad_o                        (tdo_pad_o),
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`endif
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`ifdef UART0
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      .uart0_stx_pad_o                  (uart0_stx_pad_o),
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      .uart0_srx_pad_i                  (uart0_srx_pad_i),
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`endif
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      .rst_n_pad_i                      (rst_n)
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      );
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   //
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   // Instantiate OR1200 monitor
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   //
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   or1200_monitor monitor();
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`ifndef SIM_QUIET
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 `define CPU_ic_top or1200_ic_top
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 `define CPU_dc_top or1200_dc_top
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   wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en;
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   always @(posedge ic_en)
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     $display("Or1200 IC enabled at %t", $time);
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   wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en;
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   always @(posedge dc_en)
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     $display("Or1200 DC enabled at %t", $time);
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`endif
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`ifdef JTAG_DEBUG
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 `ifdef VPI_DEBUG
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   // Debugging interface
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   vpi_debug_module vpi_dbg
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     (
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      .tms(tms_pad_i),
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      .tck(tck_pad_i),
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      .tdi(tdi_pad_i),
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      .tdo(tdo_pad_o)
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      );
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 `else
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   // If no VPI debugging, tie off JTAG inputs
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   assign tdi_pad_i = 1;
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   assign tck_pad_i = 0;
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   assign tms_pad_i = 1;
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 `endif // !`ifdef VPI_DEBUG_ENABLE
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`endif //  `ifdef JTAG_DEBUG
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   initial
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     begin
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`ifndef SIM_QUIET
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        $display("\n* Starting simulation of ORPSoC RTL.\n* Test: %s\n",
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                 `TEST_NAME_STRING );
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`endif
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`ifdef VCD
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 `ifdef VCD_DELAY
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        #(`VCD_DELAY);
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 `endif
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        // Delay by x insns
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 `ifdef VCD_DELAY_INSNS
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        #10; // Delay until after the value becomes valid
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        while (monitor.insns < `VCD_DELAY_INSNS)
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          @(posedge clk);
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 `endif
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 `ifdef SIMULATOR_MODELSIM
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        // Modelsim can GZip VCDs on the fly if given in the suffix
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  `define VCD_SUFFIX   ".vcd.gz"
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 `else
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  `define VCD_SUFFIX   ".vcd"
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 `endif
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`ifndef SIM_QUIET
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        $display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
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`endif
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        $dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
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 `ifndef VCD_DEPTH
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  `define VCD_DEPTH 0
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 `endif
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        $dumpvars(`VCD_DEPTH);
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`endif
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   end // initial begin
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`ifdef END_TIME
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   initial begin
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      #(`END_TIME);
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`ifndef SIM_QUIET
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      $display("* Finish simulation due to END_TIME being set at %t", $time);
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`endif
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      $finish;
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   end
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`endif
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`ifdef END_INSNS
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   initial begin
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      #10
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        while (monitor.insns < `END_INSNS)
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          @(posedge clk);
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 `ifndef SIM_QUIET
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      $display("* Finish simulation due to END_INSNS count (%d) reached at %t",
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               `END_INSNS, $time);
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 `endif
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      $finish;
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   end
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`endif
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`ifdef UART0
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   //   
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   // UART0 decoder
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   //   
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   uart_decoder
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     #(
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        .uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
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        )
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   uart0_decoder
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     (
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      .clk(clk),
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      .uart_tx(uart0_stx_pad_o)
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      );
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   // UART0 stimulus
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   /*
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   uart_stim
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     #(
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        .uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
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        )
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   uart0_stim
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     (
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      .clk(clk),
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      .uart_rx(uart0_srx_pad_i)
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      );
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    */
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   // UART0 is looped back for now
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   assign uart0_srx_pad_i = uart0_stx_pad_o;
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`endif //  `ifdef UART0
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endmodule // orpsoc_testbench
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// Local Variables:
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// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")
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// verilog-library-files:()
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// verilog-library-extensions:(".v" ".h")
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// End:
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