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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [orpsoc_testbench.v] - Blame information for rev 383

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//////////////////////////////////////////////////////////////////////
///                                                               //// 
/// ORPSoC testbench                                              ////
///                                                               ////
/// Instantiate ORPSoC, monitors, provide stimulus                ////
///                                                               ////
/// Julius Baxter, julius@opencores.org                           ////
///                                                               ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "orpsoc-defines.v"
`include "orpsoc-testbench-defines.v"
`include "test-defines.v"
 
`include "timescale.v"
 
module orpsoc_testbench;
 
   reg clk = 0;
   reg rst_n = 1; // Active LOW
 
   always
     #((`BOARD_CLOCK_PERIOD_NS)/2) clk <= ~clk;
 
   // Reset, ACTIVE LOW
   initial
     begin
        #1;
        repeat (32) @(negedge clk)
          rst_n <= 1;
        repeat (32) @(negedge clk)
          rst_n <= 0;
        repeat (32) @(negedge clk)
          rst_n <= 1;
     end
 
`include "orpsoc-params.v"
 
`ifdef JTAG_DEBUG
   wire                      tdo_pad_o;
   wire                      tck_pad_i;
   wire                      tms_pad_i;
   wire                      tdi_pad_i;
`endif
`ifdef UART0
   wire                      uart0_stx_pad_o;
   wire                      uart0_srx_pad_i;
`endif
 
   orpsoc_top dut
     (
      .clk_pad_i                        (clk),
`ifdef JTAG_DEBUG
      .tms_pad_i                        (tms_pad_i),
      .tck_pad_i                        (tck_pad_i),
      .tdi_pad_i                        (tdi_pad_i),
      .tdo_pad_o                        (tdo_pad_o),
`endif
`ifdef UART0
      .uart0_stx_pad_o                  (uart0_stx_pad_o),
      .uart0_srx_pad_i                  (uart0_srx_pad_i),
`endif
      .rst_n_pad_i                      (rst_n)
      );
 
   //
   // Instantiate OR1200 monitor
   //
   or1200_monitor monitor();
 
`ifndef SIM_QUIET
 `define CPU_ic_top or1200_ic_top
 `define CPU_dc_top or1200_dc_top
   wire ic_en = orpsoc_testbench.dut.or1200_top.or1200_ic_top.ic_en;
   always @(posedge ic_en)
     $display("Or1200 IC enabled at %t", $time);
 
   wire dc_en = orpsoc_testbench.dut.or1200_top.or1200_dc_top.dc_en;
   always @(posedge dc_en)
     $display("Or1200 DC enabled at %t", $time);
`endif
 
 
`ifdef JTAG_DEBUG
 `ifdef VPI_DEBUG
   // Debugging interface
   vpi_debug_module vpi_dbg
     (
      .tms(tms_pad_i),
      .tck(tck_pad_i),
      .tdi(tdi_pad_i),
      .tdo(tdo_pad_o)
      );
 `else
   // If no VPI debugging, tie off JTAG inputs
   assign tdi_pad_i = 1;
   assign tck_pad_i = 0;
   assign tms_pad_i = 1;
 `endif // !`ifdef VPI_DEBUG_ENABLE
`endif //  `ifdef JTAG_DEBUG
 
 
   initial
     begin
`ifndef SIM_QUIET
        $display("\n* Starting simulation of design RTL.\n* Test: %s\n",
                 `TEST_NAME_STRING );
`endif
 
`ifdef VCD
 `ifdef VCD_DELAY
        #(`VCD_DELAY);
 `endif
 
        // Delay by x insns
 `ifdef VCD_DELAY_INSNS
        #10; // Delay until after the value becomes valid
        while (monitor.insns < `VCD_DELAY_INSNS)
          @(posedge clk);
 `endif
 
 `ifdef SIMULATOR_MODELSIM
        // Modelsim can GZip VCDs on the fly if given in the suffix
  `define VCD_SUFFIX   ".vcd.gz"
 `else
  `define VCD_SUFFIX   ".vcd"
 `endif
 
`ifndef SIM_QUIET
        $display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
`endif
        $dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
 `ifndef VCD_DEPTH
  `define VCD_DEPTH 0
 `endif
        $dumpvars(`VCD_DEPTH);
`endif
 
   end // initial begin
 
`ifdef END_TIME
   initial begin
      #(`END_TIME);
`ifndef SIM_QUIET
      $display("* Finish simulation due to END_TIME being set at %t", $time);
`endif
      $finish;
   end
`endif
 
`ifdef END_INSNS
   initial begin
      #10
        while (monitor.insns < `END_INSNS)
          @(posedge clk);
 `ifndef SIM_QUIET
      $display("* Finish simulation due to END_INSNS count (%d) reached at %t",
               `END_INSNS, $time);
 `endif
      $finish;
   end
`endif
 
`ifdef UART0
   //   
   // UART0 decoder
   //   
   uart_decoder
     #(
        .uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
        )
   uart0_decoder
     (
      .clk(clk),
      .uart_tx(uart0_stx_pad_o)
      );
 
   // UART0 stimulus
   uart_stim
     #(
        .uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS
        )
   uart0_stim
     (
      .clk(clk),
      .uart_rx(uart0_srx_pad_i)
      );
 
`endif //  `ifdef UART0
 
endmodule // orpsoc_testbench
 
// Local Variables:
// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")
// verilog-library-files:()
// verilog-library-extensions:(".v" ".h")
// End:
 

Line No.	Rev	Author	Line
1	6	julius	`//////////////////////////////////////////////////////////////////////`
2	360	julius	`/// ////`
3			`/// ORPSoC testbench ////`
4			`/// ////`
5			`/// Instantiate ORPSoC, monitors, provide stimulus ////`
6			`/// ////`
7			`/// Julius Baxter, julius@opencores.org ////`
8			`/// ////`
9	6	julius	`//////////////////////////////////////////////////////////////////////`
10			`//// ////`
11	360	julius	`//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////`
12	6	julius	`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer. ////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation; ////`
21			`//// either version 2.1 of the License, or (at your option) any ////`
22			`//// later version. ////`
23			`//// ////`
24			`//// This source is distributed in the hope that it will be ////`
25			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
26			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
27			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
28			`//// details. ////`
29			`//// ////`
30			`//// You should have received a copy of the GNU Lesser General ////`
31			`//// Public License along with this source; if not, download it ////`
32			`//// from http://www.opencores.org/lgpl.shtml ////`
33			`//// ////`
34			`//////////////////////////////////////////////////////////////////////`
35
36	360	julius	`include "orpsoc-defines.v"
37			`include "orpsoc-testbench-defines.v"
38			`include "test-defines.v"
39
40	6	julius	`include "timescale.v"
41
42	360	julius	`module orpsoc_testbench;`
43
44			`reg clk = 0;`
45			`reg rst_n = 1; // Active LOW`
46	6	julius
47	360	julius	`always`
48			#((`BOARD_CLOCK_PERIOD_NS)/2) clk <= ~clk;
49	6	julius
50	360	julius	`// Reset, ACTIVE LOW`
51	6	julius	`initial`
52			`begin`
53	360	julius	`#1;`
54			`repeat (32) @(negedge clk)`
55			`rst_n <= 1;`
56			`repeat (32) @(negedge clk)`
57			`rst_n <= 0;`
58			`repeat (32) @(negedge clk)`
59			`rst_n <= 1;`
60	6	julius	`end`
61
62	360	julius	`include "orpsoc-params.v"
63	6	julius
64	360	julius	`ifdef JTAG_DEBUG
65			`wire tdo_pad_o;`
66			`wire tck_pad_i;`
67			`wire tms_pad_i;`
68			`wire tdi_pad_i;`
69			`endif
70			`ifdef UART0
71			`wire uart0_stx_pad_o;`
72			`wire uart0_srx_pad_i;`
73	6	julius	`endif
74
75	360	julius	`orpsoc_top dut`
76			`(`
77			`.clk_pad_i (clk),`
78			`ifdef JTAG_DEBUG
79			`.tms_pad_i (tms_pad_i),`
80			`.tck_pad_i (tck_pad_i),`
81			`.tdi_pad_i (tdi_pad_i),`
82			`.tdo_pad_o (tdo_pad_o),`
83			`endif
84			`ifdef UART0
85			`.uart0_stx_pad_o (uart0_stx_pad_o),`
86			`.uart0_srx_pad_i (uart0_srx_pad_i),`
87			`endif
88			`.rst_n_pad_i (rst_n)`
89			`);`
90	6	julius
91	360	julius	`//`
92			`// Instantiate OR1200 monitor`
93			`//`
94			`or1200_monitor monitor();`
95	6	julius
96	360	julius	`ifndef SIM_QUIET
97			`define CPU_ic_top or1200_ic_top
98			`define CPU_dc_top or1200_dc_top
99			`wire ic_en = orpsoc_testbench.dut.or1200_top.or1200_ic_top.ic_en;`
100			`always @(posedge ic_en)`
101			`$display("Or1200 IC enabled at %t", $time);`
102	6	julius
103	360	julius	`wire dc_en = orpsoc_testbench.dut.or1200_top.or1200_dc_top.dc_en;`
104			`always @(posedge dc_en)`
105			`$display("Or1200 DC enabled at %t", $time);`
106			`endif
107	6	julius
108
109	360	julius	`ifdef JTAG_DEBUG
110			`ifdef VPI_DEBUG
111	40	julius	`// Debugging interface`
112	360	julius	`vpi_debug_module vpi_dbg`
113	6	julius	`(`
114	360	julius	`.tms(tms_pad_i),`
115			`.tck(tck_pad_i),`
116			`.tdi(tdi_pad_i),`
117			`.tdo(tdo_pad_o)`
118	6	julius	`);`
119	360	julius	`else
120			`// If no VPI debugging, tie off JTAG inputs`
121			`assign tdi_pad_i = 1;`
122			`assign tck_pad_i = 0;`
123			`assign tms_pad_i = 1;`
124			`endif // !`ifdef VPI_DEBUG_ENABLE
125			`endif // `ifdef JTAG_DEBUG
126	44	julius
127
128	360	julius	`initial`
129			`begin`
130			`ifndef SIM_QUIET
131			`$display("\n* Starting simulation of design RTL.\n* Test: %s\n",`
132			`TEST_NAME_STRING );
133			`endif
134	44	julius
135	360	julius	`ifdef VCD
136			`ifdef VCD_DELAY
137			#(`VCD_DELAY);
138			`endif
139	44	julius
140	360	julius	`// Delay by x insns`
141			`ifdef VCD_DELAY_INSNS
142			`#10; // Delay until after the value becomes valid`
143			while (monitor.insns < `VCD_DELAY_INSNS)
144			`@(posedge clk);`
145			`endif
146
147			`ifdef SIMULATOR_MODELSIM
148			`// Modelsim can GZip VCDs on the fly if given in the suffix`
149			`define VCD_SUFFIX ".vcd.gz"
150			`else
151			`define VCD_SUFFIX ".vcd"
152			`endif
153
154			`ifndef SIM_QUIET
155			$display("* VCD in %s\n", {"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
156			`endif
157			$dumpfile({"../out/",`TEST_NAME_STRING,`VCD_SUFFIX});
158			`ifndef VCD_DEPTH
159			`define VCD_DEPTH 0
160			`endif
161			$dumpvars(`VCD_DEPTH);
162	44	julius	`endif
163	360	julius
164			`end // initial begin`
165	44	julius
166	360	julius	`ifdef END_TIME
167			`initial begin`
168			#(`END_TIME);
169			`ifndef SIM_QUIET
170			`$display("* Finish simulation due to END_TIME being set at %t", $time);`
171			`endif
172			`$finish;`
173			`end`
174	6	julius	`endif
175
176	360	julius	`ifdef END_INSNS
177			`initial begin`
178			`#10`
179			while (monitor.insns < `END_INSNS)
180			`@(posedge clk);`
181			`ifndef SIM_QUIET
182			`$display("* Finish simulation due to END_INSNS count (%d) reached at %t",`
183			`END_INSNS, $time);
184			`endif
185			`$finish;`
186			`end`
187			`endif
188
189			`ifdef UART0
190			`//`
191			`// UART0 decoder`
192			`//`
193	354	julius	`uart_decoder`
194			`#(`
195	360	julius	`.uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS`
196			`)`
197	354	julius	`uart0_decoder`
198			`(`
199			`.clk(clk),`
200	360	julius	`.uart_tx(uart0_stx_pad_o)`
201	354	julius	`);`
202	6	julius
203	360	julius	`// UART0 stimulus`
204			`uart_stim`
205			`#(`
206			`.uart_baudrate_period_ns(8680) // 115200 baud = period 8.68uS`
207			`)`
208			`uart0_stim`
209			`(`
210			`.clk(clk),`
211			`.uart_rx(uart0_srx_pad_i)`
212			`);`
213
214			`endif // `ifdef UART0
215
216	6	julius	`endmodule // orpsoc_testbench`
217
218			`// Local Variables:`
219	360	julius	`// verilog-library-directories:("." "../../rtl/verilog/orpsoc_top")`
220			`// verilog-library-files:()`
221			`// verilog-library-extensions:(".v" ".h")`
222	49	julius	`// End:`
223	360	julius

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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [orpsoc_testbench.v] - Blame information for rev 383