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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [uart_decoder.v] - Blame information for rev 856

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  ORPSoC Testbench UART Decoder                               ////
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////                                                              ////
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////  Description                                                 ////
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////  ORPSoC Testbench UART output decoder                        ////
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////                                                              ////
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////  To Do:                                                      ////
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////                                                              ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - jb, jb@orsoc.se                                       ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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// Receieves and decodes 8-bit,  1 stop bit, no parity UART signals.
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`timescale 1ns/1ns
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module uart_decoder(clk, uart_tx);
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   input clk;
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   input uart_tx;
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   // Default baud of 115200, period (ns)
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   parameter uart_baudrate_period_ns = 8680;
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   // Something to trigger the task
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   always @(posedge clk)
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     uart_decoder;
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   task uart_decoder;
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      reg [7:0] tx_byte;
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      begin
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         while (uart_tx !== 1'b1)
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           @(uart_tx);
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         // Wait for start bit
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         while (uart_tx !== 1'b0)
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           @(uart_tx);
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         #(uart_baudrate_period_ns+(uart_baudrate_period_ns/2));
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         tx_byte[0] = uart_tx;
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         #uart_baudrate_period_ns;
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         tx_byte[1] = uart_tx;
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         #uart_baudrate_period_ns;
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         tx_byte[2] = uart_tx;
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         #uart_baudrate_period_ns;
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         tx_byte[3] = uart_tx;
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         #uart_baudrate_period_ns;
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         tx_byte[4] = uart_tx;
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         #uart_baudrate_period_ns;
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         tx_byte[5] = uart_tx;
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         #uart_baudrate_period_ns;
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         tx_byte[6] = uart_tx;
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         #uart_baudrate_period_ns;
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         tx_byte[7] = uart_tx;
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         #uart_baudrate_period_ns;
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         //Check for stop bit
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         if (uart_tx !== 1'b1)
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           begin
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              // Wait for return to idle
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              while (uart_tx !== 1'b1)
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                @(uart_tx);
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           end
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         // display the char
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         $write("%c", tx_byte);
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      end
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   endtask // user_uart_read_byte
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endmodule // uart_decoder

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