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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [uart_stim.v] - Blame information for rev 408

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1 361 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  ORPSoC Testbench UART Stimulus                              ////
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////                                                              ////
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////  Description                                                 ////
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////  ORPSoC Testbench UART input generator                       ////
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////                                                              ////
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////  To Do:                                                      ////
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////                                                              ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - jb, jb@orsoc.se                                       ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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// Encodes 8-bit, 1 stop bit, no parity UART signals at 115200 buad
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`timescale 1ns/1ns
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module uart_stim(clk, uart_rx);
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   input clk;
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   output reg uart_rx;
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   // Default baud of 115200, period (ns)
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   parameter uart_baudrate_period_ns = 8680;
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   // Uart Stim file - we include it
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   parameter stim_file = "uart0_stim.v";
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   // Something to trigger the task
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   reg [7:0]  next_byte;
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   parameter len = 11; // Number of chars in string
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   reg [(len*8)-1:0] uart_string;
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   integer      i;
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   /*
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   initial
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     begin
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        uart_rx = 1;
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        uart_string = "dhry 100\n!\n";
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        #12_000_000;
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        for(i=0;i<len;i=i+1)
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          begin
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             uart_tx_byte(uart_string[(len*8)-1:(len*8)-8]);
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             #20_000_000;
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             // Shift along string
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             uart_string = {uart_string[(len*8)-9:0],8'h00};
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          end
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     end
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    */
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   // Task to drive UART RX line (transmit a char) - 1 stop bit, no parity
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   task uart_tx_byte;
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    input [7:0] tx_byte;
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      begin
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         // Start bit
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         uart_rx = 1'b0;
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         #uart_baudrate_period_ns;
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         uart_rx = tx_byte[0];
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         #uart_baudrate_period_ns;
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         uart_rx = tx_byte[1];
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         #uart_baudrate_period_ns;
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         uart_rx = tx_byte[2];
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         #uart_baudrate_period_ns;
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         uart_rx = tx_byte[3];
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         #uart_baudrate_period_ns;
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         uart_rx = tx_byte[4];
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         #uart_baudrate_period_ns;
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         uart_rx = tx_byte[5];
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         #uart_baudrate_period_ns;
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         uart_rx = tx_byte[6];
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         #uart_baudrate_period_ns;
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         uart_rx = tx_byte[7];
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         #uart_baudrate_period_ns;
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         // Stop bit
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         uart_rx = 1'b1;
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         #uart_baudrate_period_ns;
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      end
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   endtask // uart_tx_byte
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endmodule // uart_decoder

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