URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [SIEReceiver_simlib.v] - Blame information for rev 811

Go to most recent revision | Details | Compare with Previous | View Log


 
// File        : ../RTL/serialInterfaceEngine/siereceiver.v
// Generated   : 11/10/06 05:37:23
// From        : ../RTL/serialInterfaceEngine/siereceiver.asf
// By          : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// SIEReceiver
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
 
 
module SIEReceiver_simlib (RxWireDataIn, RxWireDataWEn, clk, connectState, rst);
input   [1:0] RxWireDataIn;
input   RxWireDataWEn;
input   clk;
input   rst;
output  [1:0] connectState;
 
wire    [1:0] RxWireDataIn;
wire    RxWireDataWEn;
wire    clk;
reg     [1:0] connectState, next_connectState;
wire    rst;
 
// diagram signals declarations
reg  [3:0]RXStMachCurrState, next_RXStMachCurrState;
reg  [7:0]RXWaitCount, next_RXWaitCount;
reg  [1:0]RxBits, next_RxBits;
 
// BINARY ENCODED state machine: rcvr
// State codes definitions:
`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
`define LS_CONN_CHK_RX_BITS 4'b0010
`define DISCNCT_CHK_RXBITS 4'b0011
`define WAIT_BIT 4'b0100
`define START_SRX 4'b0101
`define FS_CONN_CHK_RX_BITS1 4'b0110
`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111
`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000
 
reg [3:0] CurrState_rcvr;
reg [3:0] NextState_rcvr;
 
 
//--------------------------------------------------------------------
// Machine: rcvr
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (RxWireDataIn or RxBits or RXWaitCount or RxWireDataWEn or RXStMachCurrState or connectState or CurrState_rcvr)
begin : rcvr_NextState
  NextState_rcvr <= CurrState_rcvr;
  // Set default values for outputs and signals
  next_RxBits <= RxBits;
  next_RXStMachCurrState <= RXStMachCurrState;
  next_RXWaitCount <= RXWaitCount;
  next_connectState <= connectState;
  case (CurrState_rcvr)
    `WAIT_BIT:
      if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
      begin
        NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
        next_RxBits <= RxWireDataIn;
      end
      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
      begin
        NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
        next_RxBits <= RxWireDataIn;
      end
      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
      begin
        NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
        next_RxBits <= RxWireDataIn;
      end
      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
      begin
        NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
        next_RxBits <= RxWireDataIn;
      end
      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
      begin
        NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
        next_RxBits <= RxWireDataIn;
      end
      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
      begin
        NextState_rcvr <= `DISCNCT_CHK_RXBITS;
        next_RxBits <= RxWireDataIn;
      end
      else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
      begin
        NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
        next_RxBits <= RxWireDataIn;
      end
    `START_SRX:
    begin
      next_RXStMachCurrState <= `DISCONNECT_ST;
      next_RXWaitCount <= 8'h00;
      next_connectState <= `DISCONNECT;
      next_RxBits <= 2'b00;
      NextState_rcvr <= `WAIT_BIT;
    end
    `DISCNCT_CHK_RXBITS:
      if (RxBits == `ZERO_ONE)
      begin
        NextState_rcvr <= `WAIT_BIT;
        next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
        next_RXWaitCount <= 8'h00;
      end
      else if (RxBits == `ONE_ZERO)
      begin
        NextState_rcvr <= `WAIT_BIT;
        next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
        next_RXWaitCount <= 8'h00;
      end
      else
        NextState_rcvr <= `WAIT_BIT;
    `WAIT_FS_CONN_CHK_RX_BITS:
    begin
      if (RxBits == `ONE_ZERO)
      begin
        next_RXWaitCount <= RXWaitCount + 1'b1;
          if (RXWaitCount == `CONNECT_WAIT_TIME)
          begin
          next_connectState <= `FULL_SPEED_CONNECT;
          next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
          end
      end
      else
      begin
        next_RXStMachCurrState <= `DISCONNECT_ST;
      end
      NextState_rcvr <= `WAIT_BIT;
    end
    `WAIT_LS_CONN_CHK_RX_BITS:
    begin
      if (RxBits == `ZERO_ONE)
      begin
        next_RXWaitCount <= RXWaitCount + 1'b1;
          if (RXWaitCount == `CONNECT_WAIT_TIME)
          begin
          next_connectState <= `LOW_SPEED_CONNECT;
          next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
          end
      end
      else
      begin
        next_RXStMachCurrState <= `DISCONNECT_ST;
      end
      NextState_rcvr <= `WAIT_BIT;
    end
    `LS_CONN_CHK_RX_BITS:
    begin
      NextState_rcvr <= `WAIT_BIT;
      if (RxBits == `SE0)
      begin
        next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
        next_RXWaitCount <= 0;
      end
    end
    `FS_CONN_CHK_RX_BITS1:
    begin
      NextState_rcvr <= `WAIT_BIT;
      if (RxBits == `SE0)
      begin
        next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
        next_RXWaitCount <= 0;
      end
    end
    `WAIT_LS_DIS_CHK_RX_BITS:
    begin
      NextState_rcvr <= `WAIT_BIT;
      if (RxBits == `SE0)
      begin
        next_RXWaitCount <= RXWaitCount + 1'b1;
          if (RXWaitCount == `DISCONNECT_WAIT_TIME)
          begin
          next_RXStMachCurrState <= `DISCONNECT_ST;
          next_connectState <= `DISCONNECT;
          end
      end
      else
      begin
        next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
      end
    end
    `WAIT_FS_DIS_CHK_RX_BITS2:
    begin
      NextState_rcvr <= `WAIT_BIT;
      if (RxBits == `SE0)
      begin
        next_RXWaitCount <= RXWaitCount + 1'b1;
          if (RXWaitCount == `DISCONNECT_WAIT_TIME)
          begin
          next_RXStMachCurrState <= `DISCONNECT_ST;
          next_connectState <= `DISCONNECT;
          end
      end
      else
      begin
        next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
      end
    end
  endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : rcvr_CurrentState
  if (rst)
    CurrState_rcvr <= `START_SRX;
  else
    CurrState_rcvr <= NextState_rcvr;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : rcvr_RegOutput
  if (rst)
  begin
    RXStMachCurrState <= `DISCONNECT_ST;
    RXWaitCount <= 8'h00;
    RxBits <= 2'b00;
    connectState <= `DISCONNECT;
  end
  else
  begin
    RXStMachCurrState <= next_RXStMachCurrState;
    RXWaitCount <= next_RXWaitCount;
    RxBits <= next_RxBits;
    connectState <= next_connectState;
  end
end
 
endmodule

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [verilog/] [usbhostslave/] [SIEReceiver_simlib.v] - Blame information for rev 811

Line No.	Rev	Author	Line
1	408	julius
2			`// File : ../RTL/serialInterfaceEngine/siereceiver.v`
3			`// Generated : 11/10/06 05:37:23`
4			`// From : ../RTL/serialInterfaceEngine/siereceiver.asf`
5			`// By : FSM2VHDL ver. 5.0.0.9`
6
7			`//////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// SIEReceiver`
10			`//// ////`
11			`//// This file is part of the usbhostslave opencores effort.`
12			`//// http://www.opencores.org/cores/usbhostslave/ ////`
13			`//// ////`
14			`//// Module Description: ////`
15			`////`
16			`//// ////`
17			`//// To Do: ////`
18			`////`
19			`//// ////`
20			`//// Author(s): ////`
21			`//// - Steve Fielding, sfielding@base2designs.com ////`
22			`//// ////`
23			`//////////////////////////////////////////////////////////////////////`
24			`//// ////`
25			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
26			`//// ////`
27			`//// This source file may be used and distributed without ////`
28			`//// restriction provided that this copyright statement is not ////`
29			`//// removed from the file and that any derivative work contains ////`
30			`//// the original copyright notice and the associated disclaimer. ////`
31			`//// ////`
32			`//// This source file is free software; you can redistribute it ////`
33			`//// and/or modify it under the terms of the GNU Lesser General ////`
34			`//// Public License as published by the Free Software Foundation; ////`
35			`//// either version 2.1 of the License, or (at your option) any ////`
36			`//// later version. ////`
37			`//// ////`
38			`//// This source is distributed in the hope that it will be ////`
39			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
40			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
41			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
42			`//// details. ////`
43			`//// ////`
44			`//// You should have received a copy of the GNU Lesser General ////`
45			`//// Public License along with this source; if not, download it ////`
46			`//// from http://www.opencores.org/lgpl.shtml ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`include "timescale.v"
51			`include "usbSerialInterfaceEngine_h.v"
52
53
54			`module SIEReceiver_simlib (RxWireDataIn, RxWireDataWEn, clk, connectState, rst);`
55			`input [1:0] RxWireDataIn;`
56			`input RxWireDataWEn;`
57			`input clk;`
58			`input rst;`
59			`output [1:0] connectState;`
60
61			`wire [1:0] RxWireDataIn;`
62			`wire RxWireDataWEn;`
63			`wire clk;`
64			`reg [1:0] connectState, next_connectState;`
65			`wire rst;`
66
67			`// diagram signals declarations`
68			`reg [3:0]RXStMachCurrState, next_RXStMachCurrState;`
69			`reg [7:0]RXWaitCount, next_RXWaitCount;`
70			`reg [1:0]RxBits, next_RxBits;`
71
72			`// BINARY ENCODED state machine: rcvr`
73			`// State codes definitions:`
74			`define WAIT_FS_CONN_CHK_RX_BITS 4'b0000
75			`define WAIT_LS_CONN_CHK_RX_BITS 4'b0001
76			`define LS_CONN_CHK_RX_BITS 4'b0010
77			`define DISCNCT_CHK_RXBITS 4'b0011
78			`define WAIT_BIT 4'b0100
79			`define START_SRX 4'b0101
80			`define FS_CONN_CHK_RX_BITS1 4'b0110
81			`define WAIT_LS_DIS_CHK_RX_BITS 4'b0111
82			`define WAIT_FS_DIS_CHK_RX_BITS2 4'b1000
83
84			`reg [3:0] CurrState_rcvr;`
85			`reg [3:0] NextState_rcvr;`
86
87
88			`//--------------------------------------------------------------------`
89			`// Machine: rcvr`
90			`//--------------------------------------------------------------------`
91			`//----------------------------------`
92			`// Next State Logic (combinatorial)`
93			`//----------------------------------`
94			`always @ (RxWireDataIn or RxBits or RXWaitCount or RxWireDataWEn or RXStMachCurrState or connectState or CurrState_rcvr)`
95			`begin : rcvr_NextState`
96			`NextState_rcvr <= CurrState_rcvr;`
97			`// Set default values for outputs and signals`
98			`next_RxBits <= RxBits;`
99			`next_RXStMachCurrState <= RXStMachCurrState;`
100			`next_RXWaitCount <= RXWaitCount;`
101			`next_connectState <= connectState;`
102			`case (CurrState_rcvr)`
103			`WAIT_BIT:
104			if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SPEED_CONN_ST))
105			`begin`
106			NextState_rcvr <= `WAIT_LS_CONN_CHK_RX_BITS;
107			`next_RxBits <= RxWireDataIn;`
108			`end`
109			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_LOW_SPEED_ST))
110			`begin`
111			NextState_rcvr <= `LS_CONN_CHK_RX_BITS;
112			`next_RxBits <= RxWireDataIn;`
113			`end`
114			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `CONNECT_FULL_SPEED_ST))
115			`begin`
116			NextState_rcvr <= `FS_CONN_CHK_RX_BITS1;
117			`next_RxBits <= RxWireDataIn;`
118			`end`
119			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_LOW_SP_DISCONNECT_ST))
120			`begin`
121			NextState_rcvr <= `WAIT_LS_DIS_CHK_RX_BITS;
122			`next_RxBits <= RxWireDataIn;`
123			`end`
124			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SP_DISCONNECT_ST))
125			`begin`
126			NextState_rcvr <= `WAIT_FS_DIS_CHK_RX_BITS2;
127			`next_RxBits <= RxWireDataIn;`
128			`end`
129			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `DISCONNECT_ST))
130			`begin`
131			NextState_rcvr <= `DISCNCT_CHK_RXBITS;
132			`next_RxBits <= RxWireDataIn;`
133			`end`
134			else if ((RxWireDataWEn == 1'b1) && (RXStMachCurrState == `WAIT_FULL_SPEED_CONN_ST))
135			`begin`
136			NextState_rcvr <= `WAIT_FS_CONN_CHK_RX_BITS;
137			`next_RxBits <= RxWireDataIn;`
138			`end`
139			`START_SRX:
140			`begin`
141			next_RXStMachCurrState <= `DISCONNECT_ST;
142			`next_RXWaitCount <= 8'h00;`
143			next_connectState <= `DISCONNECT;
144			`next_RxBits <= 2'b00;`
145			NextState_rcvr <= `WAIT_BIT;
146			`end`
147			`DISCNCT_CHK_RXBITS:
148			if (RxBits == `ZERO_ONE)
149			`begin`
150			NextState_rcvr <= `WAIT_BIT;
151			next_RXStMachCurrState <= `WAIT_LOW_SPEED_CONN_ST;
152			`next_RXWaitCount <= 8'h00;`
153			`end`
154			else if (RxBits == `ONE_ZERO)
155			`begin`
156			NextState_rcvr <= `WAIT_BIT;
157			next_RXStMachCurrState <= `WAIT_FULL_SPEED_CONN_ST;
158			`next_RXWaitCount <= 8'h00;`
159			`end`
160			`else`
161			NextState_rcvr <= `WAIT_BIT;
162			`WAIT_FS_CONN_CHK_RX_BITS:
163			`begin`
164			if (RxBits == `ONE_ZERO)
165			`begin`
166			`next_RXWaitCount <= RXWaitCount + 1'b1;`
167			if (RXWaitCount == `CONNECT_WAIT_TIME)
168			`begin`
169			next_connectState <= `FULL_SPEED_CONNECT;
170			next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
171			`end`
172			`end`
173			`else`
174			`begin`
175			next_RXStMachCurrState <= `DISCONNECT_ST;
176			`end`
177			NextState_rcvr <= `WAIT_BIT;
178			`end`
179			`WAIT_LS_CONN_CHK_RX_BITS:
180			`begin`
181			if (RxBits == `ZERO_ONE)
182			`begin`
183			`next_RXWaitCount <= RXWaitCount + 1'b1;`
184			if (RXWaitCount == `CONNECT_WAIT_TIME)
185			`begin`
186			next_connectState <= `LOW_SPEED_CONNECT;
187			next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
188			`end`
189			`end`
190			`else`
191			`begin`
192			next_RXStMachCurrState <= `DISCONNECT_ST;
193			`end`
194			NextState_rcvr <= `WAIT_BIT;
195			`end`
196			`LS_CONN_CHK_RX_BITS:
197			`begin`
198			NextState_rcvr <= `WAIT_BIT;
199			if (RxBits == `SE0)
200			`begin`
201			next_RXStMachCurrState <= `WAIT_LOW_SP_DISCONNECT_ST;
202			`next_RXWaitCount <= 0;`
203			`end`
204			`end`
205			`FS_CONN_CHK_RX_BITS1:
206			`begin`
207			NextState_rcvr <= `WAIT_BIT;
208			if (RxBits == `SE0)
209			`begin`
210			next_RXStMachCurrState <= `WAIT_FULL_SP_DISCONNECT_ST;
211			`next_RXWaitCount <= 0;`
212			`end`
213			`end`
214			`WAIT_LS_DIS_CHK_RX_BITS:
215			`begin`
216			NextState_rcvr <= `WAIT_BIT;
217			if (RxBits == `SE0)
218			`begin`
219			`next_RXWaitCount <= RXWaitCount + 1'b1;`
220			if (RXWaitCount == `DISCONNECT_WAIT_TIME)
221			`begin`
222			next_RXStMachCurrState <= `DISCONNECT_ST;
223			next_connectState <= `DISCONNECT;
224			`end`
225			`end`
226			`else`
227			`begin`
228			next_RXStMachCurrState <= `CONNECT_LOW_SPEED_ST;
229			`end`
230			`end`
231			`WAIT_FS_DIS_CHK_RX_BITS2:
232			`begin`
233			NextState_rcvr <= `WAIT_BIT;
234			if (RxBits == `SE0)
235			`begin`
236			`next_RXWaitCount <= RXWaitCount + 1'b1;`
237			if (RXWaitCount == `DISCONNECT_WAIT_TIME)
238			`begin`
239			next_RXStMachCurrState <= `DISCONNECT_ST;
240			next_connectState <= `DISCONNECT;
241			`end`
242			`end`
243			`else`
244			`begin`
245			next_RXStMachCurrState <= `CONNECT_FULL_SPEED_ST;
246			`end`
247			`end`
248			`endcase`
249			`end`
250
251			`//----------------------------------`
252			`// Current State Logic (sequential)`
253			`//----------------------------------`
254			`always @ (posedge clk)`
255			`begin : rcvr_CurrentState`
256			`if (rst)`
257			CurrState_rcvr <= `START_SRX;
258			`else`
259			`CurrState_rcvr <= NextState_rcvr;`
260			`end`
261
262			`//----------------------------------`
263			`// Registered outputs logic`
264			`//----------------------------------`
265			`always @ (posedge clk)`
266			`begin : rcvr_RegOutput`
267			`if (rst)`
268			`begin`
269			RXStMachCurrState <= `DISCONNECT_ST;
270			`RXWaitCount <= 8'h00;`
271			`RxBits <= 2'b00;`
272			connectState <= `DISCONNECT;
273			`end`
274			`else`
275			`begin`
276			`RXStMachCurrState <= next_RXStMachCurrState;`
277			`RXWaitCount <= next_RXWaitCount;`
278			`RxBits <= next_RxBits;`
279			`connectState <= next_connectState;`
280			`end`
281			`end`
282
283			`endmodule`